Add support for M340 part.
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Nick Clifton
parent
bec504668f
commit
97ee9b94b2
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@ -1,3 +1,14 @@
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2000-02-10 Nick Clifton <nickc@cygnus.com>
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* mcore-opc.h (enum mcore_opclass): Add MULSH and OPSR
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classes.
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(mcore_table): Add "idly4", "psrclr", "psrset", "mulsh" and
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"mulsh.h" instructions.
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* mcore-dis.c (imsk array): Add masks for MULSH and OPSR
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classes.
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(print_insn_mcore): Add support for little endian targets.
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Add support for MULSH and OPSR classes.
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2000-02-07 Nick Clifton <nickc@cygnus.com>
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* arm-dis.c (parse_arm_diassembler_option): Rename again.
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@ -1,5 +1,5 @@
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/* Disassemble Motorola M*Core instructions.
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Copyright (C) 1993, 1999 Free Software Foundation, Inc.
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Copyright (C) 1993, 1999, 2000 Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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@ -57,6 +57,9 @@ static const unsigned short imsk[] =
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/* OMc */ 0xFF00,
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/* SIa */ 0xFE00,
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/* MULSH */ 0xFF00,
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/* OPSR */ 0xFFF8, /* psrset/psrclr */
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/* JC */ 0, /* JC,JU,JL don't appear in object */
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/* JU */ 0,
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/* JL */ 0,
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@ -105,7 +108,12 @@ print_insn_mcore (memaddr, info)
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return -1;
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}
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if (info->endian == BFD_ENDIAN_BIG)
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inst = (ibytes[0] << 8) | ibytes[1];
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else if (info->endian == BFD_ENDIAN_LITTLE)
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inst = (ibytes[1] << 8) | ibytes[0];
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else
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abort ();
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/* Just a linear search of the table. */
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for (op = mcore_table; op->name != 0; op ++)
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@ -129,6 +137,7 @@ print_insn_mcore (memaddr, info)
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case JSR: fprintf (stream, "\t%s", name); break;
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case OC: fprintf (stream, "\t%s, %s", name, crname[(inst >> 4) & 0x1F]); break;
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case O1R1: fprintf (stream, "\t%s, r1", name); break;
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case MULSH:
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case O2: fprintf (stream, "\t%s, %s", name, grname[(inst >> 4) & 0xF]); break;
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case X1: fprintf (stream, "\tr1, %s", name); break;
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case OI: fprintf (stream, "\t%s, %d", name, ((inst >> 4) & 0x1F) + 1); break;
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@ -193,6 +202,10 @@ print_insn_mcore (memaddr, info)
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break;
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}
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if (info->endian == BFD_ENDIAN_LITTLE)
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val = (ibytes[3] << 24) | (ibytes[2] << 16)
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| (ibytes[1] << 8) | (ibytes[0]);
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else
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val = (ibytes[0] << 24) | (ibytes[1] << 16)
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| (ibytes[2] << 8) | (ibytes[3]);
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@ -218,6 +231,10 @@ print_insn_mcore (memaddr, info)
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break;
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}
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if (info->endian == BFD_ENDIAN_LITTLE)
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val = (ibytes[3] << 24) | (ibytes[2] << 16)
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| (ibytes[1] << 8) | (ibytes[0]);
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else
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val = (ibytes[0] << 24) | (ibytes[1] << 16)
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| (ibytes[2] << 8) | (ibytes[3]);
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@ -237,6 +254,18 @@ print_insn_mcore (memaddr, info)
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}
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break;
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case OPSR:
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{
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static char * fields[] =
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{
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"af", "ie", "fe", "fe,ie",
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"ee", "ee,ie", "ee,fe", "ee,fe,ie"
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};
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fprintf (stream, "\t%s", fields[inst & 0x7]);
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}
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break;
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default:
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/* if the disassembler lags the instruction set */
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fprintf (stream, "\tundecoded operands, inst is 0x%04x", inst);
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@ -1,5 +1,5 @@
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/* Assembler instructions for Motorola's Mcore processor
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Copyright (C) 1999 Free Software Foundation, Inc.
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Copyright (C) 1999, 2000 Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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@ -24,6 +24,7 @@ typedef enum
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OMa, SI, I7, LS, BR, BL, LR, LJ,
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RM, RQ, JSR, JMP, OBRa, OBRb, OBRc, OBR2,
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O1R1, OMb, OMc, SIa,
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MULSH, OPSR,
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JC, JU, JL, RSI, DO21, OB2
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}
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mcore_opclass;
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@ -48,6 +49,7 @@ mcore_opcode_info mcore_table[] =
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{ "stop", O0, 0, 0x0004 },
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{ "wait", O0, 0, 0x0005 },
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{ "doze", O0, 0, 0x0006 },
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{ "idly4", O0, 0, 0x0007 },
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{ "trap", OT, 0, 0x0008 },
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/* SPACE: 0x000C - 0x000F */
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/* SPACE: 0x0010 - 0x001F */
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@ -99,6 +101,8 @@ mcore_opcode_info mcore_table[] =
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{ "tst", O2, 0, 0x0E00 },
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{ "cmpne", O2, 0, 0x0F00 },
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{ "mfcr", OC, 0, 0x1000 },
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{ "psrclr", OPSR, 0, 0x11F0 },
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{ "psrset", OPSR, 0, 0x11F8 },
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{ "mov", O2, 0, 0x1200 },
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{ "bgenr", O2, 0, 0x1300 },
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{ "rsub", O2, 0, 0x1400 },
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@ -147,6 +151,8 @@ mcore_opcode_info mcore_table[] =
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{ "movi", I7, 0, 0x6000 },
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#define MCORE_INST_BMASKI_ALT 0x6000
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#define MCORE_INST_BGENI_ALT 0x6000
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{ "mulsh", MULSH, 0, 0x6800 },
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{ "muls.h", MULSH, 0, 0x6800 },
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/* SPACE: 0x6900 - 0x6FFF */
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{ "jmpi", LJ, 1, 0x7000 },
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{ "jsri", LJ, 0, 0x7F00 },
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