2002-02-11 Chris Demetriou <cgd@broadcom.com>
* mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment indicating that ALU32_END or ALU64_END are there to check for overflow. (DADD): Likewise, but also remove previous comment about overflow checking.
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@ -1,3 +1,11 @@
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2002-02-11 Chris Demetriou <cgd@broadcom.com>
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* mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
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indicating that ALU32_END or ALU64_END are there to check
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for overflow.
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(DADD): Likewise, but also remove previous comment about
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overflow checking.
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2002-02-10 Chris Demetriou <cgd@broadcom.com>
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2002-02-10 Chris Demetriou <cgd@broadcom.com>
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* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
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* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
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@ -237,7 +237,7 @@
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{
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{
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ALU32_BEGIN (GPR[RS]);
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ALU32_BEGIN (GPR[RS]);
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ALU32_ADD (GPR[RT]);
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ALU32_ADD (GPR[RT]);
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ALU32_END (GPR[RD]);
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ALU32_END (GPR[RD]); /* This checks for overflow. */
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}
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}
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TRACE_ALU_RESULT (GPR[RD]);
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TRACE_ALU_RESULT (GPR[RD]);
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}
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}
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@ -255,7 +255,7 @@
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{
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{
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ALU32_BEGIN (GPR[RS]);
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ALU32_BEGIN (GPR[RS]);
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ALU32_ADD (EXTEND16 (IMMEDIATE));
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ALU32_ADD (EXTEND16 (IMMEDIATE));
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ALU32_END (GPR[RT]);
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ALU32_END (GPR[RT]); /* This checks for overflow. */
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}
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}
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TRACE_ALU_RESULT (GPR[RT]);
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TRACE_ALU_RESULT (GPR[RT]);
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}
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}
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@ -709,12 +709,11 @@
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*vr4100:
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*vr4100:
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*vr5000:
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*vr5000:
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{
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{
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/* this check's for overflow */
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TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
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TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
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{
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{
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ALU64_BEGIN (GPR[RS]);
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ALU64_BEGIN (GPR[RS]);
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ALU64_ADD (GPR[RT]);
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ALU64_ADD (GPR[RT]);
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ALU64_END (GPR[RD]);
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ALU64_END (GPR[RD]); /* This checks for overflow. */
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}
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}
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TRACE_ALU_RESULT (GPR[RD]);
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TRACE_ALU_RESULT (GPR[RD]);
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}
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}
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@ -732,7 +731,7 @@
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{
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{
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ALU64_BEGIN (GPR[RS]);
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ALU64_BEGIN (GPR[RS]);
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ALU64_ADD (EXTEND16 (IMMEDIATE));
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ALU64_ADD (EXTEND16 (IMMEDIATE));
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ALU64_END (GPR[RT]);
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ALU64_END (GPR[RT]); /* This checks for overflow. */
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}
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}
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TRACE_ALU_RESULT (GPR[RT]);
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TRACE_ALU_RESULT (GPR[RT]);
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}
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}
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@ -1181,7 +1180,7 @@
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{
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{
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ALU64_BEGIN (GPR[RS]);
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ALU64_BEGIN (GPR[RS]);
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ALU64_SUB (GPR[RT]);
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ALU64_SUB (GPR[RT]);
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ALU64_END (GPR[RD]);
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ALU64_END (GPR[RD]); /* This checks for overflow. */
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}
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}
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TRACE_ALU_RESULT (GPR[RD]);
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TRACE_ALU_RESULT (GPR[RD]);
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}
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}
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@ -2210,7 +2209,7 @@
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{
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{
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ALU32_BEGIN (GPR[RS]);
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ALU32_BEGIN (GPR[RS]);
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ALU32_SUB (GPR[RT]);
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ALU32_SUB (GPR[RT]);
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ALU32_END (GPR[RD]);
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ALU32_END (GPR[RD]); /* This checks for overflow. */
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}
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}
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TRACE_ALU_RESULT (GPR[RD]);
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TRACE_ALU_RESULT (GPR[RD]);
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}
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}
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