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2002-02-11 Chris Demetriou <cgd@broadcom.com> 

* mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
        indicating that ALU32_END or ALU64_END are there to check
        for overflow.
        (DADD): Likewise, but also remove previous comment about
        overflow checking.
This commit is contained in:
Chris Demetriou 2002-02-11 22:49:45 +00:00
parent d434e57428
commit 9805e2294e
2 changed files with 14 additions and 7 deletions
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8
sim/mips/ChangeLog
View File

@ -1,3 +1,11 @@
2002-02-11 Chris Demetriou <cgd@broadcom.com>
* mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
indicating that ALU32_END or ALU64_END are there to check
for overflow.
(DADD): Likewise, but also remove previous comment about
overflow checking.
2002-02-10 Chris Demetriou <cgd@broadcom.com> 2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32, * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,

13
sim/mips/mips.igen
View File

@ -237,7 +237,7 @@
{ {
ALU32_BEGIN (GPR[RS]); ALU32_BEGIN (GPR[RS]);
ALU32_ADD (GPR[RT]); ALU32_ADD (GPR[RT]);
ALU32_END (GPR[RD]); ALU32_END (GPR[RD]); /* This checks for overflow. */
} }
TRACE_ALU_RESULT (GPR[RD]); TRACE_ALU_RESULT (GPR[RD]);
} }
@ -255,7 +255,7 @@
{ {
ALU32_BEGIN (GPR[RS]); ALU32_BEGIN (GPR[RS]);
ALU32_ADD (EXTEND16 (IMMEDIATE)); ALU32_ADD (EXTEND16 (IMMEDIATE));
ALU32_END (GPR[RT]); ALU32_END (GPR[RT]); /* This checks for overflow. */
} }
TRACE_ALU_RESULT (GPR[RT]); TRACE_ALU_RESULT (GPR[RT]);
} }
@ -709,12 +709,11 @@
*vr4100: *vr4100:
*vr5000: *vr5000:
{ {
/* this check's for overflow */
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
{ {
ALU64_BEGIN (GPR[RS]); ALU64_BEGIN (GPR[RS]);
ALU64_ADD (GPR[RT]); ALU64_ADD (GPR[RT]);
ALU64_END (GPR[RD]); ALU64_END (GPR[RD]); /* This checks for overflow. */
} }
TRACE_ALU_RESULT (GPR[RD]); TRACE_ALU_RESULT (GPR[RD]);
} }
@ -732,7 +731,7 @@
{ {
ALU64_BEGIN (GPR[RS]); ALU64_BEGIN (GPR[RS]);
ALU64_ADD (EXTEND16 (IMMEDIATE)); ALU64_ADD (EXTEND16 (IMMEDIATE));
ALU64_END (GPR[RT]); ALU64_END (GPR[RT]); /* This checks for overflow. */
} }
TRACE_ALU_RESULT (GPR[RT]); TRACE_ALU_RESULT (GPR[RT]);
} }
@ -1181,7 +1180,7 @@
{ {
ALU64_BEGIN (GPR[RS]); ALU64_BEGIN (GPR[RS]);
ALU64_SUB (GPR[RT]); ALU64_SUB (GPR[RT]);
ALU64_END (GPR[RD]); ALU64_END (GPR[RD]); /* This checks for overflow. */
} }
TRACE_ALU_RESULT (GPR[RD]); TRACE_ALU_RESULT (GPR[RD]);
} }
@ -2210,7 +2209,7 @@
{ {
ALU32_BEGIN (GPR[RS]); ALU32_BEGIN (GPR[RS]);
ALU32_SUB (GPR[RT]); ALU32_SUB (GPR[RT]);
ALU32_END (GPR[RD]); ALU32_END (GPR[RD]); /* This checks for overflow. */
} }
TRACE_ALU_RESULT (GPR[RD]); TRACE_ALU_RESULT (GPR[RD]);
} }