* config/tc-m68hc11.h (LISTING_HEADER): Use m68hc11_listing_header
function to select the header according to the cpu. (md_after_pass_hook, md_do_align): Remove. (md_cleanup, m68hc11_cleanup): Remove. (md_pcrel_from_section): Declare. * config/tc-m68hc11.c (build_dbranch_insn): Remove insn_size. (build_jump_insn, build_insn): Likewise. (m68hc11_listing_header): New function. (m68hc11_cleanup): Remove.
This commit is contained in:
Stephane Carrez
parent
4f69f9744a
commit
986c6f4ba0
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@ -1,3 +1,15 @@
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2001-02-04 Stephane Carrez <Stephane.Carrez@worldnet.fr>
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* config/tc-m68hc11.h (LISTING_HEADER): Use m68hc11_listing_header
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function to select the header according to the cpu.
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(md_after_pass_hook, md_do_align): Remove.
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(md_cleanup, m68hc11_cleanup): Remove.
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(md_pcrel_from_section): Declare.
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* config/tc-m68hc11.c (build_dbranch_insn): Remove insn_size.
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(build_jump_insn, build_insn): Likewise.
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(m68hc11_listing_header): New function.
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(m68hc11_cleanup): Remove.
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2001-02-02 Stephane Carrez <Stephane.Carrez@worldnet.fr>
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* config/tc-m68hc11.c (relaxable_symbol): Relax externally visible
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@ -226,6 +226,8 @@ const pseudo_typeS md_pseudo_table[] = {
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{"fdb", cons, 2},
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{"fcc", stringer, 1},
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{"rmb", s_space, 0},
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/* Dwarf2 support for Gcc. */
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{"file", dwarf2_directive_file, 0},
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{"loc", dwarf2_directive_loc, 0},
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@ -288,6 +290,16 @@ m68hc11_mach ()
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return 0;
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}
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/* Listing header selected according to cpu. */
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const char *
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m68hc11_listing_header ()
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{
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if (current_architecture & cpu6811)
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return "M68HC11 GAS ";
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else
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return "M68HC12 GAS ";
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}
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void
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md_show_usage (stream)
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FILE *stream;
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@ -371,7 +383,7 @@ md_parse_option (c, arg)
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get_default_target ();
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switch (c)
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{
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/* -S means keep external to 2 bits offset rather than 16 bits one. */
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/* -S means keep external to 2 bit offset rather than 16 bit one. */
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case OPTION_SHORT_BRANCHS:
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case 'S':
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flag_fixed_branchs = 1;
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@ -1198,7 +1210,7 @@ check_range (num, mode)
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if (mode & M6812_AUTO_INC_DEC)
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return (num != 0 && num <= 8 && num >= -8);
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/* The 68HC12 supports 5, 9 and 16-bits offsets. */
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/* The 68HC12 supports 5, 9 and 16-bit offsets. */
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if (mode & (M6812_INDEXED_IND | M6812_INDEXED | M6812_OP_IDX))
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mode = M6811_OP_IND16;
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@ -1307,7 +1319,7 @@ fixup8 (oper, mode, opmode)
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}
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}
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/* Put a 2 bytes expression described by 'oper'. If this expression contains
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/* Put a 2 byte expression described by 'oper'. If this expression contains
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unresolved symbols, generate a 16-bit fixup. */
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static void
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fixup16 (oper, mode, opmode)
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@ -1392,7 +1404,6 @@ build_jump_insn (opcode, operands, nb_operands, jmp_mode)
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int jmp_mode;
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{
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unsigned char code;
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int insn_size;
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char *f;
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unsigned long n;
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@ -1403,7 +1414,6 @@ build_jump_insn (opcode, operands, nb_operands, jmp_mode)
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assert (operands[0].reg1 == REG_NONE && operands[0].reg2 == REG_NONE);
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code = opcode->opcode;
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insn_size = 1;
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n = operands[0].exp.X_add_number;
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@ -1527,7 +1537,6 @@ build_dbranch_insn (opcode, operands, nb_operands, jmp_mode)
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int jmp_mode;
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{
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unsigned char code;
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int insn_size;
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char *f;
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unsigned long n;
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@ -1538,7 +1547,6 @@ build_dbranch_insn (opcode, operands, nb_operands, jmp_mode)
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assert (operands[0].reg1 != REG_NONE);
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code = opcode->opcode & 0x0FF;
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insn_size = 1;
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f = m68hc11_new_insn (1);
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number_to_chars_bigendian (f, code, 1);
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@ -1872,7 +1880,6 @@ build_insn (opcode, operands, nb_operands)
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{
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int i;
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char *f;
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int insn_size = 1;
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long format;
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int move_insn = 0;
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@ -1892,7 +1899,6 @@ build_insn (opcode, operands, nb_operands)
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number_to_chars_bigendian (f, page_code, 1);
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f++;
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insn_size = 2;
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}
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else
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f = m68hc11_new_insn (1);
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@ -1908,13 +1914,13 @@ build_insn (opcode, operands, nb_operands)
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move_insn = 1;
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if (format & M6812_OP_IDX)
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{
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insn_size += build_indexed_byte (&operands[0], format, 1);
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build_indexed_byte (&operands[0], format, 1);
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i = 1;
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format &= ~M6812_OP_IDX;
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}
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if (format & M6812_OP_IDX_P2)
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{
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insn_size += build_indexed_byte (&operands[1], format, 1);
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build_indexed_byte (&operands[1], format, 1);
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i = 0;
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format &= ~M6812_OP_IDX_P2;
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}
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@ -1922,7 +1928,6 @@ build_insn (opcode, operands, nb_operands)
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if (format & (M6811_OP_DIRECT | M6811_OP_IMM8))
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{
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insn_size++;
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fixup8 (&operands[i].exp,
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format & (M6811_OP_DIRECT | M6811_OP_IMM8 | M6812_OP_TRAP_ID),
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operands[i].mode);
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@ -1930,7 +1935,6 @@ build_insn (opcode, operands, nb_operands)
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}
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else if (format & (M6811_OP_IMM16 | M6811_OP_IND16))
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{
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insn_size += 2;
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fixup16 (&operands[i].exp, format & (M6811_OP_IMM16 | M6811_OP_IND16),
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operands[i].mode);
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i++;
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@ -1942,36 +1946,31 @@ build_insn (opcode, operands, nb_operands)
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if ((format & M6811_OP_IY) && (operands[0].reg1 != REG_Y))
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as_bad (_("Invalid indexed register, expecting register Y."));
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insn_size++;
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fixup8 (&operands[0].exp, M6811_OP_IX, operands[0].mode);
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i = 1;
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}
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else if (format &
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(M6812_OP_IDX | M6812_OP_IDX_2 | M6812_OP_IDX_1 | M6812_OP_D_IDX))
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{
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insn_size += build_indexed_byte (&operands[i], format, move_insn);
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build_indexed_byte (&operands[i], format, move_insn);
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i++;
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}
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else if (format & M6812_OP_REG && current_architecture & cpu6812)
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{
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insn_size += build_reg_mode (&operands[i], format);
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build_reg_mode (&operands[i], format);
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i++;
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}
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if (format & M6811_OP_BITMASK)
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{
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insn_size++;
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fixup8 (&operands[i].exp, M6811_OP_BITMASK, operands[i].mode);
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i++;
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}
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if (format & M6811_OP_JUMP_REL)
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{
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insn_size++;
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fixup8 (&operands[i].exp, M6811_OP_JUMP_REL, operands[i].mode);
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i++;
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}
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else if (format & M6812_OP_IND16_P2)
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{
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insn_size += 2;
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fixup16 (&operands[1].exp, M6811_OP_IND16, operands[1].mode);
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}
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}
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@ -2288,7 +2287,7 @@ md_assemble (str)
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}
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/* Identify a possible instruction alias. There are some on the
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68HC12 to emulate a fiew 68HC11 instructions. */
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68HC12 to emulate a few 68HC11 instructions. */
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if (opc == NULL && (current_architecture & cpu6812))
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{
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int i;
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@ -2809,9 +2808,3 @@ md_apply_fix (fixp, valuep)
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return 0;
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}
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int
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m68hc11_cleanup ()
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{
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return 1;
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}
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@ -1,5 +1,5 @@
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/* tc-m68hc11.h -- Header file for tc-m68hc11.c.
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Copyright (C) 1999, 2000 Free Software Foundation, Inc.
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Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
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This file is part of GAS, the GNU Assembler.
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@ -21,6 +21,10 @@
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#define TC_M68HC11
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#define TC_M68HC12
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#ifdef ANSI_PROTOTYPES
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struct fix;
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#endif
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/* Define TC_M68K so that we can use the MRI mode. */
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#define TC_M68K
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@ -63,21 +67,23 @@ extern const char *m68hc11_arch_format PARAMS ((void));
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#define LISTING_LHS_WIDTH 4 /* One word on the first line */
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#define LISTING_LHS_WIDTH_SECOND 4 /* One word on the second line */
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#define LISTING_LHS_CONT_LINES 4 /* And 4 lines max */
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#define LISTING_HEADER "M68HC11 GAS "
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#define LISTING_HEADER m68hc11_listing_header ()
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extern const char *m68hc11_listing_header PARAMS (());
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/* call md_pcrel_from_section, not md_pcrel_from */
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#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section(FIXP, SEC)
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extern long md_pcrel_from_section PARAMS ((struct fix *fixp, segT sec));
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/* Permit temporary numeric labels. */
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#define LOCAL_LABELS_FB 1
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#define DIFF_EXPR_OK /* .-foo gets turned into PC relative relocs */
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extern void m68hc11_init_after_args PARAMS ((void));
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#define tc_init_after_args m68hc11_init_after_args
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extern void m68hc11_init_after_args PARAMS ((void));
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extern int m68hc11_parse_long_option PARAMS ((char *));
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#define md_parse_long_option m68hc11_parse_long_option
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extern int m68hc11_parse_long_option PARAMS ((char *));
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#define DWARF2_LINE_MIN_INSN_LENGTH 1
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@ -88,19 +94,13 @@ extern int m68hc11_parse_long_option PARAMS ((char *));
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/* Relax table to translate short relative branches (-128..127) into
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absolute branches. */
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extern struct relax_type md_relax_table[];
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#define TC_GENERIC_RELAX_TABLE md_relax_table
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extern int m68hc11_cleanup PARAMS ((void));
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extern struct relax_type md_relax_table[];
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#define md_operand(x)
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#define md_after_pass_hook() m68hc11_cleanup()
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#define md_cleanup() m68hc11_cleanup()
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#define md_do_align(a,b,c,d,e) m68hc11_cleanup()
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#define tc_frob_label(sym) do {\
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m68hc11_cleanup(); \
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S_SET_VALUE (sym, (valueT) frag_now_fix ()); \
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} while (0)
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#define tc_print_statistics m68hc11_print_statistics
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#define tc_print_statistics(FILE) m68hc11_print_statistics (FILE)
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extern void m68hc11_print_statistics PARAMS ((FILE *));
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