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* simops.c (OP_1C007E0): Compensate for 64 bit hosts.

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(OP_18007E0): Likewise.
(OP_2C007E0): Likewise.
(OP_28007E0): Likewise.
* v850.igen (divh): Likewise.
This commit is contained in:
DJ Delorie 2008-02-06 04:41:26 +00:00
parent 1a4ca44aeb
commit 98e460c30d
3 changed files with 17 additions and 9 deletions
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6
sim/v850/ChangeLog
View File

@ -1,5 +1,11 @@
2008-02-05 DJ Delorie <dj@redhat.com>
* simops.c (OP_1C007E0): Compensate for 64 bit hosts.
(OP_18007E0): Likewise.
(OP_2C007E0): Likewise.
(OP_28007E0): Likewise.
* v850.igen (divh): Likewise.
* simops.c (OP_C0): Correct saturation logic.
(OP_220): Likewise.
(OP_A0): Likewise.

16
sim/v850/simops.c
View File

@ -2209,8 +2209,8 @@ OP_1C007E0 (void)
imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
divide_by = State.regs[ OP[0] ];
divide_this = State.regs[ OP[1] ] << imm5;
divide_by = (signed32) State.regs[ OP[0] ];
divide_this = (signed32) (State.regs[ OP[1] ] << imm5);
divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
@ -2280,7 +2280,7 @@ OP_18007E0 (void)
imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
divide_by = EXTEND16 (State.regs[ OP[0] ]);
divide_this = State.regs[ OP[1] ] << imm5;
divide_this = (signed32) (State.regs[ OP[1] ] << imm5);
divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
@ -2351,14 +2351,14 @@ OP_2C007E0 (void)
/* Compute the result. */
divide_by = State.regs[ OP[0] ];
divide_by = (signed32) State.regs[ OP[0] ];
divide_this = State.regs[ OP[1] ];
if (divide_by == 0)
{
PSW |= PSW_OV;
}
else if (divide_by == -1 && divide_this == (1 << 31))
else if (divide_by == -1 && divide_this == (1L << 31))
{
PSW &= ~PSW_Z;
PSW |= PSW_OV | PSW_S;
@ -2367,9 +2367,10 @@ OP_2C007E0 (void)
}
else
{
divide_this = (signed32) divide_this;
State.regs[ OP[1] ] = quotient = divide_this / divide_by;
State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
/* Set condition codes. */
PSW &= ~(PSW_Z | PSW_S | PSW_OV);
@ -2442,7 +2443,7 @@ OP_28007E0 (void)
{
PSW |= PSW_OV;
}
else if (divide_by == -1 && divide_this == (1 << 31))
else if (divide_by == -1 && divide_this == (1L << 31))
{
PSW &= ~PSW_Z;
PSW |= PSW_OV | PSW_S;
@ -2451,6 +2452,7 @@ OP_28007E0 (void)
}
else
{
divide_this = (signed32) divide_this;
State.regs[ OP[1] ] = quotient = divide_this / divide_by;
State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;

4
sim/v850/v850.igen
View File

@ -356,7 +356,7 @@ rrrrr!0,000010,RRRRR!0:I:::divh
op0 = EXTEND16 (State.regs[OP[0]]);
op1 = State.regs[OP[1]];
if (op0 == 0xffffffff && op1 == 0x80000000)
if (op0 == -1 && op1 == 0x80000000)
{
PSW &= ~PSW_Z;
PSW |= PSW_OV | PSW_S;
@ -368,7 +368,7 @@ rrrrr!0,000010,RRRRR!0:I:::divh
}
else
{
result = op1 / op0;
result = (signed32) op1 / op0;
ov = 0;
/* Compute the condition codes. */