opcodes/
* ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf. (extract_fxm): Don't test dialect. (XFXFXM_MASK): Include the power4 bit. (XFXM): Add p4 param. (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr. gas/testsuite/ * gas/ppc/power4.d: Update.
This commit is contained in:
Alan Modra
parent
3722b82f10
commit
98e6987548
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@ -1,3 +1,7 @@
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2004-06-28 Alan Modra <amodra@bigpond.net.au>
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* gas/ppc/power4.d: Update.
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2004-06-24 Alan Modra <amodra@bigpond.net.au>
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* gas/i386/prescott.s: Remove fisttpd and fisttpq.
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@ -82,23 +82,23 @@ Disassembly of section \.text:
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+68: 7c 6f f1 20 mtcr r3
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+6c: 7c 6f f1 20 mtcr r3
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+70: 7c 68 11 20 mtcrf 129,r3
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+74: 7c 70 11 20 mtcrf 1,r3
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+78: 7c 70 21 20 mtcrf 2,r3
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+7c: 7c 70 41 20 mtcrf 4,r3
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+80: 7c 70 81 20 mtcrf 8,r3
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+84: 7c 71 01 20 mtcrf 16,r3
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+88: 7c 72 01 20 mtcrf 32,r3
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+8c: 7c 74 01 20 mtcrf 64,r3
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+90: 7c 78 01 20 mtcrf 128,r3
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+74: 7c 70 11 20 mtocrf 1,r3
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+78: 7c 70 21 20 mtocrf 2,r3
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+7c: 7c 70 41 20 mtocrf 4,r3
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+80: 7c 70 81 20 mtocrf 8,r3
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+84: 7c 71 01 20 mtocrf 16,r3
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+88: 7c 72 01 20 mtocrf 32,r3
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+8c: 7c 74 01 20 mtocrf 64,r3
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+90: 7c 78 01 20 mtocrf 128,r3
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+94: 7c 60 00 26 mfcr r3
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+98: 7c 70 10 26 mfcr r3,1
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+9c: 7c 70 20 26 mfcr r3,2
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+a0: 7c 70 40 26 mfcr r3,4
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+a4: 7c 70 80 26 mfcr r3,8
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+a8: 7c 71 00 26 mfcr r3,16
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+ac: 7c 72 00 26 mfcr r3,32
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+b0: 7c 74 00 26 mfcr r3,64
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+b4: 7c 78 00 26 mfcr r3,128
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+98: 7c 70 10 26 mfocrf r3,1
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+9c: 7c 70 20 26 mfocrf r3,2
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+a0: 7c 70 40 26 mfocrf r3,4
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+a4: 7c 70 80 26 mfocrf r3,8
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+a8: 7c 71 00 26 mfocrf r3,16
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+ac: 7c 72 00 26 mfocrf r3,32
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+b0: 7c 74 00 26 mfocrf r3,64
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+b4: 7c 78 00 26 mfocrf r3,128
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+b8: 7c 01 17 ec dcbz r1,r2
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+bc: 7c 23 27 ec dcbzl r3,r4
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+c0: 7c 05 37 ec dcbz r5,r6
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@ -1,3 +1,11 @@
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2004-06-28 Alan Modra <amodra@bigpond.net.au>
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* ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
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(extract_fxm): Don't test dialect.
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(XFXFXM_MASK): Include the power4 bit.
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(XFXM): Add p4 param.
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(powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
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2004-06-27 Alexandre Oliva <aoliva@redhat.com>
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2003-07-21 Richard Sandiford <rsandifo@redhat.com>
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@ -998,11 +998,22 @@ insert_fxm (unsigned long insn,
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int dialect,
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const char **errmsg)
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{
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/* If we're handling the mfocrf and mtocrf insns ensure that exactly
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one bit of the mask field is set. */
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if ((insn & (1 << 20)) != 0)
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{
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if (value == 0 || (value & -value) != value)
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{
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*errmsg = _("invalid mask field");
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value = 0;
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}
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}
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/* If the optional field on mfcr is missing that means we want to use
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the old form of the instruction that moves the whole cr. In that
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case we'll have VALUE zero. There doesn't seem to be a way to
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distinguish this from the case where someone writes mfcr %r3,0. */
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if (value == 0)
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else if (value == 0)
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;
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/* If only one bit of the FXM field is set, we can use the new form
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@ -1028,7 +1039,7 @@ insert_fxm (unsigned long insn,
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static long
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extract_fxm (unsigned long insn,
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int dialect,
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int dialect ATTRIBUTE_UNUSED,
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int *invalid)
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{
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long mask = (insn >> 12) & 0xff;
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@ -1036,14 +1047,9 @@ extract_fxm (unsigned long insn,
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/* Is this a Power4 insn? */
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if ((insn & (1 << 20)) != 0)
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{
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if ((dialect & PPC_OPCODE_POWER4) == 0)
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/* Exactly one bit of MASK should be set. */
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if (mask == 0 || (mask & -mask) != mask)
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*invalid = 1;
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else
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{
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/* Exactly one bit of MASK should be set. */
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if (mask == 0 || (mask & -mask) != mask)
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*invalid = 1;
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}
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}
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/* Check that non-power4 form of mfcr has a zero MASK. */
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@ -1681,11 +1687,12 @@ extract_tbr (unsigned long insn,
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#define XS_MASK XS (0x3f, 0x1ff, 1)
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/* A mask for the FXM version of an XFX form instruction. */
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#define XFXFXM_MASK (X_MASK | (1 << 11))
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#define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
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/* An XFX form instruction with the FXM field filled in. */
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#define XFXM(op, xop, fxm) \
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(X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
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#define XFXM(op, xop, fxm, p4) \
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(X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
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| ((unsigned long)(p4) << 20))
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/* An XFX form instruction with the SPR field filled in. */
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#define XSPR(op, xop, spr) \
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@ -3227,6 +3234,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
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{ "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
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{ "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } },
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{ "mfcr", X(31,19), XRARB_MASK, NOPOWER4, { RT } },
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{ "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
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@ -3382,7 +3390,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
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{ "mtcr", XFXM(31,144,0xff), XRARB_MASK, COM, { RS }},
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{ "mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, { FXM, RS } },
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{ "mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, { RS }},
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{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
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{ "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
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