x86: Encode 256-bit/512-bit VEX/EVEX insns with 128-bit VEX
Since all AVX512 processors support AVX, we can encode 256-bit/512-bit VEX/EVEX vector register clearing instructions with 128-bit VEX vector register clearing instructions at -O1. * config/tc-i386.c (optimize_encoding): Encode 256-bit/512-bit VEX/EVEX vector register clearing instructions with 128-bit VEX vector register clearing instructions at -O1. * doc/c-i386.texi: Update -O1 and -O2 documentation. * testsuite/gas/i386/i386.exp: Run optimize-1a and x86-64-optimize-2a. * testsuite/gas/i386/optimize-1a.d: New file. * testsuite/gas/i386/x86-64-optimize-2a.d: Likewise.
This commit is contained in:
H.J. Lu
parent
d4cbef22ba
commit
99112332cd
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@ -1,3 +1,14 @@
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2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (optimize_encoding): Encode 256-bit/512-bit
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VEX/EVEX vector register clearing instructions with 128-bit VEX
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vector register clearing instructions at -O1.
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* doc/c-i386.texi: Update -O1 and -O2 documentation.
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* testsuite/gas/i386/i386.exp: Run optimize-1a and
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x86-64-optimize-2a.
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* testsuite/gas/i386/optimize-1a.d: New file.
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* testsuite/gas/i386/x86-64-optimize-2a.d: Likewise.
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2019-03-17 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/24353
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@ -3977,8 +3977,7 @@ optimize_encoding (void)
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}
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}
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}
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else if (optimize > 1
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&& i.reg_operands == 3
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else if (i.reg_operands == 3
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&& i.op[0].regs == i.op[1].regs
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&& !i.types[2].bitfield.xmmword
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&& (i.tm.opcode_modifier.vex
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@ -4009,15 +4008,15 @@ optimize_encoding (void)
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|| i.tm.base_opcode == 0x6647)
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&& i.tm.extension_opcode == None))
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{
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/* Optimize: -O2:
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/* Optimize: -O1:
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VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
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vpsubq and vpsubw:
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EVEX VOP %zmmM, %zmmM, %zmmN
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-> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
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-> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
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-> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
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EVEX VOP %ymmM, %ymmM, %ymmN
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-> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
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-> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
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-> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
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VEX VOP %ymmM, %ymmM, %ymmN
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-> VEX VOP %xmmM, %xmmM, %xmmN
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VOP, one of vpandn and vpxor:
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@ -4026,17 +4025,17 @@ optimize_encoding (void)
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VOP, one of vpandnd and vpandnq:
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EVEX VOP %zmmM, %zmmM, %zmmN
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-> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
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-> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
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-> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
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EVEX VOP %ymmM, %ymmM, %ymmN
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-> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
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-> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
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-> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
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VOP, one of vpxord and vpxorq:
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EVEX VOP %zmmM, %zmmM, %zmmN
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-> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
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-> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
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-> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
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EVEX VOP %ymmM, %ymmM, %ymmN
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-> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
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-> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
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-> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
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VOP, one of kxord and kxorq:
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VEX VOP %kM, %kM, %kN
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-> VEX kxorw %kM, %kM, %kN
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@ -4054,8 +4053,9 @@ optimize_encoding (void)
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i.tm.opcode_modifier.vexw = VEXW0;
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i.tm.opcode_modifier.evex = 0;
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}
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else if (cpu_arch_flags.bitfield.cpuavx512vl
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|| cpu_arch_isa_flags.bitfield.cpuavx512vl)
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else if (optimize > 1
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&& (cpu_arch_flags.bitfield.cpuavx512vl
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|| cpu_arch_isa_flags.bitfield.cpuavx512vl))
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i.tm.opcode_modifier.evex = EVEX128;
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else
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return;
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@ -453,10 +453,12 @@ Intel64 ISA in 64-bit mode. The default is to accept both.
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Optimize instruction encoding with smaller instruction size. @samp{-O}
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and @samp{-O1} encode 64-bit register load instructions with 64-bit
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immediate as 32-bit register load instructions with 31-bit or 32-bits
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immediates and encode 64-bit register clearing instructions with 32-bit
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register clearing instructions. @samp{-O2} includes @samp{-O1}
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optimization plus encodes 256-bit and 512-bit vector register clearing
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instructions with 128-bit vector register clearing instructions.
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immediates, encode 64-bit register clearing instructions with 32-bit
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register clearing instructions and encode 256-bit/512-bit VEX/EVEX
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vector register clearing instructions with 128-bit VEX vector register
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clearing instructions. @samp{-O2} includes @samp{-O1} optimization plus
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encodes 256-bit/512-bit EVEX vector register clearing instructions with
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128-bit EVEX vector register clearing instructions.
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@samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit
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and 64-bit register tests with immediate as 8-bit register test with
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immediate. @samp{-O0} turns off this optimization.
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@ -468,6 +468,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_dump_test "nop-1"
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run_dump_test "nop-2"
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run_dump_test "optimize-1"
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run_dump_test "optimize-1a"
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run_dump_test "optimize-2"
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run_dump_test "optimize-3"
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run_dump_test "optimize-4"
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@ -981,6 +982,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
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run_dump_test "x86-64-nop-2"
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run_dump_test "x86-64-optimize-1"
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run_dump_test "x86-64-optimize-2"
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run_dump_test "x86-64-optimize-2a"
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run_dump_test "x86-64-optimize-3"
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run_dump_test "x86-64-optimize-4"
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run_dump_test "x86-64-optimize-5"
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@ -0,0 +1,66 @@
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#source: optimize-1.s
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#as: -O
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#objdump: -drw
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#name: optimized encoding 1a with -O
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.*: +file format .*
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Disassembly of section .text:
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0+ <_start>:
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+[a-f0-9]+: 62 f1 f5 4f 55 e9 vandnpd %zmm1,%zmm1,%zmm5\{%k7\}
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+[a-f0-9]+: c5 f1 55 e9 vandnpd %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f1 55 e9 vandnpd %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f1 55 e9 vandnpd %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: 62 f1 74 4f 55 e9 vandnps %zmm1,%zmm1,%zmm5\{%k7\}
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+[a-f0-9]+: c5 f0 55 e9 vandnps %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f0 55 e9 vandnps %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f0 55 e9 vandnps %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f1 df e9 vpandn %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: 62 f1 75 4f df e9 vpandnd %zmm1,%zmm1,%zmm5\{%k7\}
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+[a-f0-9]+: c5 f1 df e9 vpandn %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f1 df e9 vpandn %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f1 df e9 vpandn %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: 62 f1 f5 4f df e9 vpandnq %zmm1,%zmm1,%zmm5\{%k7\}
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+[a-f0-9]+: c5 f1 df e9 vpandn %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f1 df e9 vpandn %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f1 df e9 vpandn %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: 62 f1 f5 4f 57 e9 vxorpd %zmm1,%zmm1,%zmm5\{%k7\}
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+[a-f0-9]+: c5 f1 57 e9 vxorpd %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f1 57 e9 vxorpd %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f1 57 e9 vxorpd %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: 62 f1 74 4f 57 e9 vxorps %zmm1,%zmm1,%zmm5\{%k7\}
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+[a-f0-9]+: c5 f0 57 e9 vxorps %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f0 57 e9 vxorps %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f0 57 e9 vxorps %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f1 ef e9 vpxor %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: 62 f1 75 4f ef e9 vpxord %zmm1,%zmm1,%zmm5\{%k7\}
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+[a-f0-9]+: c5 f1 ef e9 vpxor %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f1 ef e9 vpxor %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f1 ef e9 vpxor %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: 62 f1 f5 4f ef e9 vpxorq %zmm1,%zmm1,%zmm5\{%k7\}
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+[a-f0-9]+: c5 f1 ef e9 vpxor %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f1 ef e9 vpxor %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f1 ef e9 vpxor %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: 62 f1 75 4f f8 e9 vpsubb %zmm1,%zmm1,%zmm5\{%k7\}
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+[a-f0-9]+: c5 f1 f8 e9 vpsubb %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f1 f8 e9 vpsubb %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f1 f8 e9 vpsubb %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: 62 f1 75 4f f9 e9 vpsubw %zmm1,%zmm1,%zmm5\{%k7\}
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+[a-f0-9]+: c5 f1 f9 e9 vpsubw %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f1 f9 e9 vpsubw %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f1 f9 e9 vpsubw %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: 62 f1 75 4f fa e9 vpsubd %zmm1,%zmm1,%zmm5\{%k7\}
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+[a-f0-9]+: c5 f1 fa e9 vpsubd %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f1 fa e9 vpsubd %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f1 fa e9 vpsubd %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: 62 f1 f5 4f fb e9 vpsubq %zmm1,%zmm1,%zmm5\{%k7\}
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+[a-f0-9]+: c5 f1 fb e9 vpsubq %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f1 fb e9 vpsubq %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f1 fb e9 vpsubq %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f4 47 e9 kxorw %k1,%k1,%k5
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+[a-f0-9]+: c5 f4 47 e9 kxorw %k1,%k1,%k5
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+[a-f0-9]+: c5 f4 42 e9 kandnw %k1,%k1,%k5
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+[a-f0-9]+: c5 f4 42 e9 kandnw %k1,%k1,%k5
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#pass
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@ -0,0 +1,110 @@
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#source: x86-64-optimize-2.s
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#as: -O
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#objdump: -drw
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#name: x86-64 optimized encoding 2a with -O
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.*: +file format .*
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Disassembly of section .text:
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0+ <_start>:
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+[a-f0-9]+: 62 71 f5 4f 55 f9 vandnpd %zmm1,%zmm1,%zmm15\{%k7\}
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+[a-f0-9]+: c5 71 55 f9 vandnpd %xmm1,%xmm1,%xmm15
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+[a-f0-9]+: c5 71 55 f9 vandnpd %xmm1,%xmm1,%xmm15
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+[a-f0-9]+: c5 71 55 f9 vandnpd %xmm1,%xmm1,%xmm15
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+[a-f0-9]+: 62 e1 f5 48 55 c1 vandnpd %zmm1,%zmm1,%zmm16
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+[a-f0-9]+: 62 e1 f5 28 55 c1 vandnpd %ymm1,%ymm1,%ymm16
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+[a-f0-9]+: 62 b1 f5 40 55 c9 vandnpd %zmm17,%zmm17,%zmm1
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+[a-f0-9]+: 62 b1 f5 20 55 c9 vandnpd %ymm17,%ymm17,%ymm1
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+[a-f0-9]+: 62 71 74 4f 55 f9 vandnps %zmm1,%zmm1,%zmm15\{%k7\}
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+[a-f0-9]+: c5 70 55 f9 vandnps %xmm1,%xmm1,%xmm15
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+[a-f0-9]+: c5 70 55 f9 vandnps %xmm1,%xmm1,%xmm15
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+[a-f0-9]+: c5 70 55 f9 vandnps %xmm1,%xmm1,%xmm15
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+[a-f0-9]+: 62 e1 74 48 55 c1 vandnps %zmm1,%zmm1,%zmm16
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+[a-f0-9]+: 62 e1 74 28 55 c1 vandnps %ymm1,%ymm1,%ymm16
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+[a-f0-9]+: 62 b1 74 40 55 c9 vandnps %zmm17,%zmm17,%zmm1
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+[a-f0-9]+: 62 b1 74 20 55 c9 vandnps %ymm17,%ymm17,%ymm1
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+[a-f0-9]+: c5 71 df f9 vpandn %xmm1,%xmm1,%xmm15
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+[a-f0-9]+: 62 71 75 4f df f9 vpandnd %zmm1,%zmm1,%zmm15\{%k7\}
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+[a-f0-9]+: c5 71 df f9 vpandn %xmm1,%xmm1,%xmm15
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+[a-f0-9]+: c5 71 df f9 vpandn %xmm1,%xmm1,%xmm15
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+[a-f0-9]+: c5 71 df f9 vpandn %xmm1,%xmm1,%xmm15
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||||
+[a-f0-9]+: 62 e1 75 48 df c1 vpandnd %zmm1,%zmm1,%zmm16
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||||
+[a-f0-9]+: 62 e1 75 28 df c1 vpandnd %ymm1,%ymm1,%ymm16
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||||
+[a-f0-9]+: 62 b1 75 40 df c9 vpandnd %zmm17,%zmm17,%zmm1
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+[a-f0-9]+: 62 b1 75 20 df c9 vpandnd %ymm17,%ymm17,%ymm1
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+[a-f0-9]+: 62 71 f5 4f df f9 vpandnq %zmm1,%zmm1,%zmm15\{%k7\}
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+[a-f0-9]+: c5 71 df f9 vpandn %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: c5 71 df f9 vpandn %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: c5 71 df f9 vpandn %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: 62 e1 f5 48 df c1 vpandnq %zmm1,%zmm1,%zmm16
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||||
+[a-f0-9]+: 62 e1 f5 28 df c1 vpandnq %ymm1,%ymm1,%ymm16
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||||
+[a-f0-9]+: 62 b1 f5 40 df c9 vpandnq %zmm17,%zmm17,%zmm1
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||||
+[a-f0-9]+: 62 b1 f5 20 df c9 vpandnq %ymm17,%ymm17,%ymm1
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||||
+[a-f0-9]+: 62 71 f5 4f 57 f9 vxorpd %zmm1,%zmm1,%zmm15\{%k7\}
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||||
+[a-f0-9]+: c5 71 57 f9 vxorpd %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: c5 71 57 f9 vxorpd %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: c5 71 57 f9 vxorpd %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: 62 e1 f5 48 57 c1 vxorpd %zmm1,%zmm1,%zmm16
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||||
+[a-f0-9]+: 62 e1 f5 28 57 c1 vxorpd %ymm1,%ymm1,%ymm16
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||||
+[a-f0-9]+: 62 b1 f5 40 57 c9 vxorpd %zmm17,%zmm17,%zmm1
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||||
+[a-f0-9]+: 62 b1 f5 20 57 c9 vxorpd %ymm17,%ymm17,%ymm1
|
||||
+[a-f0-9]+: 62 71 74 4f 57 f9 vxorps %zmm1,%zmm1,%zmm15\{%k7\}
|
||||
+[a-f0-9]+: c5 70 57 f9 vxorps %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: c5 70 57 f9 vxorps %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: c5 70 57 f9 vxorps %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: 62 e1 74 48 57 c1 vxorps %zmm1,%zmm1,%zmm16
|
||||
+[a-f0-9]+: 62 e1 74 28 57 c1 vxorps %ymm1,%ymm1,%ymm16
|
||||
+[a-f0-9]+: 62 b1 74 40 57 c9 vxorps %zmm17,%zmm17,%zmm1
|
||||
+[a-f0-9]+: 62 b1 74 20 57 c9 vxorps %ymm17,%ymm17,%ymm1
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||||
+[a-f0-9]+: c5 71 ef f9 vpxor %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: 62 71 75 4f ef f9 vpxord %zmm1,%zmm1,%zmm15\{%k7\}
|
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+[a-f0-9]+: c5 71 ef f9 vpxor %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: c5 71 ef f9 vpxor %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: c5 71 ef f9 vpxor %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: 62 e1 75 48 ef c1 vpxord %zmm1,%zmm1,%zmm16
|
||||
+[a-f0-9]+: 62 e1 75 28 ef c1 vpxord %ymm1,%ymm1,%ymm16
|
||||
+[a-f0-9]+: 62 b1 75 40 ef c9 vpxord %zmm17,%zmm17,%zmm1
|
||||
+[a-f0-9]+: 62 b1 75 20 ef c9 vpxord %ymm17,%ymm17,%ymm1
|
||||
+[a-f0-9]+: 62 71 f5 4f ef f9 vpxorq %zmm1,%zmm1,%zmm15\{%k7\}
|
||||
+[a-f0-9]+: c5 71 ef f9 vpxor %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: c5 71 ef f9 vpxor %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: c5 71 ef f9 vpxor %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: 62 e1 f5 48 ef c1 vpxorq %zmm1,%zmm1,%zmm16
|
||||
+[a-f0-9]+: 62 e1 f5 28 ef c1 vpxorq %ymm1,%ymm1,%ymm16
|
||||
+[a-f0-9]+: 62 b1 f5 40 ef c9 vpxorq %zmm17,%zmm17,%zmm1
|
||||
+[a-f0-9]+: 62 b1 f5 20 ef c9 vpxorq %ymm17,%ymm17,%ymm1
|
||||
+[a-f0-9]+: 62 71 75 4f f8 f9 vpsubb %zmm1,%zmm1,%zmm15\{%k7\}
|
||||
+[a-f0-9]+: c5 71 f8 f9 vpsubb %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: c5 71 f8 f9 vpsubb %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: c5 71 f8 f9 vpsubb %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: 62 e1 75 48 f8 c1 vpsubb %zmm1,%zmm1,%zmm16
|
||||
+[a-f0-9]+: 62 e1 75 28 f8 c1 vpsubb %ymm1,%ymm1,%ymm16
|
||||
+[a-f0-9]+: 62 b1 75 40 f8 c9 vpsubb %zmm17,%zmm17,%zmm1
|
||||
+[a-f0-9]+: 62 b1 75 20 f8 c9 vpsubb %ymm17,%ymm17,%ymm1
|
||||
+[a-f0-9]+: 62 71 75 4f f9 f9 vpsubw %zmm1,%zmm1,%zmm15\{%k7\}
|
||||
+[a-f0-9]+: c5 71 f9 f9 vpsubw %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: c5 71 f9 f9 vpsubw %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: c5 71 f9 f9 vpsubw %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: 62 e1 75 48 f9 c1 vpsubw %zmm1,%zmm1,%zmm16
|
||||
+[a-f0-9]+: 62 e1 75 28 f9 c1 vpsubw %ymm1,%ymm1,%ymm16
|
||||
+[a-f0-9]+: 62 b1 75 40 f9 c9 vpsubw %zmm17,%zmm17,%zmm1
|
||||
+[a-f0-9]+: 62 b1 75 20 f9 c9 vpsubw %ymm17,%ymm17,%ymm1
|
||||
+[a-f0-9]+: 62 71 75 4f fa f9 vpsubd %zmm1,%zmm1,%zmm15\{%k7\}
|
||||
+[a-f0-9]+: c5 71 fa f9 vpsubd %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: c5 71 fa f9 vpsubd %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: c5 71 fa f9 vpsubd %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: 62 e1 75 48 fa c1 vpsubd %zmm1,%zmm1,%zmm16
|
||||
+[a-f0-9]+: 62 e1 75 28 fa c1 vpsubd %ymm1,%ymm1,%ymm16
|
||||
+[a-f0-9]+: 62 b1 75 40 fa c9 vpsubd %zmm17,%zmm17,%zmm1
|
||||
+[a-f0-9]+: 62 b1 75 20 fa c9 vpsubd %ymm17,%ymm17,%ymm1
|
||||
+[a-f0-9]+: 62 71 f5 4f fb f9 vpsubq %zmm1,%zmm1,%zmm15\{%k7\}
|
||||
+[a-f0-9]+: c5 71 fb f9 vpsubq %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: c5 71 fb f9 vpsubq %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: c5 71 fb f9 vpsubq %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: 62 e1 f5 48 fb c1 vpsubq %zmm1,%zmm1,%zmm16
|
||||
+[a-f0-9]+: 62 e1 f5 28 fb c1 vpsubq %ymm1,%ymm1,%ymm16
|
||||
+[a-f0-9]+: 62 b1 f5 40 fb c9 vpsubq %zmm17,%zmm17,%zmm1
|
||||
+[a-f0-9]+: 62 b1 f5 20 fb c9 vpsubq %ymm17,%ymm17,%ymm1
|
||||
#pass
|
||||
Loading…
Reference in New Issue