Add support for MIPS R1[02]000 performance counter opcodes.
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Thiemo Seufer
parent
2cd8959083
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99c14723f3
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@ -1,3 +1,9 @@
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2001-08-16 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
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* gas/mips/mips.exp: Added performance counter test.
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* gas/mips/perfcount.s: New File. Test of performance counter opcodes.
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* gas/mips/perfcount.d: Likewise.
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2001-08-12 Nick Clifton <nickc@cambridge.redhat.com>
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* gas/sparc/unalign.s: Extend test to check .uaword with multiple
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@ -111,6 +111,7 @@ if { [istarget mips*-*-*] } then {
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run_dump_test "mips4010"
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run_dump_test "mips4650"
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run_dump_test "mips4100"
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run_dump_test "perfcount"
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# Linux uses ELF stabs, which doesn't support line number.
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setup_xfail "mips*-*-*linux*"
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run_dump_test "lineno"
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@ -0,0 +1,11 @@
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#objdump: -dr --prefix-addresses -mmips:10000
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#name: MIPS R1[20]000 performance counters
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#as: -mips4 -march=r10000
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.*: +file format .*mips.*
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Disassembly of section .text:
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0+0000 <[^>]*> mtps a0,0
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0+0004 <[^>]*> mfps a0,1
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0+0008 <[^>]*> mtpc a0,1
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0+000c <[^>]*> mfpc a0,0
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@ -0,0 +1,7 @@
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# source file to test assembly of R1[20]000 performance counter instructions.
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foo:
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mtps $4, 0
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mfps $4, 1
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mtpc $4, 1
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mfpc $4, 0
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@ -1,3 +1,8 @@
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2001-08-16 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
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* mips.h (INSN_10000): Define.
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(OPCODE_IS_MEMBER): Check for INSN_10000.
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2001-08-10 Alan Modra <amodra@one.net.au>
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* ppc.h: Revert 2001-08-08.
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@ -326,6 +326,8 @@ struct mips_opcode
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#define INSN_4100 0x00040000
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/* Toshiba R3900 instruction. */
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#define INSN_3900 0x00080000
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/* MIPS R10000 instruction. */
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#define INSN_10000 0x00100000
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/* MIPS ISA defines, use instead of hardcoding ISA level. */
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@ -375,7 +377,9 @@ struct mips_opcode
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|| (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
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|| ((cpu == CPU_VR4100 || cpu == CPU_R4111) \
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&& ((insn)->membership & INSN_4100) != 0) \
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|| (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0))
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|| (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
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|| ((cpu == CPU_R10000 || cpu == CPU_R12000) \
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&& ((insn)->membership & INSN_10000) != 0))
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/* This is a list of macro expanded instructions.
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@ -1,3 +1,9 @@
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2001-08-16 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
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* mips-opc.c (M1): Define. Reformatted Code.
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(mips_builtin_opcodes): Added performance counter opcodes mfpc, mfps,
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mtps, mtps. Typo.
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2001-08-16 Jonathan Larmour <jlarmour@redhat.com>
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* mips-opc.c: R3900s can support all branch likely INSN_MACROs where
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@ -86,15 +86,16 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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#define L1 INSN_4010
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#define V1 INSN_4100
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#define T3 INSN_3900
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#define M1 INSN_10000
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#define G1 (T3 \
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)
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#define G2 (T3 \
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#define G2 (T3 \
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)
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#define G3 (I4 \
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)
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#define G3 (I4 \
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)
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/* The order of overloaded instructions matters. Label arguments and
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register arguments look the same. Instructions that can have either
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@ -557,6 +558,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, G1 },
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{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 },
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{"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, V1 },
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{"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, M1 },
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{"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, M1 },
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{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, I1 },
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{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, I32 },
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{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 },
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@ -594,6 +597,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, I32 },
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{"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, L1 },
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{"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, I32 },
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{"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, M1 },
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{"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, M1 },
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{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I1 },
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{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I32 },
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{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
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@ -836,7 +841,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
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/* No hazard protection on coprocessor instructions--they shouldn't
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change the state of the processor and if they do it's up to the
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user to put in nops as necessary. These are at the end so that the
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disasembler recognizes more specific versions first. */
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disassembler recognizes more specific versions first. */
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{"c0", "C", 0x42000000, 0xfe000000, 0, I1 },
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{"c1", "C", 0x46000000, 0xfe000000, 0, I1 },
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{"c2", "C", 0x4a000000, 0xfe000000, 0, I1 },
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