Add RegRex64 to riz
* i386-reg.tbl (riz): Add RegRex64. * i386-tbl.h: Regenerated.
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@ -1,3 +1,8 @@
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2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
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* i386-reg.tbl (riz): Add RegRex64.
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* i386-tbl.h: Regenerated.
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2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
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* aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
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@ -211,8 +211,8 @@ rip, BaseIndex, RegRex64, RegRip, Dw2Inval, 16
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eip, BaseIndex, RegRex64, RegEip, 8, Dw2Inval
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// No type will make these registers rejected for all purposes except
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// for addressing.
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riz, BaseIndex, RegRex64, RegRiz, Dw2Inval, Dw2Inval
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eiz, BaseIndex, 0, RegEiz, Dw2Inval, Dw2Inval
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riz, BaseIndex, 0, RegRiz, Dw2Inval, Dw2Inval
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// fp regs.
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st(0), FloatReg|FloatAcc, 0, 0, 11, 33
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st(1), FloatReg, 0, 1, 12, 34
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@ -40246,16 +40246,16 @@ const reg_entry i386_regtab[] =
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0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0 } },
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RegRex64, RegEip, { 8, Dw2Inval } },
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{ "riz",
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0 } },
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RegRex64, RegRiz, { Dw2Inval, Dw2Inval } },
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{ "eiz",
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0 } },
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0, RegEiz, { Dw2Inval, Dw2Inval } },
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{ "riz",
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0 } },
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0, RegRiz, { Dw2Inval, Dw2Inval } },
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{ "st(0)",
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{ { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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