gdb/riscv: Update test to handle targets without an fpu
The FPU is optional on RISC-V. The gdb.base/float.exp test currently assumes that an fpu is always available on RISC-V. Update the test so that this is not the case. gdb/testsuite/ChangeLog: * gdb.base/float.exp: Handle RISC-V targets without an FPU.
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2018-12-11 Andrew Burgess <andrew.burgess@embecosm.com>
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* gdb.base/float.exp: Handle RISC-V targets without an FPU.
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2018-12-09 Philippe Waroquiers <philippe.waroquiers@skynet.be>
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* gdb.threads/tid-reuse.c (REUSE_TIME_CAP): Declare as 60.
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@ -111,7 +111,15 @@ if { [is_aarch64_target] } then {
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} elseif [istarget "sparc*-*-*"] then {
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gdb_test "info float" "f0.*f1.*f31.*d0.*d30.*" "info float"
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} elseif [istarget "riscv*-*-*"] then {
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gdb_test "info float" "ft0.*ft1.*ft11.*fflags.*frm.*fcsr.*" "info float"
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# RISC-V may or may not have an FPU
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gdb_test_multiple "info float" "info float" {
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-re "ft0.*ft1.*ft11.*fflags.*frm.*fcsr.*$gdb_prompt $" {
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pass "info float (with FPU)"
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}
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-re "No floating.point info available for this processor.*$gdb_prompt $" {
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pass "info float (without FPU)"
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}
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}
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} else {
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gdb_test "info float" "No floating.point info available for this processor." "info float (unknown target)"
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}
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