gas/
* config/tc-mips.c (nops_for_insn_or_target): Replace MIPS16_INSN_BRANCH with MIPS16_INSN_UNCOND_BRANCH and MIPS16_INSN_COND_BRANCH. include/opcode/ * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro. (MIPS16_INSN_BRANCH): Rename to... (MIPS16_INSN_COND_BRANCH): ... this. opcodes/ * mips-dis.c (print_mips16_insn_arg): Remove branch instruction type and delay slot determination. (print_insn_mips16): Extend branch instruction type and delay slot determination to cover all instructions. * mips16-opc.c (BR): Remove macro. (UBR, CBR): New macros. (mips16_opcodes): Update branch annotation for "b", "beqz", "bnez", "bteqz" and "btnez". Add branch annotation for "jalrc" and "jrc".
This commit is contained in:
Maciej W. Rozycki
parent
bf501491ea
commit
9a2c708887
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@ -1,3 +1,9 @@
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2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
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* config/tc-mips.c (nops_for_insn_or_target): Replace
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MIPS16_INSN_BRANCH with MIPS16_INSN_UNCOND_BRANCH and
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MIPS16_INSN_COND_BRANCH.
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2010-07-05 Jim Wilson <wilson@codesourcery.com>
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PR gas/10531
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@ -2730,7 +2730,9 @@ nops_for_insn_or_target (const struct mips_cl_insn *hist,
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if (tmp_nops > nops)
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nops = tmp_nops;
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}
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else if (mips_opts.mips16 && (insn->insn_mo->pinfo & MIPS16_INSN_BRANCH))
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else if (mips_opts.mips16
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&& (insn->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
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| MIPS16_INSN_COND_BRANCH)))
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{
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tmp_nops = nops_for_sequence (1, hist, insn);
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if (tmp_nops > nops)
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@ -1,3 +1,9 @@
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2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
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* mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
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(MIPS16_INSN_BRANCH): Rename to...
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(MIPS16_INSN_COND_BRANCH): ... this.
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2010-07-03 Alan Modra <amodra@gmail.com>
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* ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
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@ -1089,8 +1089,10 @@ extern int bfd_mips_num_opcodes;
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#define MIPS16_INSN_READ_PC 0x00002000
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/* Reads the general purpose register in MIPS16OP_*_REGR32. */
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#define MIPS16_INSN_READ_GPR_X 0x00004000
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/* Is a branch insn. */
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#define MIPS16_INSN_BRANCH 0x00010000
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/* Is an unconditional branch insn. */
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#define MIPS16_INSN_UNCOND_BRANCH 0x00008000
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/* Is a conditional branch insn. */
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#define MIPS16_INSN_COND_BRANCH 0x00010000
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/* The following flags have the same value for the mips16 opcode
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table:
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@ -1,3 +1,15 @@
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2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
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* mips-dis.c (print_mips16_insn_arg): Remove branch instruction
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type and delay slot determination.
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(print_insn_mips16): Extend branch instruction type and delay
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slot determination to cover all instructions.
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* mips16-opc.c (BR): Remove macro.
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(UBR, CBR): New macros.
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(mips16_opcodes): Update branch annotation for "b", "beqz",
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"bnez", "bteqz" and "btnez". Add branch annotation for "jalrc"
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and "jrc".
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2010-07-05 H.J. Lu <hongjiu.lu@intel.com>
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AVX Programming Reference (June, 2010)
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@ -1660,7 +1660,6 @@ print_mips16_insn_arg (char type,
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signedp = 1;
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pcrel = 1;
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branch = 1;
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info->insn_type = dis_condbranch;
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break;
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case 'q':
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nbits = 11;
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@ -1668,7 +1667,6 @@ print_mips16_insn_arg (char type,
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signedp = 1;
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pcrel = 1;
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branch = 1;
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info->insn_type = dis_branch;
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break;
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case 'A':
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nbits = 8;
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@ -1789,8 +1787,6 @@ print_mips16_insn_arg (char type,
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}
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info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
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(*info->print_address_func) (info->target, info);
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info->insn_type = dis_jsr;
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info->branch_delay_insns = 1;
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break;
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case 'l':
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@ -2082,12 +2078,19 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
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info);
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}
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/* Figure out branch instruction type and delay slot information. */
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if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
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info->branch_delay_insns = 1;
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if ((op->pinfo & (INSN_UNCOND_BRANCH_DELAY
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| MIPS16_INSN_UNCOND_BRANCH)) != 0)
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{
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info->branch_delay_insns = 1;
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if (info->insn_type != dis_jsr)
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if ((op->pinfo & INSN_WRITE_GPR_31) != 0)
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info->insn_type = dis_jsr;
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else
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info->insn_type = dis_branch;
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}
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else if ((op->pinfo & MIPS16_INSN_COND_BRANCH) != 0)
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info->insn_type = dis_condbranch;
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return length;
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}
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@ -33,7 +33,8 @@
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the opcodes table. */
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#define UBD INSN_UNCOND_BRANCH_DELAY
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#define BR MIPS16_INSN_BRANCH
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#define UBR MIPS16_INSN_UNCOND_BRANCH
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#define CBR MIPS16_INSN_COND_BRANCH
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#define WR_x MIPS16_INSN_WRITE_X
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#define WR_y MIPS16_INSN_WRITE_Y
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@ -85,10 +86,10 @@ const struct mips_opcode mips16_opcodes[] =
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{"addu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0, I1 },
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{"addu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0, I1 },
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{"and", "x,y", 0xe80c, 0xf81f, WR_x|RD_x|RD_y, 0, I1 },
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{"b", "q", 0x1000, 0xf800, BR, 0, I1 },
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{"b", "q", 0x1000, 0xf800, UBR, 0, I1 },
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{"beq", "x,y,p", 0, (int) M_BEQ, INSN_MACRO, 0, I1 },
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{"beq", "x,U,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1 },
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{"beqz", "x,p", 0x2000, 0xf800, BR|RD_x, 0, I1 },
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{"beqz", "x,p", 0x2000, 0xf800, CBR|RD_x, 0, I1 },
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{"bge", "x,y,p", 0, (int) M_BGE, INSN_MACRO, 0, I1 },
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{"bge", "x,8,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1 },
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{"bgeu", "x,y,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1 },
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@ -107,10 +108,10 @@ const struct mips_opcode mips16_opcodes[] =
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{"bltu", "x,8,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1 },
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{"bne", "x,y,p", 0, (int) M_BNE, INSN_MACRO, 0, I1 },
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{"bne", "x,U,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1 },
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{"bnez", "x,p", 0x2800, 0xf800, BR|RD_x, 0, I1 },
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{"bnez", "x,p", 0x2800, 0xf800, CBR|RD_x, 0, I1 },
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{"break", "6", 0xe805, 0xf81f, TRAP, 0, I1 },
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{"bteqz", "p", 0x6000, 0xff00, BR|RD_T, 0, I1 },
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{"btnez", "p", 0x6100, 0xff00, BR|RD_T, 0, I1 },
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{"bteqz", "p", 0x6000, 0xff00, CBR|RD_T, 0, I1 },
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{"btnez", "p", 0x6100, 0xff00, CBR|RD_T, 0, I1 },
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{"cmpi", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0, I1 },
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{"cmp", "x,y", 0xe80a, 0xf81f, WR_T|RD_x|RD_y, 0, I1 },
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{"cmp", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0, I1 },
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@ -226,10 +227,10 @@ const struct mips_opcode mips16_opcodes[] =
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{"sw", "R,V(S)", 0x6200, 0xff00, RD_31|RD_SP, 0, I1 },
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{"xor", "x,y", 0xe80e, 0xf81f, WR_x|RD_x|RD_y, 0, I1 },
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/* MIPS16e additions */
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{"jalrc", "x", 0xe8c0, 0xf8ff, WR_31|RD_x|TRAP, 0, I32 },
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{"jalrc", "R,x", 0xe8c0, 0xf8ff, WR_31|RD_x|TRAP, 0, I32 },
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{"jrc", "x", 0xe880, 0xf8ff, RD_x|TRAP, 0, I32 },
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{"jrc", "R", 0xe8a0, 0xffff, RD_31|TRAP, 0, I32 },
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{"jalrc", "x", 0xe8c0, 0xf8ff, UBR|WR_31|RD_x|TRAP, 0, I32 },
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{"jalrc", "R,x", 0xe8c0, 0xf8ff, UBR|WR_31|RD_x|TRAP, 0, I32 },
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{"jrc", "x", 0xe880, 0xf8ff, UBR|RD_x|TRAP, 0, I32 },
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{"jrc", "R", 0xe8a0, 0xffff, UBR|RD_31|TRAP, 0, I32 },
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{"restore", "M", 0x6400, 0xff80, WR_31|RD_SP|WR_SP|TRAP, 0, I32 },
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{"save", "m", 0x6480, 0xff80, RD_31|RD_SP|WR_SP|TRAP, 0, I32 },
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{"sdbbp", "6", 0xe801, 0xf81f, TRAP, 0, I32 },
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