gas/
* config/tc-ppc.c (parse_cpu): Rename altivec_or_spe to retain_flags. Handle -mvsx and -mpower7. (md_show_usage): Document -mpower7 and -mvsx. * doc/as.texinfo (Target PowerPC): Document -mvsx. * doc/c-ppc.texi (PowerPC-Opts): Document -mvsx and -mpower7. gas/testsuite/ * gas/ppc/power7.d: New. * gas/ppc/power7.s: Likewise. * gas/ppc/ppc.exp: Run power7 test. include/opcode/ * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New. opcodes/ * ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options. (print_insn_powerpc): Prepend 'vs' when printing VSX registers. (print_ppc_disassembler_options): Document -Mpower7 and -Mvsx. * ppc-opc.c (insert_xt6): New static function. (extract_xt6): Likewise. (insert_xa6): Likewise. (extract_xa6: Likewise. (insert_xb6): Likewise. (extract_xb6): Likewise. (insert_xb6s): Likewise. (extract_xb6s): Likewise. (XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK, XX3DM_MASK, PPCVSX): New. (powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x", "stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp".
This commit is contained in:
Peter Bergner
parent
dbe454a3b5
commit
9b4e57660d
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@ -1,3 +1,11 @@
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2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
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* config/tc-ppc.c (parse_cpu): Rename altivec_or_spe to retain_flags.
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Handle -mvsx and -mpower7.
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(md_show_usage): Document -mpower7 and -mvsx.
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* doc/as.texinfo (Target PowerPC): Document -mvsx.
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* doc/c-ppc.texi (PowerPC-Opts): Document -mvsx and -mpower7.
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2008-07-31 Peter Bergner <bergner@vnet.ibm.com>
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* config/tc-ppc.c (parse_cpu) <power6>: Accept Altivec instructions.
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@ -825,7 +825,8 @@ const size_t md_longopts_size = sizeof (md_longopts);
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static int
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parse_cpu (const char *arg)
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{
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ppc_cpu_t altivec_or_spe = ppc_cpu & (PPC_OPCODE_ALTIVEC | PPC_OPCODE_SPE);
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ppc_cpu_t retain_flags =
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ppc_cpu & (PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX | PPC_OPCODE_SPE);
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/* -mpwrx and -mpwr2 mean to assemble for the IBM POWER/2
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(RIOS2). */
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@ -873,7 +874,14 @@ parse_cpu (const char *arg)
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if (ppc_cpu == 0)
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ppc_cpu = PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC;
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altivec_or_spe |= PPC_OPCODE_ALTIVEC;
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retain_flags |= PPC_OPCODE_ALTIVEC;
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}
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else if (strcmp (arg, "vsx") == 0)
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{
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if (ppc_cpu == 0)
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ppc_cpu = PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC;
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retain_flags |= PPC_OPCODE_VSX;
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}
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else if (strcmp (arg, "e500") == 0 || strcmp (arg, "e500x2") == 0)
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{
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@ -893,7 +901,7 @@ parse_cpu (const char *arg)
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if (ppc_cpu == 0)
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ppc_cpu = PPC_OPCODE_PPC | PPC_OPCODE_EFS;
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altivec_or_spe |= PPC_OPCODE_SPE;
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retain_flags |= PPC_OPCODE_SPE;
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}
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/* -mppc64 and -m620 mean to assemble for the 64-bit PowerPC
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620. */
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@ -935,6 +943,13 @@ parse_cpu (const char *arg)
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| PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
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| PPC_OPCODE_ALTIVEC);
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}
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else if (strcmp (arg, "power7") == 0)
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{
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ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC
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| PPC_OPCODE_64 | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
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| PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX);
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}
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else if (strcmp (arg, "cell") == 0)
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{
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ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC
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@ -952,8 +967,8 @@ parse_cpu (const char *arg)
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else
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return 0;
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/* Make sure the the Altivec and SPE bits are not lost. */
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ppc_cpu |= altivec_or_spe;
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/* Make sure the the Altivec, VSX and SPE bits are not lost. */
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ppc_cpu |= retain_flags;
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return 1;
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}
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@ -1139,11 +1154,13 @@ PowerPC options:\n\
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-mpower4 generate code for Power4 architecture\n\
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-mpower5 generate code for Power5 architecture\n\
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-mpower6 generate code for Power6 architecture\n\
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-mpower7 generate code for Power7 architecture\n\
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-mcell generate code for Cell Broadband Engine architecture\n\
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-mcom generate code Power/PowerPC common instructions\n\
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-many generate code for any architecture (PWR/PWRX/PPC)\n"));
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fprintf (stream, _("\
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-maltivec generate code for AltiVec\n\
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-mvsx generate code for Vector-Scalar (VSX) instructions\n\
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-me300 generate code for PowerPC e300 family\n\
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-me500, -me500x2 generate code for Motorola e500 core complex\n\
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-me500mc, generate code for Freescale e500mc core complex\n\
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@ -409,7 +409,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
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[@b{-mpwrx}|@b{-mpwr2}|@b{-mpwr}|@b{-m601}|@b{-mppc}|@b{-mppc32}|@b{-m603}|@b{-m604}|
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@b{-m403}|@b{-m405}|@b{-mppc64}|@b{-m620}|@b{-mppc64bridge}|@b{-mbooke}|
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@b{-mbooke32}|@b{-mbooke64}]
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[@b{-mcom}|@b{-many}|@b{-maltivec}] [@b{-memb}]
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[@b{-mcom}|@b{-many}|@b{-maltivec}|@b{-mvsx}] [@b{-memb}]
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[@b{-mregnames}|@b{-mno-regnames}]
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[@b{-mrelocatable}|@b{-mrelocatable-lib}]
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[@b{-mlittle}|@b{-mlittle-endian}|@b{-mbig}|@b{-mbig-endian}]
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@ -82,6 +82,9 @@ Generate code for PowerPC e300 family.
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@item -maltivec
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Generate code for processors with AltiVec instructions.
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@item -mvsx
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Generate code for processors with Vector-Scalar (VSX) instructions.
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@item -mpower4
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Generate code for Power4 architecture.
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@ -91,6 +94,9 @@ Generate code for Power5 architecture.
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@item -mpower6
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Generate code for Power6 architecture.
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@item -mpower7
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Generate code for Power7 architecture.
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@item -mcell
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Generate code for Cell Broadband Engine architecture.
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@ -1,3 +1,9 @@
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2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
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* gas/ppc/power7.d: New.
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* gas/ppc/power7.s: Likewise.
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* gas/ppc/ppc.exp: Run power7 test.
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2008-08-01 H.J. Lu <hongjiu.lu@intel.com>
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* gas/cfi/cfi-i386.s: Remove tests for AVX register maps.
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@ -0,0 +1,57 @@
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#as: -a32 -mpower7
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#objdump: -dr -Mpower7
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#name: POWER7 tests (includes DFP, Altivec and VSX)
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.*: +file format elf32-powerpc.*
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Disassembly of section \.text:
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0+00 <power7>:
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0: 7c 64 2e 98 lxvd2x vs3,r4,r5
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4: 7c 64 2e d8 lxvd2ux vs3,r4,r5
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8: 7d 64 2e 99 lxvd2x vs43,r4,r5
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c: 7d 64 2e d9 lxvd2ux vs43,r4,r5
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10: 7c 64 2f 98 stxvd2x vs3,r4,r5
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14: 7c 64 2f d8 stxvd2ux vs3,r4,r5
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18: 7d 64 2f 99 stxvd2x vs43,r4,r5
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1c: 7d 64 2f d9 stxvd2ux vs43,r4,r5
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20: f0 64 28 50 xxmrghd vs3,vs4,vs5
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24: f1 6c 68 57 xxmrghd vs43,vs44,vs45
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28: f0 64 2b 50 xxmrgld vs3,vs4,vs5
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2c: f1 6c 6b 57 xxmrgld vs43,vs44,vs45
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30: f0 64 28 50 xxmrghd vs3,vs4,vs5
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34: f1 6c 68 57 xxmrghd vs43,vs44,vs45
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38: f0 64 2b 50 xxmrgld vs3,vs4,vs5
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3c: f1 6c 6b 57 xxmrgld vs43,vs44,vs45
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40: f0 64 29 50 xxpermdi vs3,vs4,vs5,1
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44: f1 6c 69 57 xxpermdi vs43,vs44,vs45,1
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48: f0 64 2a 50 xxpermdi vs3,vs4,vs5,2
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4c: f1 6c 6a 57 xxpermdi vs43,vs44,vs45,2
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50: f0 64 27 80 xvmovdp vs3,vs4
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54: f1 6c 67 87 xvmovdp vs43,vs44
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58: f0 64 27 80 xvmovdp vs3,vs4
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5c: f1 6c 67 87 xvmovdp vs43,vs44
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60: f0 64 2f 80 xvcpsgndp vs3,vs4,vs5
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64: f1 6c 6f 87 xvcpsgndp vs43,vs44,vs45
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68: 4c 00 03 24 doze
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6c: 4c 00 03 64 nap
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70: 4c 00 03 a4 sleep
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74: 4c 00 03 e4 rvwinkle
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78: 7c 83 01 34 prtyw r3,r4
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7c: 7d cd 01 74 prtyd r13,r14
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80: 7d 5c 02 a6 mfcfar r10
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84: 7d 7c 03 a6 mtcfar r11
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88: 7c 83 2b f8 cmpb r3,r4,r5
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8c: 7c c0 3c be mffgpr f6,r7
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90: 7d 00 4d be mftgpr r8,f9
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94: 7d 4b 66 2a lwzcix r10,r11,r12
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98: 7d ae 7e 2e lfdpx f13,r14,r15
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9c: ee 11 90 04 dadd f16,f17,f18
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a0: fe 96 c0 04 daddq f20,f22,f24
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a4: 7c 60 06 6c dss 3
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a8: 7e 00 06 6c dssall
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ac: 7c 25 22 ac dst r5,r4,1
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b0: 7e 08 3a ac dstt r8,r7,0
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b4: 7c 65 32 ec dstst r5,r6,3
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b8: 7e 44 2a ec dststt r4,r5,2
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bc: 4e 80 00 20 blr
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@ -0,0 +1,58 @@
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.file "power7.c"
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.section ".text"
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.align 2
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.p2align 4,,15
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.globl power7
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.type power7, @function
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power7:
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lxvd2x 3,4,5
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lxvd2ux 3,4,5
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lxvd2x 43,4,5
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lxvd2ux 43,4,5
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stxvd2x 3,4,5
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stxvd2ux 3,4,5
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stxvd2x 43,4,5
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stxvd2ux 43,4,5
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xxmrghd 3,4,5
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xxmrghd 43,44,45
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xxmrgld 3,4,5
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xxmrgld 43,44,45
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xxpermdi 3,4,5,0
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xxpermdi 43,44,45,0
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xxpermdi 3,4,5,3
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xxpermdi 43,44,45,3
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xxpermdi 3,4,5,1
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xxpermdi 43,44,45,1
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xxpermdi 3,4,5,2
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xxpermdi 43,44,45,2
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xvmovdp 3,4
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xvmovdp 43,44
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xvcpsgndp 3,4,4
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xvcpsgndp 43,44,44
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xvcpsgndp 3,4,5
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xvcpsgndp 43,44,45
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doze
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nap
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sleep
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rvwinkle
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prtyw 3,4
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prtyd 13,14
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mfcfar 10
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mtcfar 11
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cmpb 3,4,5
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mffgpr 6,7
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mftgpr 8,9
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lwzcix 10,11,12
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lfdpx 13,14,15
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dadd 16,17,18
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daddq 20,22,24
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dss 3
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dssall
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dst 5,4,1
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dstt 8,7,0
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dstst 5,6,3
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dststt 4,5,2
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blr
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.size power7,.-power7
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.ident "GCC: (GNU) 4.1.2 20070115 (prerelease) (SUSE Linux)"
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.section .note.GNU-stack,"",@progbits
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@ -46,5 +46,6 @@ if { [istarget powerpc*-*-*] } then {
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run_dump_test "e500mc"
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run_dump_test "cell"
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run_dump_test "power6"
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run_dump_test "power7"
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}
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}
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@ -1,3 +1,7 @@
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2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
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* ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
|
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2008-07-30 Michael J. Eager <eager@eagercon.com>
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* ppc.h (PPC_OPCODE_405): Define.
|
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|
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@ -157,6 +157,9 @@ extern const int powerpc_num_opcodes;
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/* Opcode is supported by PowerPC 405 processor. */
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#define PPC_OPCODE_405 0x40000000
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/* Opcode is supported by Vector-Scalar (VSX) Unit */
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#define PPC_OPCODE_VSX 0x80000000
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/* A macro to extract the major opcode from an instruction. */
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#define PPC_OP(i) (((i) >> 26) & 0x3f)
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@ -312,6 +315,10 @@ extern const unsigned int num_powerpc_operands;
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#define PPC_OPERAND_FSL (0x20000)
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#define PPC_OPERAND_FCR (0x40000)
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#define PPC_OPERAND_UDI (0x80000)
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/* This operand names a vector-scalar unit register. The disassembler
|
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prints these with a leading 'vs'. */
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#define PPC_OPERAND_VSR (0x100000)
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/* The POWER and PowerPC assemblers use a few macros. We keep them
|
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with the operands table for simplicity. The macro table is an
|
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|
|
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@ -1,3 +1,21 @@
|
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2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
|
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|
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* ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options.
|
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(print_insn_powerpc): Prepend 'vs' when printing VSX registers.
|
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(print_ppc_disassembler_options): Document -Mpower7 and -Mvsx.
|
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* ppc-opc.c (insert_xt6): New static function.
|
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(extract_xt6): Likewise.
|
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(insert_xa6): Likewise.
|
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(extract_xa6: Likewise.
|
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(insert_xb6): Likewise.
|
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(extract_xb6): Likewise.
|
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(insert_xb6s): Likewise.
|
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(extract_xb6s): Likewise.
|
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(XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK,
|
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XX3DM_MASK, PPCVSX): New.
|
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(powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x",
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"stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp".
|
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|
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2008-08-01 Pedro Alves <pedro@codesourcery.com>
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* Makefile.am ($(srcdir)/ia64-asmtab.c): Remove line continuation.
|
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|
|
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|
@ -107,7 +107,17 @@ powerpc_init_dialect (struct disassemble_info *info)
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if (info->disassembler_options
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&& strstr (info->disassembler_options, "power6") != NULL)
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dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC;
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dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
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| PPC_OPCODE_ALTIVEC;
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if (info->disassembler_options
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&& strstr (info->disassembler_options, "power7") != NULL)
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dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
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| PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX;
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if (info->disassembler_options
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&& strstr (info->disassembler_options, "vsx") != NULL)
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dialect |= PPC_OPCODE_VSX;
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if (info->disassembler_options
|
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&& strstr (info->disassembler_options, "any") != NULL)
|
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|
|
@ -321,6 +331,8 @@ print_insn_powerpc (bfd_vma memaddr,
|
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(*info->fprintf_func) (info->stream, "f%ld", value);
|
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else if ((operand->flags & PPC_OPERAND_VR) != 0)
|
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(*info->fprintf_func) (info->stream, "v%ld", value);
|
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else if ((operand->flags & PPC_OPERAND_VSR) != 0)
|
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(*info->fprintf_func) (info->stream, "vs%ld", value);
|
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else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
|
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(*info->print_address_func) (memaddr + value, info);
|
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else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
|
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|
|
@ -401,6 +413,8 @@ the -M switch:\n");
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fprintf (stream, " power4 Disassemble the Power4 instructions\n");
|
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fprintf (stream, " power5 Disassemble the Power5 instructions\n");
|
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fprintf (stream, " power6 Disassemble the Power6 instructions\n");
|
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fprintf (stream, " power7 Disassemble the Power7 instructions\n");
|
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fprintf (stream, " vsx Disassemble the Vector-Scalar (VSX) instructions\n");
|
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fprintf (stream, " 32 Do not disassemble 64-bit instructions\n");
|
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fprintf (stream, " 64 Allow disassembly of 64-bit instructions\n");
|
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}
|
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|
|
|
|||
|
|
@ -73,6 +73,14 @@ static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **)
|
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static long extract_sprg (unsigned long, ppc_cpu_t, int *);
|
||||
static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **);
|
||||
static long extract_tbr (unsigned long, ppc_cpu_t, int *);
|
||||
static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **);
|
||||
static long extract_xt6 (unsigned long, ppc_cpu_t, int *);
|
||||
static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **);
|
||||
static long extract_xa6 (unsigned long, ppc_cpu_t, int *);
|
||||
static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **);
|
||||
static long extract_xb6 (unsigned long, ppc_cpu_t, int *);
|
||||
static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **);
|
||||
static long extract_xb6s (unsigned long, ppc_cpu_t, int *);
|
||||
|
||||
/* The operands table.
|
||||
|
||||
|
|
@ -600,6 +608,28 @@ const struct powerpc_operand powerpc_operands[] =
|
|||
#define URC URB + 1
|
||||
{ 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
|
||||
|
||||
/* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
|
||||
#define XS6 URC + 1
|
||||
#define XT6 XS6
|
||||
{ 0x3f, -1, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
|
||||
|
||||
/* The XA field in an XX3 form instruction. This is split. */
|
||||
#define XA6 XT6 + 1
|
||||
{ 0x3f, -1, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
|
||||
|
||||
/* The XB field in an XX3 form instruction. This is split. */
|
||||
#define XB6 XA6 + 1
|
||||
{ 0x3f, -1, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
|
||||
|
||||
/* The XB field in an XX3 form instruction when it must be the same as
|
||||
the XA field in the instruction. This is used in extended mnemonics
|
||||
like xvmovdp. This is split. */
|
||||
#define XB6S XB6 + 1
|
||||
{ 0x3f, -1, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
|
||||
|
||||
/* The DM field in an XX3 form instruction. */
|
||||
#define DM XB6S + 1
|
||||
{ 0x3, 8, NULL, NULL, 0 },
|
||||
};
|
||||
|
||||
const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
|
||||
|
|
@ -1292,6 +1322,89 @@ extract_tbr (unsigned long insn,
|
|||
ret = 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
|
||||
|
||||
static unsigned long
|
||||
insert_xt6 (unsigned long insn,
|
||||
long value,
|
||||
ppc_cpu_t dialect ATTRIBUTE_UNUSED,
|
||||
const char **errmsg ATTRIBUTE_UNUSED)
|
||||
{
|
||||
return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5);
|
||||
}
|
||||
|
||||
static long
|
||||
extract_xt6 (unsigned long insn,
|
||||
ppc_cpu_t dialect ATTRIBUTE_UNUSED,
|
||||
int *invalid ATTRIBUTE_UNUSED)
|
||||
{
|
||||
return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f);
|
||||
}
|
||||
|
||||
/* The XA field in an XX3 form instruction. This is split. */
|
||||
|
||||
static unsigned long
|
||||
insert_xa6 (unsigned long insn,
|
||||
long value,
|
||||
ppc_cpu_t dialect ATTRIBUTE_UNUSED,
|
||||
const char **errmsg ATTRIBUTE_UNUSED)
|
||||
{
|
||||
return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3);
|
||||
}
|
||||
|
||||
static long
|
||||
extract_xa6 (unsigned long insn,
|
||||
ppc_cpu_t dialect ATTRIBUTE_UNUSED,
|
||||
int *invalid ATTRIBUTE_UNUSED)
|
||||
{
|
||||
return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
|
||||
}
|
||||
|
||||
/* The XB field in an XX3 form instruction. This is split. */
|
||||
|
||||
static unsigned long
|
||||
insert_xb6 (unsigned long insn,
|
||||
long value,
|
||||
ppc_cpu_t dialect ATTRIBUTE_UNUSED,
|
||||
const char **errmsg ATTRIBUTE_UNUSED)
|
||||
{
|
||||
return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
|
||||
}
|
||||
|
||||
static long
|
||||
extract_xb6 (unsigned long insn,
|
||||
ppc_cpu_t dialect ATTRIBUTE_UNUSED,
|
||||
int *invalid ATTRIBUTE_UNUSED)
|
||||
{
|
||||
return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f);
|
||||
}
|
||||
|
||||
/* The XB field in an XX3 form instruction when it must be the same as
|
||||
the XA field in the instruction. This is used for extended
|
||||
mnemonics like xvmovdp. This operand is marked FAKE. The insertion
|
||||
function just copies the XA field into the XB field, and the
|
||||
extraction function just checks that the fields are the same. */
|
||||
|
||||
static unsigned long
|
||||
insert_xb6s (unsigned long insn,
|
||||
long value ATTRIBUTE_UNUSED,
|
||||
ppc_cpu_t dialect ATTRIBUTE_UNUSED,
|
||||
const char **errmsg ATTRIBUTE_UNUSED)
|
||||
{
|
||||
return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1);
|
||||
}
|
||||
|
||||
static long
|
||||
extract_xb6s (unsigned long insn,
|
||||
ppc_cpu_t dialect ATTRIBUTE_UNUSED,
|
||||
int *invalid)
|
||||
{
|
||||
if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
|
||||
|| (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1)))
|
||||
*invalid = 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Macros used to form opcodes. */
|
||||
|
||||
|
|
@ -1437,6 +1550,12 @@ extract_tbr (unsigned long insn,
|
|||
/* An X form instruction. */
|
||||
#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
|
||||
|
||||
/* An XX3 form instruction. */
|
||||
#define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
|
||||
|
||||
#define XX3DM(op, xop, dm) (XX3 (op, ((unsigned long)(xop) & 0x1f)) \
|
||||
| ((((unsigned long)(dm)) & 0x3) << 8))
|
||||
|
||||
/* A Z form instruction. */
|
||||
#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
|
||||
|
||||
|
|
@ -1449,6 +1568,15 @@ extract_tbr (unsigned long insn,
|
|||
/* The mask for an X form instruction. */
|
||||
#define X_MASK XRC (0x3f, 0x3ff, 1)
|
||||
|
||||
/* The mask for an XX1 form instruction. */
|
||||
#define XX1_MASK X (0x3f, 0x3ff)
|
||||
|
||||
/* The mask for an XX3 form instruction. */
|
||||
#define XX3_MASK XX3 (0x3f, 0xff)
|
||||
|
||||
/* The mask for an XX3 form instruction with the DM bits specified. */
|
||||
#define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
|
||||
|
||||
/* The mask for a Z form instruction. */
|
||||
#define Z_MASK ZRC (0x3f, 0x1ff, 1)
|
||||
#define Z2_MASK ZRC (0x3f, 0xff, 1)
|
||||
|
|
@ -1701,6 +1829,7 @@ extract_tbr (unsigned long insn,
|
|||
#define PPC860 PPC
|
||||
#define PPCPS PPC_OPCODE_PPCPS
|
||||
#define PPCVEC PPC_OPCODE_ALTIVEC
|
||||
#define PPCVSX PPC_OPCODE_VSX
|
||||
#define POWER PPC_OPCODE_POWER
|
||||
#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
|
||||
#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
|
||||
|
|
@ -4441,6 +4570,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"divo.", XO(31,331,1,1), XO_MASK, M601, {RT, RA, RB}},
|
||||
{"lduxe", X(31,831), X_MASK, BOOKE64, {RT, RA0, RB}},
|
||||
|
||||
{"lxvd2x", X(31,844), XX1_MASK, PPCVSX, {XT6, RA, RB}},
|
||||
|
||||
{"slbmfev", X(31,851), XRA_MASK, PPC64, {RT, RB}},
|
||||
|
||||
{"lbzcix", X(31,853), X_MASK, POWER6, {RT, RA0, RB}},
|
||||
|
|
@ -4456,6 +4587,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"divso", XO(31,363,1,0), XO_MASK, M601, {RT, RA, RB}},
|
||||
{"divso.", XO(31,363,1,1), XO_MASK, M601, {RT, RA, RB}},
|
||||
|
||||
{"lxvd2ux", X(31,876), XX1_MASK, PPCVSX, {XT6, RA, RB}},
|
||||
|
||||
{"ldcix", X(31,885), X_MASK, POWER6, {RT, RA0, RB}},
|
||||
|
||||
{"stvlxl", X(31,903), X_MASK, CELL, {VS, RA0, RB}},
|
||||
|
|
@ -4526,6 +4659,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"divwuo", XO(31,459,1,0), XO_MASK, PPC, {RT, RA, RB}},
|
||||
{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, {RT, RA, RB}},
|
||||
|
||||
{"stxvd2x", X(31,972), XX1_MASK, PPCVSX, {XS6, RA, RB}},
|
||||
|
||||
{"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, {RT, RA}},
|
||||
{"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, {RT, RA}},
|
||||
{"tlbwe", X(31,978), X_MASK, PPC403|BOOKE, {RSO, RAOPT, SHO}},
|
||||
|
|
@ -4559,6 +4694,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"divwo", XO(31,491,1,0), XO_MASK, PPC, {RT, RA, RB}},
|
||||
{"divwo.", XO(31,491,1,1), XO_MASK, PPC, {RT, RA, RB}},
|
||||
|
||||
{"stxvd2ux", X(31,1004), XX1_MASK, PPCVSX, {XS6, RA, RB}},
|
||||
|
||||
{"tlbli", X(31,1010), XRTRA_MASK, PPC, {RB}},
|
||||
|
||||
{"stdcix", X(31,1013), X_MASK, POWER6, {RS, RA0, RB}},
|
||||
|
|
@ -4770,6 +4907,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"stfq", OP(60), OP_MASK, POWER2, {FRS, D, RA}},
|
||||
|
||||
{"psq_st", OP(60), OP_MASK, PPCPS, {FRS,PSD,RA,PSW,PSQ}},
|
||||
|
||||
{"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, {XT6, XA6, XB6}},
|
||||
{"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, {XT6, XA6, XB6}},
|
||||
{"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, {XT6, XA6, XB6, DM}},
|
||||
{"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, {XT6, XA6, XB6S}},
|
||||
{"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, {XT6, XA6, XB6}},
|
||||
|
||||
{"psq_stu", OP(61), OP_MASK, PPCPS, {FRS,PSD,RA,PSW,PSQ}},
|
||||
|
||||
{"stfqu", OP(61), OP_MASK, POWER2, {FRS, D, RA}},
|
||||
|
|
|
|||
Loading…
Reference in New Issue