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RISC-V: Fix SLTI disassembly 

2017-06-23  Andrew Waterman  <andrew@sifive.com>

	* riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
	alias; do not mark SLTI instruction as an alias.
This commit is contained in:
Andrew Waterman 2017-05-15 08:50:57 -07:00 committed by Palmer Dabbelt
parent 94f78a777c
commit 9bdfdbf929
2 changed files with 7 additions and 2 deletions
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5
opcodes/ChangeLog
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@ -1,3 +1,8 @@
2017-06-23 Andrew Waterman <andrew@sifive.com>
* riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
alias; do not mark SLTI instruction as an alias.
2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (RM_0FAE_REG_5): Removed.

4
opcodes/riscv-opc.c
View File

@ -245,9 +245,9 @@ const struct riscv_opcode riscv_opcodes[] =
{"snez", "I", "d,t", MATCH_SLTU, MASK_SLTU | MASK_RS1, match_opcode, INSN_ALIAS },
{"sltz", "I", "d,s", MATCH_SLT, MASK_SLT | MASK_RS2, match_opcode, INSN_ALIAS },
{"sgtz", "I", "d,t", MATCH_SLT, MASK_SLT | MASK_RS1, match_opcode, INSN_ALIAS },
{"slti", "I", "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, INSN_ALIAS },
{"slti", "I", "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, 0 },
{"slt", "I", "d,s,t", MATCH_SLT, MASK_SLT, match_opcode, 0 },
{"slt", "I", "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, 0 },
{"slt", "I", "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, INSN_ALIAS },
{"sltiu", "I", "d,s,j", MATCH_SLTIU, MASK_SLTIU, match_opcode, 0 },
{"sltu", "I", "d,s,t", MATCH_SLTU, MASK_SLTU, match_opcode, 0 },
{"sltu", "I", "d,s,j", MATCH_SLTIU, MASK_SLTIU, match_opcode, INSN_ALIAS },