Add support for new target 'csky'.
2018-08-28 Jiangshuai Li <jiangshuai_li@c-sky.com> Hafiz Abid Qadeer <abidh@codesourcery.com> Don Breazeal <donb@codesourcery.com> * csky-linux-tdep.c: New file. * csky-tdep.c: Likewise. * csky-tdep.h: Likewise. * Makefile.in (ALL_TARGET_OBS): Add csky-linux-tdep.o and csky-tdep.o. (HFILES_NO_SRCDIR): Add csky-tdep.h. (ALLDEPFILES): Add csky-linux-tdep.c and csky-tdep.c * configure.tgt: Add csky support.
This commit is contained in:
Hafiz Abid Qadeer
parent
626887ddc3
commit
9d24df82ec
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@ -1,3 +1,16 @@
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2018-08-28 Jiangshuai Li <jiangshuai_li@c-sky.com>
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Hafiz Abid Qadeer <abidh@codesourcery.com>
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Don Breazeal <donb@codesourcery.com>
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* csky-linux-tdep.c: New file.
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* csky-tdep.c: Likewise.
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* csky-tdep.h: Likewise.
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* Makefile.in (ALL_TARGET_OBS): Add csky-linux-tdep.o and
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csky-tdep.o.
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(HFILES_NO_SRCDIR): Add csky-tdep.h.
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(ALLDEPFILES): Add csky-linux-tdep.c and csky-tdep.c
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* configure.tgt: Add csky support.
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2018-08-27 Jan Vrany <jan.vrany@fit.cvut.cz>
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* python/py-framefilter.c (py_print_frame): Print frame architecture
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@ -687,6 +687,8 @@ ALL_TARGET_OBS = \
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bsd-uthread.o \
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cris-linux-tdep.o \
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cris-tdep.o \
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csky-linux-tdep.o \
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csky-tdep.o \
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dicos-tdep.o \
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fbsd-tdep.o \
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frv-linux-tdep.o \
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@ -1209,6 +1211,7 @@ HFILES_NO_SRCDIR = \
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completer.h \
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cp-abi.h \
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cp-support.h \
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csky-tdep.h \
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ctf.h \
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d-lang.h \
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darwin-nat.h \
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@ -2215,6 +2218,8 @@ ALLDEPFILES = \
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bfin-tdep.c \
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bsd-kvm.c \
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bsd-uthread.c \
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csky-linux-tdep.c \
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csky-tdep.c \
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darwin-nat.c \
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dicos-tdep.c \
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fbsd-nat.c \
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@ -206,6 +206,17 @@ cris*)
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gdb_target_obs="cris-tdep.o cris-linux-tdep.o linux-tdep.o solib-svr4.o"
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;;
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csky*-*-linux*)
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# Target: CSKY running GNU/Linux
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gdb_target_obs="csky-tdep.o csky-linux-tdep.o glibc-tdep.o \
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linux-tdep.o solib-svr4.o"
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;;
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csky*-*-*)
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# Target: CSKY bare metal
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gdb_target_obs="csky-tdep.o"
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;;
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frv-*-*)
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# Target: Fujitsu FRV processor
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gdb_target_obs="frv-tdep.o frv-linux-tdep.o linux-tdep.o solib-frv.o"
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@ -0,0 +1,263 @@
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/* Target-dependent code for GNU/Linux on CSKY.
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Copyright (C) 2012-2018 Free Software Foundation, Inc.
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Contributed by C-SKY Microsystems and Mentor Graphics.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "defs.h"
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#include "osabi.h"
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#include "glibc-tdep.h"
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#include "linux-tdep.h"
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#include "gdbarch.h"
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#include "solib-svr4.h"
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#include "regset.h"
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#include "trad-frame.h"
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#include "tramp-frame.h"
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#include "csky-tdep.h"
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/* Functions, definitions, and data structures for C-Sky core file debug. */
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/* General regset pc, r1, r0, psr, r2-r31 for CK810. */
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#define SIZEOF_CSKY_GREGSET 34*4
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/* Float regset fesr fsr fr0-fr31 for CK810. */
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#define SIZEOF_CSKY_FREGSET 34*4
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/* Offset mapping table from core_section to regcache of general
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registers for ck810. */
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static const int csky_gregset_offset[] =
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{
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72, 1, 0, 89, 2, /* pc, r1, r0, psr, r2. */
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3, 4, 5, 6, 7, /* r3 ~ r32. */
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8, 9, 10, 11, 12,
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13, 14, 15, 16, 17,
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18, 19, 20, 21, 22,
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23, 24, 25, 26, 27,
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28, 29, 30, 31
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};
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/* Offset mapping table from core_section to regcache of float
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registers for ck810. */
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static const int csky_fregset_offset[] =
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{
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122, 123, 40, 41, 42, /* fcr, fesr, fr0 ~ fr2. */
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43, 44, 45, 46, 47, /* fr3 ~ fr15. */
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48, 49, 50, 51, 52,
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53, 54, 55
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};
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/* Implement the supply_regset hook for GP registers in core files. */
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static void
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csky_supply_gregset (const struct regset *regset,
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struct regcache *regcache, int regnum,
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const void *regs, size_t len)
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{
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int i, gregset_num;
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const gdb_byte *gregs = (const gdb_byte *) regs ;
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gdb_assert (len >= SIZEOF_CSKY_GREGSET);
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gregset_num = ARRAY_SIZE (csky_gregset_offset);
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for (i = 0; i < gregset_num; i++)
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{
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if ((regnum == csky_gregset_offset[i] || regnum == -1)
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&& csky_gregset_offset[i] != -1)
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regcache->raw_supply (csky_gregset_offset[i], gregs + 4 * i);
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}
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}
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/* Implement the collect_regset hook for GP registers in core files. */
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static void
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csky_collect_gregset (const struct regset *regset,
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const struct regcache *regcache,
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int regnum, void *gregs_buf, size_t len)
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{
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int regno, gregset_num;
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gdb_byte *gregs = (gdb_byte *) gregs_buf ;
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gdb_assert (len >= SIZEOF_CSKY_GREGSET);
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gregset_num = ARRAY_SIZE (csky_gregset_offset);
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for (regno = 0; regno < gregset_num; regno++)
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{
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if ((regnum == csky_gregset_offset[regno] || regnum == -1)
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&& csky_gregset_offset[regno] != -1)
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regcache->raw_collect (regno,
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gregs + 4 + csky_gregset_offset[regno]);
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}
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}
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/* Implement the supply_regset hook for FP registers in core files. */
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void
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csky_supply_fregset (const struct regset *regset,
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struct regcache *regcache, int regnum,
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const void *regs, size_t len)
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{
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int i;
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int offset = 0;
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struct gdbarch *gdbarch = regcache->arch ();
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const gdb_byte *fregs = (const gdb_byte *) regs;
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int fregset_num = ARRAY_SIZE (csky_fregset_offset);
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gdb_assert (len >= SIZEOF_CSKY_FREGSET);
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for (i = 0; i < fregset_num; i++)
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{
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if ((regnum == csky_fregset_offset[i] || regnum == -1)
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&& csky_fregset_offset[i] != -1)
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{
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int num = csky_fregset_offset[i];
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offset += register_size (gdbarch, num);
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regcache->raw_supply (csky_fregset_offset[i], fregs + offset);
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}
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}
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}
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/* Implement the collect_regset hook for FP registers in core files. */
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static void
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csky_collect_fregset (const struct regset *regset,
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const struct regcache *regcache,
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int regnum, void *fregs_buf, size_t len)
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{
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int regno;
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struct gdbarch *gdbarch = regcache->arch ();
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gdb_byte *fregs = (gdb_byte *) fregs_buf ;
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int fregset_num = ARRAY_SIZE (csky_fregset_offset);
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int offset = 0;
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gdb_assert (len >= SIZEOF_CSKY_FREGSET);
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for (regno = 0; regno < fregset_num; regno++)
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{
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if ((regnum == csky_fregset_offset[regno] || regnum == -1)
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&& csky_fregset_offset[regno] != -1)
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{
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offset += register_size (gdbarch, csky_fregset_offset[regno]);
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regcache->raw_collect (regno, fregs + offset);
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}
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}
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}
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static const struct regset csky_regset_general =
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{
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NULL,
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csky_supply_gregset,
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csky_collect_gregset
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};
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static const struct regset csky_regset_float =
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{
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NULL,
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csky_supply_fregset,
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csky_collect_fregset
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};
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/* Iterate over core file register note sections. */
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static void
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csky_linux_iterate_over_regset_sections (struct gdbarch *gdbarch,
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iterate_over_regset_sections_cb *cb,
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void *cb_data,
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const struct regcache *regcache)
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{
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cb (".reg", sizeof (csky_gregset_offset), sizeof (csky_gregset_offset),
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&csky_regset_general, NULL, cb_data);
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cb (".reg2", sizeof (csky_fregset_offset), sizeof (csky_fregset_offset),
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&csky_regset_float, NULL, cb_data);
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}
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static void
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csky_linux_rt_sigreturn_init (const struct tramp_frame *self,
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struct frame_info *this_frame,
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struct trad_frame_cache *this_cache,
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CORE_ADDR func)
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{
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int i;
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CORE_ADDR sp = get_frame_register_unsigned (this_frame, 14);
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CORE_ADDR base = sp + CSKY_SIGINFO_OFFSET + CSKY_SIGINFO_SIZE
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+ CSKY_UCONTEXT_SIGCONTEXT
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+ CSKY_SIGCONTEXT_SC_USP
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+ CSKY_SIGCONTEXT_SC_A0;
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/* Set addrs of R0 ~ R13. */
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for (i = 0; i < 14; i++)
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trad_frame_set_reg_addr (this_cache, i, base + i * 4);
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/* Set addrs of SP(R14) and R15. */
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trad_frame_set_reg_addr (this_cache, 14, base - 4);
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trad_frame_set_reg_addr (this_cache, 15, base + 4 * 14);
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/* Set addrs of R16 ~ R31. */
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for (i = 15; i < 31; i++)
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trad_frame_set_reg_addr (this_cache, i, base + i * 4);
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/* Set addrs of PSR and PC. */
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trad_frame_set_reg_addr (this_cache, 89, base + 4 * 33);
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trad_frame_set_reg_addr (this_cache, 72, base + 4 * 34);
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trad_frame_set_id (this_cache, frame_id_build (sp, func));
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}
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static struct tramp_frame
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csky_linux_rt_sigreturn_tramp_frame = {
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SIGTRAMP_FRAME,
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4,
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{
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{ CSKY_MOVI_R7_173, ULONGEST_MAX },
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{ CSKY_TRAP_0, ULONGEST_MAX },
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{ TRAMP_SENTINEL_INSN }
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},
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csky_linux_rt_sigreturn_init
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};
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/* Hook function for gdbarch_register_osabi. */
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static void
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csky_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
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{
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linux_init_abi (info, gdbarch);
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/* Shared library handling. */
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set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
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set_gdbarch_skip_solib_resolver (gdbarch, glibc_skip_solib_resolver);
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set_solib_svr4_fetch_link_map_offsets (gdbarch,
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svr4_ilp32_fetch_link_map_offsets);
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/* Enable TLS support. */
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set_gdbarch_fetch_tls_load_module_address (gdbarch,
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svr4_fetch_objfile_link_map);
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/* Core file support. */
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set_gdbarch_iterate_over_regset_sections (
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gdbarch, csky_linux_iterate_over_regset_sections);
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/* Append tramp frame unwinder for SIGNAL. */
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tramp_frame_prepend_unwinder (gdbarch,
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&csky_linux_rt_sigreturn_tramp_frame);
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}
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void
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_initialize_csky_linux_tdep (void)
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{
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gdbarch_register_osabi (bfd_arch_csky, 0, GDB_OSABI_LINUX,
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csky_linux_init_abi);
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}
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,355 @@
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/* Target-dependent code for the CSKY architecture, for GDB.
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Copyright (C) 2010-2018 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef CSKY_TDEP_H
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#define CSKY_TDEP_H
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/* How to interpret the contents of the link register. */
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enum lr_type_t
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{
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LR_TYPE_R15,
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LR_TYPE_EPC,
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LR_TYPE_FPC
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};
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/* Target-dependent structure in gdbarch. */
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struct gdbarch_tdep
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{
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/* This is Unused. */
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};
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/* Instruction sizes. */
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enum csky_insn_size_t
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{
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CSKY_INSN_SIZE16 = 2,
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CSKY_INSN_SIZE32 = 4
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};
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/* CSKY register numbers. */
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enum csky_regnum
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{
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CSKY_R0_REGNUM = 0, /* General registers. */
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CSKY_R15_REGNUM = 15,
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CSKY_PC_REGNUM = 72,
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CSKY_HI_REGNUM = 20,
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CSKY_LO_REGNUM = 21,
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CSKY_CR0_REGNUM = 89,
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CSKY_VBR_REGNUM = CSKY_CR0_REGNUM + 1,
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CSKY_EPSR_REGNUM = CSKY_CR0_REGNUM + 2,
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CSKY_FPSR_REGNUM = CSKY_CR0_REGNUM + 3,
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CSKY_EPC_REGNUM = CSKY_CR0_REGNUM + 4,
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CSKY_FPC_REGNUM = CSKY_CR0_REGNUM + 5,
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/* Float register 0. */
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CSKY_FR0_REGNUM = 40,
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CSKY_VCR0_REGNUM = 121,
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CSKY_MMU_REGNUM = 128,
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CSKY_PROFCR_REGNUM = 140,
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CSKY_PROFGR_REGNUM = 144,
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CSKY_FP_REGNUM = 8,
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/* Vector register 0. */
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CSKY_VR0_REGNUM = 56,
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/* m32r calling convention. */
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CSKY_SP_REGNUM = CSKY_R0_REGNUM + 14,
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CSKY_RET_REGNUM = CSKY_R0_REGNUM,
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/* Argument registers. */
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CSKY_ABI_A0_REGNUM = 0,
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CSKY_ABI_LAST_ARG_REGNUM = 3,
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/* Link register, r15. */
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CSKY_LR_REGNUM = CSKY_R15_REGNUM,
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/* Processor status register, cr0. */
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CSKY_PSR_REGNUM = CSKY_CR0_REGNUM,
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CSKY_MAX_REGISTER_SIZE = 16,
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CSKY_MAX_REGS = 253
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};
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/* ICE registers. */
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#define CSKY_CRBANK_NUM_REGS 32
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/* Number of processor registers w/o ICE registers. */
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#define CSKY_NUM_REGS (CSKY_MAX_REGS - CSKY_CRBANK_NUM_REGS)
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/* size. */
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#define CSKY_16_ST_SIZE(insn) (1 << ((insn & 0x1800) >> 11))
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/* rx. */
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#define CSKY_16_ST_ADDR_REGNUM(insn) ((insn & 0x700) >> 8)
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/* disp. */
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#define CSKY_16_ST_OFFSET(insn) ((insn & 0x1f) << ((insn & 0x1800) >> 11))
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/* ry. */
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#define CSKY_16_ST_VAL_REGNUM(insn) ((insn & 0xe0) >> 5)
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/* st16.w rz, (sp, disp). */
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#define CSKY_16_IS_STWx0(insn) ((insn & 0xf800) == 0xb800)
|
||||
#define CSKY_16_STWx0_VAL_REGNUM(insn) CSKY_16_ST_ADDR_REGNUM (insn)
|
||||
|
||||
/* disp. */
|
||||
#define CSKY_16_STWx0_OFFSET(insn) \
|
||||
((((insn & 0x700) >> 3) + (insn & 0x1f)) << 2)
|
||||
|
||||
/* Check ld16 but not ld16 sp. */
|
||||
#define CSKY_16_IS_LD(insn) \
|
||||
(((insn & 0xe000) == 0x8000) && (insn & 0x1800) != 0x1800)
|
||||
/* size. */
|
||||
#define CSKY_16_LD_SIZE(insn) CSKY_16_ST_SIZE (insn)
|
||||
/* rx. */
|
||||
#define CSKY_16_LD_ADDR_REGNUM(insn) CSKY_16_ST_ADDR_REGNUM (insn)
|
||||
/* disp. */
|
||||
#define CSKY_16_LD_OFFSET(insn) CSKY_16_ST_OFFSET (insn)
|
||||
|
||||
/* ld16.w rz,(sp,disp). */
|
||||
#define CSKY_16_IS_LDWx0(insn) ((insn & 0xf800) == 0x9800)
|
||||
/*disp. */
|
||||
#define CSKY_16_LDWx0_OFFSET(insn) CSKY_16_STWx0_OFFSET (insn)
|
||||
|
||||
/* st32.b/h/w/d. */
|
||||
#define CSKY_32_IS_ST(insn) ((insn & 0xfc00c000) == 0xdc000000)
|
||||
|
||||
/* size: b/h/w/d. */
|
||||
#define CSKY_32_ST_SIZE(insn) (1 << ((insn & 0x3000) >> 12))
|
||||
/* rx. */
|
||||
#define CSKY_32_ST_ADDR_REGNUM(insn) ((insn & 0x001f0000) >> 16)
|
||||
/* disp. */
|
||||
#define CSKY_32_ST_OFFSET(insn) ((insn & 0xfff) << ((insn & 0x3000) >> 12))
|
||||
/* ry. */
|
||||
#define CSKY_32_ST_VAL_REGNUM(insn) ((insn & 0x03e00000) >> 21)
|
||||
|
||||
/* stw ry, (sp, disp). */
|
||||
#define CSKY_32_IS_STWx0(insn) ((insn & 0xfc1ff000) == 0xdc0e2000)
|
||||
|
||||
/* stm32 ry-rz, (rx). */
|
||||
#define CSKY_32_IS_STM(insn) ((insn & 0xfc00ffe0) == 0xd4001c20)
|
||||
/* rx. */
|
||||
#define CSKY_32_STM_ADDR_REGNUM(insn) CSKY_32_ST_ADDR_REGNUM (insn)
|
||||
/* Count of registers. */
|
||||
#define CSKY_32_STM_SIZE(insn) (insn & 0x1f)
|
||||
/* ry. */
|
||||
#define CSKY_32_STM_VAL_REGNUM(insn) ((insn & 0x03e00000) >> 21)
|
||||
/* stm32 ry-rz, (sp). */
|
||||
#define CSKY_32_IS_STMx0(insn) ((insn & 0xfc1fffe0) == 0xd40e1c20)
|
||||
|
||||
/* str32.b/h/w rz, (rx, ry << offset). */
|
||||
#define CSKY_32_IS_STR(insn) \
|
||||
(((insn & 0xfc000000) == 0xd4000000) && !(CSKY_32_IS_STM (insn)))
|
||||
/* rx. */
|
||||
#define CSKY_32_STR_X_REGNUM(insn) CSKY_32_ST_ADDR_REGNUM (insn)
|
||||
/* ry. */
|
||||
#define CSKY_32_STR_Y_REGNUM(insn) ((insn >> 21) & 0x1f)
|
||||
/* size: b/h/w. */
|
||||
#define CSKY_32_STR_SIZE(insn) (1 << ((insn & 0x0c00) >> 10))
|
||||
/* imm (for rx + ry * imm). */
|
||||
#define CSKY_32_STR_OFFSET(insn) ((insn & 0x000003e0) >> 5)
|
||||
|
||||
/* stex32.w rz, (rx, disp). */
|
||||
#define CSKY_32_IS_STEX(insn) ((insn & 0xfc00f000) == 0xdc007000)
|
||||
/* rx. */
|
||||
#define CSKY_32_STEX_ADDR_REGNUM(insn) ((insn & 0x1f0000) >> 16)
|
||||
/* disp. */
|
||||
#define CSKY_32_STEX_OFFSET(insn) ((insn & 0x0fff) << 2)
|
||||
|
||||
/* ld.b/h/w. */
|
||||
#define CSKY_32_IS_LD(insn) ((insn & 0xfc00c000) == 0xd8000000)
|
||||
/* size. */
|
||||
#define CSKY_32_LD_SIZE(insn) CSKY_32_ST_SIZE (insn)
|
||||
/* rx. */
|
||||
#define CSKY_32_LD_ADDR_REGNUM(insn) CSKY_32_ST_ADDR_REGNUM (insn)
|
||||
/* disp. */
|
||||
#define CSKY_32_LD_OFFSET(insn) CSKY_32_ST_OFFSET (insn)
|
||||
#define CSKY_32_IS_LDM(insn) ((insn & 0xfc00ffe0) == 0xd0001c20)
|
||||
/* rx. */
|
||||
#define CSKY_32_LDM_ADDR_REGNUM(insn) CSKY_32_STM_ADDR_REGNUM (insn)
|
||||
/* Count of registers. */
|
||||
#define CSKY_32_LDM_SIZE(insn) CSKY_32_STM_SIZE (insn)
|
||||
|
||||
/* ldr32.b/h/w rz, (rx, ry << offset). */
|
||||
#define CSKY_32_IS_LDR(insn) \
|
||||
(((insn & 0xfc00fe00) == 0xd0000000) && !(CSKY_32_IS_LDM (insn)))
|
||||
/* rx. */
|
||||
#define CSKY_32_LDR_X_REGNUM(insn) CSKY_32_STR_X_REGNUM (insn)
|
||||
/* ry. */
|
||||
#define CSKY_32_LDR_Y_REGNUM(insn) CSKY_32_STR_Y_REGNUM (insn)
|
||||
/* size: b/h/w. */
|
||||
#define CSKY_32_LDR_SIZE(insn) CSKY_32_STR_SIZE (insn)
|
||||
/* imm (for rx + ry*imm). */
|
||||
#define CSKY_32_LDR_OFFSET(insn) CSKY_32_STR_OFFSET (insn)
|
||||
|
||||
#define CSKY_32_IS_LDEX(insn) ((insn & 0xfc00f000) == 0xd8007000)
|
||||
/* rx. */
|
||||
#define CSKY_32_LDEX_ADDR_REGNUM(insn) CSKY_32_STEX_ADDR_REGNUM (insn)
|
||||
/* disp. */
|
||||
#define CSKY_32_LDEX_OFFSET(insn) CSKY_32_STEX_OFFSET (insn)
|
||||
|
||||
/* subi.sp sp, disp. */
|
||||
#define CSKY_16_IS_SUBI0(insn) ((insn & 0xfce0) == 0x1420)
|
||||
/* disp. */
|
||||
#define CSKY_16_SUBI_IMM(insn) ((((insn & 0x300) >> 3) + (insn & 0x1f)) << 2)
|
||||
|
||||
/* subi32 sp,sp,oimm12. */
|
||||
#define CSKY_32_IS_SUBI0(insn) ((insn & 0xfffff000) == 0xe5ce1000)
|
||||
/* oimm12. */
|
||||
#define CSKY_32_SUBI_IMM(insn) ((insn & 0xfff) + 1)
|
||||
|
||||
/* push16. */
|
||||
#define CSKY_16_IS_PUSH(insn) ((insn & 0xffe0) == 0x14c0)
|
||||
#define CSKY_16_IS_PUSH_R15(insn) ((insn & 0x10) == 0x10)
|
||||
#define CSKY_16_PUSH_LIST1(insn) (insn & 0xf) /* r4 - r11. */
|
||||
|
||||
/* pop16. */
|
||||
#define CSKY_16_IS_POP(insn) ((insn & 0xffe0) == 0x1480)
|
||||
#define CSKY_16_IS_POP_R15(insn) CSKY_16_IS_PUSH_R15 (insn)
|
||||
#define CSKY_16_POP_LIST1(insn) CSKY_16_PUSH_LIST1 (insn) /* r4 - r11. */
|
||||
|
||||
/* push32. */
|
||||
#define CSKY_32_IS_PUSH(insn) ((insn & 0xfffffe00) == 0xebe00000)
|
||||
#define CSKY_32_IS_PUSH_R29(insn) ((insn & 0x100) == 0x100)
|
||||
#define CSKY_32_IS_PUSH_R15(insn) ((insn & 0x10) == 0x10)
|
||||
#define CSKY_32_PUSH_LIST1(insn) (insn & 0xf) /* r4 - r11. */
|
||||
#define CSKY_32_PUSH_LIST2(insn) ((insn & 0xe0) >> 5) /* r16 - r17. */
|
||||
|
||||
/* pop32. */
|
||||
#define CSKY_32_IS_POP(insn) ((insn & 0xfffffe00) == 0xebc00000)
|
||||
#define CSKY_32_IS_POP_R29(insn) CSKY_32_IS_PUSH_R29 (insn)
|
||||
#define CSKY_32_IS_POP_R15(insn) CSKY_32_IS_PUSH_R15 (insn)
|
||||
#define CSKY_32_POP_LIST1(insn) CSKY_32_PUSH_LIST1 (insn) /* r4 - r11. */
|
||||
#define CSKY_32_POP_LIST2(insn) CSKY_32_PUSH_LIST2 (insn) /* r16 - r17. */
|
||||
|
||||
/* Adjust sp by r4(l0). */
|
||||
/* lrw r4, literal. */
|
||||
#define CSKY_16_IS_LRW4(x) (((x) &0xfce0) == 0x1080)
|
||||
/* movi r4, imm8. */
|
||||
#define CSKY_16_IS_MOVI4(x) (((x) &0xff00) == 0x3400)
|
||||
|
||||
/* addi r4, oimm8. */
|
||||
#define CSKY_16_IS_ADDI4(x) (((x) &0xff00) == 0x2400)
|
||||
/* subi r4, oimm8. */
|
||||
#define CSKY_16_IS_SUBI4(x) (((x) &0xff00) == 0x2c00)
|
||||
|
||||
/* nor16 r4, r4. */
|
||||
#define CSKY_16_IS_NOR4(x) ((x) == 0x6d12)
|
||||
|
||||
/* lsli r4, r4, imm5. */
|
||||
#define CSKY_16_IS_LSLI4(x) (((x) &0xffe0) == 0x4480)
|
||||
/* bseti r4, imm5. */
|
||||
#define CSKY_16_IS_BSETI4(x) (((x) &0xffe0) == 0x3ca0)
|
||||
/* bclri r4, imm5. */
|
||||
#define CSKY_16_IS_BCLRI4(x) (((x) &0xffe0) == 0x3c80)
|
||||
|
||||
/* subu sp, r4. */
|
||||
#define CSKY_16_IS_SUBU4(x) ((x) == 0x6392)
|
||||
|
||||
#define CSKY_16_IS_R4_ADJUSTER(x) \
|
||||
(CSKY_16_IS_ADDI4 (x) || CSKY_16_IS_SUBI4 (x) || CSKY_16_IS_BSETI4 (x) \
|
||||
|| CSKY_16_IS_BCLRI4 (x) || CSKY_16_IS_NOR4 (x) || CSKY_16_IS_LSLI4 (x))
|
||||
|
||||
/* lrw r4, literal. */
|
||||
#define CSKY_32_IS_LRW4(x) (((x) &0xffff0000) == 0xea840000)
|
||||
/* movi r4, imm16. */
|
||||
#define CSKY_32_IS_MOVI4(x) (((x) &0xffff0000) == 0xea040000)
|
||||
/* movih r4, imm16. */
|
||||
#define CSKY_32_IS_MOVIH4(x) (((x) &0xffff0000) == 0xea240000)
|
||||
/* bmaski r4, oimm5. */
|
||||
#define CSKY_32_IS_BMASKI4(x) (((x) &0xfc1fffff) == 0xc4005024)
|
||||
/* addi r4, r4, oimm12. */
|
||||
#define CSKY_32_IS_ADDI4(x) (((x) &0xfffff000) == 0xe4840000)
|
||||
/* subi r4, r4, oimm12. */
|
||||
#define CSKY_32_IS_SUBI4(x) (((x) &0xfffff000) == 0xe4810000)
|
||||
|
||||
/* nor32 r4, r4, r4. */
|
||||
#define CSKY_32_IS_NOR4(x) ((x) == 0xc4842484)
|
||||
/* rotli r4, r4, imm5. */
|
||||
#define CSKY_32_IS_ROTLI4(x) (((x) &0xfc1fffff) == 0xc4044904)
|
||||
/* lsli r4, r4, imm5. */
|
||||
#define CSKY_32_IS_LISI4(x) (((x) &0xfc1fffff) == 0xc4044824)
|
||||
/* bseti32 r4, r4, imm5. */
|
||||
#define CSKY_32_IS_BSETI4(x) (((x) &0xfc1fffff) == 0xc4042844)
|
||||
/* bclri32 r4, r4, imm5. */
|
||||
#define CSKY_32_IS_BCLRI4(x) (((x) &0xfc1fffff) == 0xc4042824)
|
||||
/* ixh r4, r4, r4. */
|
||||
#define CSKY_32_IS_IXH4(x) ((x) == 0xc4840824)
|
||||
/* ixw r4, r4, r4. */
|
||||
#define CSKY_32_IS_IXW4(x) ((x) == 0xc4840844)
|
||||
/* subu32 sp, sp, r4. */
|
||||
#define CSKY_32_IS_SUBU4(x) ((x) == 0xc48e008e)
|
||||
|
||||
#define CSKY_32_IS_R4_ADJUSTER(x) \
|
||||
(CSKY_32_IS_ADDI4 (x) || CSKY_32_IS_SUBI4 (x) || CSKY_32_IS_ROTLI4 (x) \
|
||||
|| CSKY_32_IS_IXH4 (x) || CSKY_32_IS_IXW4 (x) || CSKY_32_IS_NOR4 (x) \
|
||||
|| CSKY_32_IS_BSETI4 (x) || CSKY_32_IS_BCLRI4 (x) || CSKY_32_IS_LISI4 (x))
|
||||
|
||||
#define CSKY_IS_R4_ADJUSTER(x) \
|
||||
(CSKY_32_IS_R4_ADJUSTER (x) || CSKY_16_IS_R4_ADJUSTER (x))
|
||||
#define CSKY_IS_SUBU4(x) (CSKY_32_IS_SUBU4 (x) || CSKY_16_IS_SUBU4 (x))
|
||||
|
||||
/* mfcr rz, epsr. */
|
||||
#define CSKY_32_IS_MFCR_EPSR(insn) ((insn & 0xffffffe0) == 0xc0026020)
|
||||
/* mfcr rz, fpsr. */
|
||||
#define CSKY_32_IS_MFCR_FPSR(insn) ((insn & 0xffffffe0) == 0xc0036020)
|
||||
/* mfcr rz, epc. */
|
||||
#define CSKY_32_IS_MFCR_EPC(insn) ((insn & 0xffffffe0) == 0xc0046020)
|
||||
/* mfcr rz, fpc. */
|
||||
#define CSKY_32_IS_MFCR_FPC(insn) ((insn & 0xffffffe0) == 0xc0056020)
|
||||
|
||||
#define CSKY_32_IS_RTE(insn) (insn == 0xc0004020)
|
||||
#define CSKY_32_IS_RFI(insn) (insn == 0xc0004420)
|
||||
#define CSKY_32_IS_JMP(insn) ((insn & 0xffe0ffff) == 0xe8c00000)
|
||||
#define CSKY_16_IS_JMP(insn) ((insn & 0xffc3) == 0x7800)
|
||||
#define CSKY_32_IS_JMPI(insn) ((insn & 0xffff0000) == 0xeac00000)
|
||||
#define CSKY_32_IS_JMPIX(insn) ((insn & 0xffe0fffc) == 0xe9e00000)
|
||||
#define CSKY_16_IS_JMPIX(insn) ((insn & 0xf8fc) == 0x38e0)
|
||||
|
||||
#define CSKY_16_IS_BR(insn) ((insn & 0xfc00) == 0x0400)
|
||||
#define CSKY_32_IS_BR(insn) ((insn & 0xffff0000) == 0xe8000000)
|
||||
#define CSKY_16_IS_MOV_FP_SP(insn) (insn == 0x6e3b) /* mov r8, r14. */
|
||||
#define CSKY_32_IS_MOV_FP_SP(insn) (insn == 0xc40e4828) /* mov r8, r14. */
|
||||
#define CSKY_16_IS_MOV_SP_FP(insn) (insn == 0x6fa3) /* mov r14, r8. */
|
||||
#define CSKY_32_INSN_MASK 0xc000
|
||||
#define CSKY_BKPT_INSN 0x0
|
||||
#define CSKY_NUM_GREGS 32
|
||||
/* 32 general regs + 4. */
|
||||
#define CSKY_NUM_GREGS_SAVED_GREGS (CSKY_NUM_GREGS + 4)
|
||||
|
||||
/* CSKY software bkpt write-mode. */
|
||||
#define CSKY_WR_BKPT_MODE 4
|
||||
|
||||
/* Define insns for parse rt_sigframe. */
|
||||
/* There are three words(sig, pinfo, puc) before siginfo. */
|
||||
#define CSKY_SIGINFO_OFFSET 0xc
|
||||
|
||||
/* Size of struct siginfo. */
|
||||
#define CSKY_SIGINFO_SIZE 0x80
|
||||
|
||||
/* There are five words(uc_flags, uc_link, and three for uc_stack)
|
||||
in struct ucontext before sigcontext. */
|
||||
#define CSKY_UCONTEXT_SIGCONTEXT 0x14
|
||||
|
||||
/* There is a word(sc_mask) before sc_usp. */
|
||||
#define CSKY_SIGCONTEXT_SC_USP 0x4
|
||||
|
||||
/* There is a word(sc_usp) before sc_a0. */
|
||||
#define CSKY_SIGCONTEXT_SC_A0 0x4
|
||||
|
||||
#define CSKY_MOVI_R7_173 0x00adea07
|
||||
#define CSKY_TRAP_0 0x2020c000
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue