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2000-07-22 Jason Eckhardt <jle@cygnus.com> 

* include/opcode/i860.h (btne, bte, bla): Changed these opcodes
	to use sbroff ('r') instead of split16 ('s').
	(J, K, L, M): New operand types for 16-bit aligned fields.
	(ld.x, {p}fld.x, fst.x, pst.d): Changed these opcodes to
	use I, J, K, L, M instead of just I.
	(T, U): New operand types for split 16-bit aligned fields.
	(st.x): Changed these opcodes to use S, T, U instead of just S.
	(andh, andnoth, orh, xorh): Deleted 3-register forms as they do not
	exist on the i860.
	(pfgt.sd, pfle.sd): Deleted these as they do not exist on the i860.
	(pfeq.ss, pfeq.dd): New opcodes.
	(st.s): Fixed incorrect mask bits.
	(fmlow): Fixed incorrect mask bits.
	(fzchkl, pfzchkl): Fixed incorrect mask bits.
	(faddz, pfaddz): Fixed incorrect mask bits.
	(form, pform): Fixed incorrect mask bits.
	(pfld.l): Fixed incorrect mask bits.
	(fst.q): Fixed incorrect mask bits.
	(all floating point opcodes): Fixed incorrect mask bits for
	handling of dual bit.

	* include/elf/i860.h: New file.
	(elf_i860_reloc_type): Defined ELF32 i860 relocations.

	* bfd/cpu-i860.c: Added comments.

	* bfd/elf32-i860.c (TARGET_LITTLE_SYM): Defined to
	bfd_elf32_i860_little_vec.
	(TARGET_LITTLE_NAME): Defined to "elf32-i860-little".
	(ELF_MAXPAGESIZE): Changed to 4096.

	* bfd/targets.c (bfd_elf32_i860_little_vec): Declaration of
	new target.
	(bfd_target_vector): Added bfd_elf32_i860_little_vec.

	* bfd/config.bfd (i860-stardent-sysv4*, i860-stardent-elf*): Added
	config for little endian elf32 i860.
	(targ_defvec): Define for the new config above
	as "bfd_elf32_i860_little_vec".
	(targ_selvecs): Define for the new config above
	as "bfd_elf32_i860_vec bfd_elf32_i860_little_vec"

	* bfd/configure.in (bfd_elf32_i860_little_vec): Added recognition
	of new target vec.

	* bfd/configure: Regenerated.

	* opcodes/i860-dis.c: New file.
	(print_insn_i860): New function.
	(print_br_address): New function.
	(sign_extend): New function.
	(BITWISE_OP): New macro.
	(I860_REG_PREFIX): New macro.
	(grnames, frnames, crnames): New structures.

	* opcodes/disassemble.c (ARCH_i860): Define.
	(disassembler): Add check for bfd_arch_i860 to set disassemble
	function to print_insn_i860.

	* include/dis-asm.h (print_insn_i860): Add prototype.

	* opcodes/Makefile.in (CFILES): Added i860-dis.c.
	(ALL_MACHINES): Added i860-dis.lo.
	(i860-dis.lo): New dependences.

	* opcodes/configure.in: New bits for bfd_i860_arch.

	* opcodes/configure: Regenerated.
This commit is contained in:
Jason Eckhardt 2000-07-28 21:10:20 +00:00
parent b22a602753
commit 9d75133528
14 changed files with 1084 additions and 723 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
bfd/config.bfd
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@ -389,6 +389,10 @@ case "${targ}" in
i860-*-mach3* | i860-*-osf1* | i860-*-coff*)
targ_defvec=i860coff_vec
;;
i860-stardent-sysv4* | i860-stardent-elf*)
targ_defvec=bfd_elf32_i860_little_vec
targ_selvecs="bfd_elf32_i860_vec bfd_elf32_i860_little_vec"
;;
i860-*-sysv4* | i860-*-elf*)
targ_defvec=bfd_elf32_i860_vec
;;

472
bfd/configure vendored
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File diff suppressed because it is too large Load Diff

1
bfd/configure.in
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@ -496,6 +496,7 @@ do
bfd_elf32_i370_vec) tb="$tb elf32-i370.lo elf32.lo $elf" ;;
bfd_elf32_i386_vec) tb="$tb elf32-i386.lo elf32.lo $elf" ;;
bfd_elf32_i860_vec) tb="$tb elf32-i860.lo elf32.lo $elf" ;;
bfd_elf32_i860_little_vec) tb="$tb elf32-i860.lo elf32.lo $elf" ;;
bfd_elf32_i960_vec) tb="$tb elf32-i960.lo elf32.lo $elf" ;;
bfd_elf32_little_generic_vec) tb="$tb elf32-gen.lo elf32.lo $elf" ;;
bfd_elf32_littlemips_vec) tb="$tb elf32-mips.lo elf32.lo $elf ecofflink.lo" ;;

26
bfd/cpu-i860.c
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@ -1,5 +1,5 @@
/* BFD support for the Intel 860 architecture.
Copyright 1992, 1995 Free Software Foundation, Inc.
Copyright 1992, 1995, 2000 Free Software Foundation, Inc.
Created mostly by substituting "860" for "386" in cpu-i386.c
Harry Dolan <dolan@ssd.intel.com>, October 1995
@ -25,16 +25,16 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
const bfd_arch_info_type bfd_i860_arch =
{
32, /* 32 bits in a word */
32, /* 32 bits in an address */
8, /* 8 bits in a byte */
bfd_arch_i860,
0, /* only 1 machine */
"i860",
"i860",
3,
true, /* the one and only */
bfd_default_compatible,
bfd_default_scan ,
0,
32, /* 32 bits in a word */
32, /* 32 bits in an address */
8, /* 8 bits in a byte */
bfd_arch_i860, /* Architecture */
0, /* Only one machine */
"i860", /* Architecture name */
"i860", /* Printable name */
3, /* Section alignment exponent */
true, /* Is this the default architecture? */
bfd_default_compatible,
bfd_default_scan,
0, /* Next in list */
};

12
bfd/elf32-i860.c
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@ -1,5 +1,7 @@
/* Intel 860 specific support for 32-bit ELF
Copyright 1993 Free Software Foundation, Inc.
Copyright 1993, 2000 Free Software Foundation, Inc.
Full i860 support added by Jason Eckhardt <jle@cygnus.com>.
This file is part of BFD, the Binary File Descriptor library.
@ -25,10 +27,12 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#define bfd_elf32_bfd_reloc_type_lookup bfd_default_reloc_type_lookup
#define elf_info_to_howto _bfd_elf_no_info_to_howto
#define TARGET_BIG_SYM bfd_elf32_i860_vec
#define TARGET_BIG_NAME "elf32-i860"
#define TARGET_BIG_SYM bfd_elf32_i860_vec
#define TARGET_BIG_NAME "elf32-i860"
#define TARGET_LITTLE_SYM bfd_elf32_i860_little_vec
#define TARGET_LITTLE_NAME "elf32-i860-little"
#define ELF_ARCH bfd_arch_i860
#define ELF_MACHINE_CODE EM_860
#define ELF_MAXPAGESIZE 1 /* FIXME: This number is wrong, It should be the page size in bytes. */
#define ELF_MAXPAGESIZE 4096 /* Page size in bytes. */
#include "elf32-target.h"

2
bfd/targets.c
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@ -529,6 +529,7 @@ extern const bfd_target bfd_elf32_hppa_vec;
extern const bfd_target bfd_elf32_i370_vec;
extern const bfd_target bfd_elf32_i386_vec;
extern const bfd_target bfd_elf32_i860_vec;
extern const bfd_target bfd_elf32_i860_little_vec;
extern const bfd_target bfd_elf32_i960_vec;
extern const bfd_target bfd_elf32_little_generic_vec;
extern const bfd_target bfd_elf32_littlemips_vec;
@ -733,6 +734,7 @@ const bfd_target * const bfd_target_vector[] = {
&bfd_elf32_i370_vec,
&bfd_elf32_i386_vec,
&bfd_elf32_i860_vec,
&bfd_elf32_i860_little_vec,
&bfd_elf32_i960_vec,
&bfd_elf32_little_generic_vec,
&bfd_elf32_littlearc_vec,

1
include/dis-asm.h
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@ -175,6 +175,7 @@ extern int print_insn_little_arm PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_sparc PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_big_a29k PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_little_a29k PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_i860 PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_i960 PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_sh PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_shl PARAMS ((bfd_vma, disassemble_info*));

66
include/elf/i860.h Normal file
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@ -0,0 +1,66 @@
/* i860 ELF support for BFD.
Copyright (C) 2000 Free Software Foundation, Inc.
Contributed by Jason Eckhardt <jle@cygnus.com>.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation,
Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#ifndef _ELF_I860_H
#define _ELF_I860_H
/* Note: i860 ELF is defined to use only RELA relocations. */
#include "elf/reloc-macros.h"
START_RELOC_NUMBERS (elf_i860_reloc_type)
RELOC_NUMBER (R_860_NONE, 0x00) /* No reloc */
RELOC_NUMBER (R_860_32, 0x01) /* S+A */
RELOC_NUMBER (R_860_COPY, 0x02) /* No calculation */
RELOC_NUMBER (R_860_GLOB_DAT, 0x03) /* S, Create GOT entry */
RELOC_NUMBER (R_860_JUMP_SLOT, 0x04) /* S+A, Create PLT entry */
RELOC_NUMBER (R_860_RELATIVE, 0x05) /* B+A, Adj by program base */
RELOC_NUMBER (R_860_PC26, 0x30) /* (S+A-P) >> 2 */
RELOC_NUMBER (R_860_PLT26, 0x31) /* (L+A-P) >> 2 */
RELOC_NUMBER (R_860_PC16, 0x32) /* (S+A-P) >> 2 */
RELOC_NUMBER (R_860_LOW0, 0x40) /* S+A */
RELOC_NUMBER (R_860_SPLIT0, 0x42) /* S+A */
RELOC_NUMBER (R_860_LOW1, 0x44) /* S+A */
RELOC_NUMBER (R_860_SPLIT1, 0x46) /* S+A */
RELOC_NUMBER (R_860_LOW2, 0x48) /* S+A */
RELOC_NUMBER (R_860_SPLIT2, 0x4A) /* S+A */
RELOC_NUMBER (R_860_LOW3, 0x4C) /* S+A */
RELOC_NUMBER (R_860_LOGOT0, 0x50) /* G */
RELOC_NUMBER (R_860_SPGOT0, 0x52) /* G */
RELOC_NUMBER (R_860_LOGOT1, 0x54) /* G */
RELOC_NUMBER (R_860_SPGOT1, 0x56) /* G */
RELOC_NUMBER (R_860_LOGOTOFF0, 0x60) /* O */
RELOC_NUMBER (R_860_SPGOTOFF0, 0x62) /* O */
RELOC_NUMBER (R_860_LOGOTOFF1, 0x64) /* O */
RELOC_NUMBER (R_860_SPGOTOFF1, 0x66) /* O */
RELOC_NUMBER (R_860_LOGOTOFF2, 0x68) /* O */
RELOC_NUMBER (R_860_LOGOTOFF3, 0x6C) /* O */
RELOC_NUMBER (R_860_LOPC, 0x70) /* (S+A-P) >> 2 */
RELOC_NUMBER (R_860_HIGHADJ, 0x80) /* hiadj(S+A) */
RELOC_NUMBER (R_860_HAGOT, 0x90) /* hiadj(G) */
RELOC_NUMBER (R_860_HAGOTOFF, 0xA0) /* hiadj(O) */
RELOC_NUMBER (R_860_HAPC, 0xB0) /* hiadj((S+A-P) >> 2) */
RELOC_NUMBER (R_860_HIGH, 0xC0) /* (S+A) >> 16 */
RELOC_NUMBER (R_860_HIGOT, 0xD0) /* G >> 16 */
RELOC_NUMBER (R_860_HIGOTOFF, 0xE0) /* O */
END_RELOC_NUMBERS (R_860_max)
#endif

602
include/opcode/i860.h
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@ -1,5 +1,5 @@
/* Table of opcodes for the i860.
Copyright (C) 1989 Free Software Foundation, Inc.
Copyright (C) 1989, 2000 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.
@ -69,12 +69,18 @@ Kinds of operands:
d dest register.
c ctrlreg control register.
i 16 bit immediate.
I 16 bit immediate, aligned.
I 16 bit immediate, aligned 2^0. (ld.b)
J 16 bit immediate, aligned 2^1. (ld.s)
K 16 bit immediate, aligned 2^2. (ld.l, {p}fld.l, fst.l)
L 16 bit immediate, aligned 2^3. ({p}fld.d, fst.d)
M 16 bit immediate, aligned 2^4. ({p}fld.q, fst.q)
5 5 bit immediate.
l lbroff 26 bit PC relative immediate.
r sbroff 16 bit PC relative immediate.
s split 16 bit immediate.
S split 16 bit immediate, aligned.
S split 16 bit immediate, aligned 2^0. (st.b)
T split 16 bit immediate, aligned 2^1. (st.s)
U split 16 bit immediate, aligned 2^2. (st.l)
e src1 floating point register.
f src2 floating point register.
g dest floating point register.
@ -96,50 +102,54 @@ static struct i860_opcode i860_opcodes[] =
{ "ld.b", 0x00000000, 0xfc000000, "1(2),d", 0 }, /* ld.b isrc1(isrc2),idest */
{ "ld.b", 0x04000000, 0xf8000000, "I(2),d", E_ADDR }, /* ld.b #const(isrc2),idest */
{ "ld.s", 0x10000000, 0xec000001, "1(2),d", 0 }, /* ld.s isrc1(isrc2),idest */
{ "ld.s", 0x14000001, 0xe8000000, "I(2),d", E_ADDR }, /* ld.s #const(isrc2),idest */
{ "ld.s", 0x14000000, 0xe8000001, "J(2),d", E_ADDR }, /* ld.s #const(isrc2),idest */
{ "ld.l", 0x10000001, 0xec000000, "1(2),d", 0 }, /* ld.l isrc1(isrc2),idest */
{ "ld.l", 0x14000001, 0xe8000000, "I(2),d", E_ADDR }, /* ld.l #const(isrc2),idest */
{ "ld.l", 0x14000001, 0xe8000000, "K(2),d", E_ADDR }, /* ld.l #const(isrc2),idest */
{ "st.c", 0x38000000, 0xc4000000, "1,c", 0 }, /* st.c isrc1ni,csrc2 */
{ "st.b", 0x0c000000, 0xf0000000, "1,S(2)", E_ADDR }, /* st.b isrc1ni,#const(isrc2) */
{ "st.s", 0x1c000000, 0xe0000000, "1,S(2)", E_ADDR }, /* st.s isrc1ni,#const(isrc2) */
{ "st.l", 0x1c000001, 0xe0000000, "1,S(2)", E_ADDR }, /* st.l isrc1ni,#const(isrc2) */
{ "st.s", 0x1c000000, 0xe0000001, "1,T(2)", E_ADDR }, /* st.s isrc1ni,#const(isrc2) */
{ "st.l", 0x1c000001, 0xe0000000, "1,U(2)", E_ADDR }, /* st.l isrc1ni,#const(isrc2) */
{ "ixfr", 0x08000000, 0xf4000000, "1,g", 0 }, /* ixfr isrc1ni,fdest */
{ "fld.l", 0x20000002, 0xdc000001, "1(2),g", 0 }, /* fld.l isrc1(isrc2),fdest */
{ "fld.l", 0x24000002, 0xd8000001, "i(2),g", E_ADDR }, /* fld.l #const(isrc2),fdest */
{ "fld.l", 0x24000002, 0xd8000001, "K(2),g", E_ADDR }, /* fld.l #const(isrc2),fdest */
{ "fld.l", 0x20000003, 0xdc000000, "1(2)++,g", 0 }, /* fld.l isrc1(isrc2)++,fdest */
{ "fld.l", 0x24000003, 0xd8000000, "i(2)++,g", E_ADDR }, /* fld.l #const(isrc2)++,fdest */
{ "fld.l", 0x24000003, 0xd8000000, "K(2)++,g", E_ADDR }, /* fld.l #const(isrc2)++,fdest */
{ "fld.d", 0x20000000, 0xdc000007, "1(2),g", 0 }, /* fld.d isrc1(isrc2),fdest */
{ "fld.d", 0x24000000, 0xd8000007, "i(2),g", E_ADDR }, /* fld.d #const(isrc2),fdest */
{ "fld.d", 0x24000000, 0xd8000007, "L(2),g", E_ADDR }, /* fld.d #const(isrc2),fdest */
{ "fld.d", 0x20000001, 0xdc000006, "1(2)++,g", 0 }, /* fld.d isrc1(isrc2)++,fdest */
{ "fld.d", 0x24000001, 0xd8000006, "i(2)++,g", E_ADDR }, /* fld.d #const(isrc2)++,fdest */
{ "fld.d", 0x24000001, 0xd8000006, "L(2)++,g", E_ADDR }, /* fld.d #const(isrc2)++,fdest */
{ "fld.q", 0x20000004, 0xdc000003, "1(2),g", 0 }, /* fld.q isrc1(isrc2),fdest */
{ "fld.q", 0x24000004, 0xd8000003, "i(2),g", E_ADDR }, /* fld.q #const(isrc2),fdest */
{ "fld.q", 0x24000004, 0xd8000003, "M(2),g", E_ADDR }, /* fld.q #const(isrc2),fdest */
{ "fld.q", 0x20000005, 0xdc000002, "1(2)++,g", 0 }, /* fld.q isrc1(isrc2)++,fdest */
{ "fld.q", 0x24000005, 0xd8000002, "i(2)++,g", E_ADDR }, /* fld.q #const(isrc2)++,fdest */
{ "fld.q", 0x24000005, 0xd8000002, "M(2)++,g", E_ADDR }, /* fld.q #const(isrc2)++,fdest */
{ "pfld.l", 0x60000000, 0x9c000003, "1(2),g", 0 }, /* pfld.l isrc1(isrc2),fdest */
{ "pfld.l", 0x64000000, 0x98000003, "i(2),g", E_ADDR }, /* pfld.l #const(isrc2),fdest */
{ "pfld.l", 0x60000001, 0x9c000002, "1(2)++,g", 0 }, /* pfld.l isrc1(isrc2)++,fdest */
{ "pfld.l", 0x64000001, 0x98000002, "i(2)++,g", E_ADDR }, /* pfld.l #const(isrc2)++,fdest */
{ "pfld.l", 0x60000002, 0x9c000001, "1(2),g", 0 }, /* pfld.l isrc1(isrc2),fdest */
{ "pfld.l", 0x64000002, 0x98000001, "K(2),g", E_ADDR }, /* pfld.l #const(isrc2),fdest */
{ "pfld.l", 0x60000003, 0x9c000000, "1(2)++,g", 0 }, /* pfld.l isrc1(isrc2)++,fdest */
{ "pfld.l", 0x64000003, 0x98000000, "K(2)++,g", E_ADDR }, /* pfld.l #const(isrc2)++,fdest */
{ "pfld.d", 0x60000000, 0x9c000007, "1(2),g", 0 }, /* pfld.d isrc1(isrc2),fdest */
{ "pfld.d", 0x64000000, 0x98000007, "i(2),g", E_ADDR }, /* pfld.d #const(isrc2),fdest */
{ "pfld.d", 0x64000000, 0x98000007, "L(2),g", E_ADDR }, /* pfld.d #const(isrc2),fdest */
{ "pfld.d", 0x60000001, 0x9c000006, "1(2)++,g", 0 }, /* pfld.d isrc1(isrc2)++,fdest */
{ "pfld.d", 0x64000001, 0x98000006, "i(2)++,g", E_ADDR }, /* pfld.d #const(isrc2)++,fdest */
{ "pfld.d", 0x64000001, 0x98000006, "L(2)++,g", E_ADDR }, /* pfld.d #const(isrc2)++,fdest */
{ "fst.l", 0x28000002, 0xd4000001, "g,1(2)", 0 }, /* fst.l fdest,isrc1(isrc2) */
{ "fst.l", 0x2c000002, 0xd0000001, "g,i(2)", E_ADDR }, /* fst.l fdest,#const(isrc2) */
{ "fst.l", 0x2c000002, 0xd0000001, "g,K(2)", E_ADDR }, /* fst.l fdest,#const(isrc2) */
{ "fst.l", 0x28000003, 0xd4000000, "g,1(2)++", 0 }, /* fst.l fdest,isrc1(isrc2)++ */
{ "fst.l", 0x2c000003, 0xd0000000, "g,i(2)++", E_ADDR }, /* fst.l fdest,#const(isrc2)++ */
{ "fst.l", 0x2c000003, 0xd0000000, "g,K(2)++", E_ADDR }, /* fst.l fdest,#const(isrc2)++ */
{ "fst.d", 0x28000000, 0xd4000007, "g,1(2)", 0 }, /* fst.d fdest,isrc1(isrc2) */
{ "fst.d", 0x2c000000, 0xd0000007, "g,i(2)", E_ADDR }, /* fst.d fdest,#const(isrc2) */
{ "fst.d", 0x2c000000, 0xd0000007, "g,L(2)", E_ADDR }, /* fst.d fdest,#const(isrc2) */
{ "fst.d", 0x28000001, 0xd4000006, "g,1(2)++", 0 }, /* fst.d fdest,isrc1(isrc2)++ */
{ "fst.d", 0x2c000001, 0xd0000006, "g,i(2)++", E_ADDR }, /* fst.d fdest,#const(isrc2)++ */
{ "fst.d", 0x2c000001, 0xd0000006, "g,L(2)++", E_ADDR }, /* fst.d fdest,#const(isrc2)++ */
{ "fst.q", 0x28000004, 0xd4000003, "g,1(2)", 0 }, /* fst.d fdest,isrc1(isrc2) */
{ "fst.q", 0x2c000004, 0xd0000003, "g,M(2)", E_ADDR }, /* fst.d fdest,#const(isrc2) */
{ "fst.q", 0x28000005, 0xd4000002, "g,1(2)++", 0 }, /* fst.d fdest,isrc1(isrc2)++ */
{ "fst.q", 0x2c000005, 0xd0000002, "g,M(2)++", E_ADDR }, /* fst.d fdest,#const(isrc2)++ */
{ "pst.d", 0x3c000000, 0xc0000007, "g,i(2)", E_ADDR }, /* pst.d fdest,#const(isrc2) */
{ "pst.d", 0x3c000001, 0xc0000006, "g,i(2)++", E_ADDR }, /* pst.d fdest,#const(isrc2)++ */
{ "pst.d", 0x3c000000, 0xc0000007, "g,L(2)", E_ADDR }, /* pst.d fdest,#const(isrc2) */
{ "pst.d", 0x3c000001, 0xc0000006, "g,L(2)++", E_ADDR }, /* pst.d fdest,#const(isrc2)++ */
{ "addu", 0x80000000, 0x7c000000, "1,2,d", 0 }, /* addu isrc1,isrc2,idest */
{ "addu", 0x84000000, 0x78000000, "i,2,d", E_S32 }, /* addu #const,isrc2,idest */
@ -170,26 +180,22 @@ static struct i860_opcode i860_opcodes[] =
{ "and", 0xc0000000, 0x3c000000, "1,2,d", 0 }, /* and isrc1,isrc2,idest */
{ "and", 0xc4000000, 0x38000000, "i,2,d", E_AND }, /* and #const,isrc2,idest */
{ "andh", 0xc8000000, 0x34000000, "1,2,d", 0 }, /* andh isrc1,isrc2,idest */
{ "andh", 0xcc000000, 0x30000000, "i,2,d", 0 }, /* andh #const,isrc2,idest */
{ "andnot", 0xd0000000, 0x2c000000, "1,2,d", 0 }, /* andnot isrc1,isrc2,idest */
{ "andnot", 0xd4000000, 0x28000000, "i,2,d", E_U32 }, /* andnot #const,isrc2,idest */
{ "andnoth", 0xd8000000, 0x24000000, "1,2,d", 0 }, /* andnoth isrc1,isrc2,idest */
{ "andnoth", 0xdc000000, 0x20000000, "i,2,d", 0 }, /* andnoth #const,isrc2,idest */
{ "or", 0xe0000000, 0x1c000000, "1,2,d", 0 }, /* or isrc1,isrc2,idest */
{ "or", 0xe4000000, 0x18000000, "i,2,d", E_U32 }, /* or #const,isrc2,idest */
{ "orh", 0xe8000000, 0x14000000, "1,2,d", 0 }, /* orh isrc1,isrc2,idest */
{ "orh", 0xec000000, 0x10000000, "i,2,d", 0 }, /* orh #const,isrc2,idest */
{ "xor", 0xf0000000, 0x0c000000, "1,2,d", 0 }, /* xor isrc1,isrc2,idest */
{ "xor", 0xf4000000, 0x08000000, "i,2,d", E_U32 }, /* xor #const,isrc2,idest */
{ "xorh", 0xf8000000, 0x04000000, "1,2,d", 0 }, /* xorh isrc1,isrc2,idest */
{ "xorh", 0xfc000000, 0x00000000, "i,2,d", 0 }, /* xorh #const,isrc2,idest */
{ "bte", 0x58000000, 0xa4000000, "1,2,s", 0 }, /* bte isrc1s,isrc2,sbroff */
{ "bte", 0x5c000000, 0xa0000000, "5,2,s", 0 }, /* bte #const5,isrc2,sbroff */
{ "btne", 0x50000000, 0xac000000, "1,2,s", 0 }, /* btne isrc1s,isrc2,sbroff */
{ "btne", 0x54000000, 0xa8000000, "5,2,s", 0 }, /* btne #const5,isrc2,sbroff */
{ "bla", 0xb4000000, 0x48000000, "1,2,s", E_DELAY }, /* bla isrc1s,isrc2,sbroff */
{ "bte", 0x58000000, 0xa4000000, "1,2,r", 0 }, /* bte isrc1s,isrc2,sbroff */
{ "bte", 0x5c000000, 0xa0000000, "5,2,r", 0 }, /* bte #const5,isrc2,sbroff */
{ "btne", 0x50000000, 0xac000000, "1,2,r", 0 }, /* btne isrc1s,isrc2,sbroff */
{ "btne", 0x54000000, 0xa8000000, "5,2,r", 0 }, /* btne #const5,isrc2,sbroff */
{ "bla", 0xb4000000, 0x48000000, "1,2,r", E_DELAY }, /* bla isrc1s,isrc2,sbroff */
{ "bri", 0x40000000, 0xbc000000, "1", E_DELAY }, /* bri isrc1ni */
/* Core Escape Instruction Format */
@ -207,282 +213,282 @@ static struct i860_opcode i860_opcodes[] =
{ "bnc.t", 0x7c000000, 0x80000000, "l", E_DELAY }, /* bnc.t lbroff */
/* Floating Point Escape Instruction Format - pfam.p fsrc1,fsrc2,fdest */
{ "r2p1.ss", 0x48000400, 0xb40003ff, "e,f,g", 0 },
{ "r2p1.sd", 0x48000480, 0xb400037f, "e,f,g", 0 },
{ "r2p1.dd", 0x48000580, 0xb400027f, "e,f,g", 0 },
{ "r2pt.ss", 0x48000401, 0xb40003fe, "e,f,g", 0 },
{ "r2pt.sd", 0x48000481, 0xb400037e, "e,f,g", 0 },
{ "r2pt.dd", 0x48000581, 0xb400027e, "e,f,g", 0 },
{ "r2ap1.ss", 0x48000402, 0xb40003fd, "e,f,g", 0 },
{ "r2ap1.sd", 0x48000482, 0xb400037d, "e,f,g", 0 },
{ "r2ap1.dd", 0x48000582, 0xb400027d, "e,f,g", 0 },
{ "r2apt.ss", 0x48000403, 0xb40003fc, "e,f,g", 0 },
{ "r2apt.sd", 0x48000483, 0xb400037c, "e,f,g", 0 },
{ "r2apt.dd", 0x48000583, 0xb400027c, "e,f,g", 0 },
{ "i2p1.ss", 0x48000404, 0xb40003fb, "e,f,g", 0 },
{ "i2p1.sd", 0x48000484, 0xb400037b, "e,f,g", 0 },
{ "i2p1.dd", 0x48000584, 0xb400027b, "e,f,g", 0 },
{ "i2pt.ss", 0x48000405, 0xb40003fa, "e,f,g", 0 },
{ "i2pt.sd", 0x48000485, 0xb400037a, "e,f,g", 0 },
{ "i2pt.dd", 0x48000585, 0xb400027a, "e,f,g", 0 },
{ "i2ap1.ss", 0x48000406, 0xb40003f9, "e,f,g", 0 },
{ "i2ap1.sd", 0x48000486, 0xb4000379, "e,f,g", 0 },
{ "i2ap1.dd", 0x48000586, 0xb4000279, "e,f,g", 0 },
{ "i2apt.ss", 0x48000407, 0xb40003f8, "e,f,g", 0 },
{ "i2apt.sd", 0x48000487, 0xb4000378, "e,f,g", 0 },
{ "i2apt.dd", 0x48000587, 0xb4000278, "e,f,g", 0 },
{ "rat1p2.ss", 0x48000408, 0xb40003f7, "e,f,g", 0 },
{ "rat1p2.sd", 0x48000488, 0xb4000377, "e,f,g", 0 },
{ "rat1p2.dd", 0x48000588, 0xb4000277, "e,f,g", 0 },
{ "m12apm.ss", 0x48000409, 0xb40003f6, "e,f,g", 0 },
{ "m12apm.sd", 0x48000489, 0xb4000376, "e,f,g", 0 },
{ "m12apm.dd", 0x48000589, 0xb4000276, "e,f,g", 0 },
{ "ra1p2.ss", 0x4800040a, 0xb40003f5, "e,f,g", 0 },
{ "ra1p2.sd", 0x4800048a, 0xb4000375, "e,f,g", 0 },
{ "ra1p2.dd", 0x4800058a, 0xb4000275, "e,f,g", 0 },
{ "m12ttpa.ss", 0x4800040b, 0xb40003f4, "e,f,g", 0 },
{ "m12ttpa.sd", 0x4800048b, 0xb4000374, "e,f,g", 0 },
{ "m12ttpa.dd", 0x4800058b, 0xb4000274, "e,f,g", 0 },
{ "iat1p2.ss", 0x4800040c, 0xb40003f3, "e,f,g", 0 },
{ "iat1p2.sd", 0x4800048c, 0xb4000373, "e,f,g", 0 },
{ "iat1p2.dd", 0x4800058c, 0xb4000273, "e,f,g", 0 },
{ "m12tpm.ss", 0x4800040d, 0xb40003f2, "e,f,g", 0 },
{ "m12tpm.sd", 0x4800048d, 0xb4000372, "e,f,g", 0 },
{ "m12tpm.dd", 0x4800058d, 0xb4000272, "e,f,g", 0 },
{ "ia1p2.ss", 0x4800040e, 0xb40003f1, "e,f,g", 0 },
{ "ia1p2.sd", 0x4800048e, 0xb4000371, "e,f,g", 0 },
{ "ia1p2.dd", 0x4800058e, 0xb4000271, "e,f,g", 0 },
{ "m12tpa.ss", 0x4800040f, 0xb40003f0, "e,f,g", 0 },
{ "m12tpa.sd", 0x4800048f, 0xb4000370, "e,f,g", 0 },
{ "m12tpa.dd", 0x4800058f, 0xb4000270, "e,f,g", 0 },
{ "r2p1.ss", 0x48000400, 0xb40001ff, "e,f,g", 0 },
{ "r2p1.sd", 0x48000480, 0xb400017f, "e,f,g", 0 },
{ "r2p1.dd", 0x48000580, 0xb400007f, "e,f,g", 0 },
{ "r2pt.ss", 0x48000401, 0xb40001fe, "e,f,g", 0 },
{ "r2pt.sd", 0x48000481, 0xb400017e, "e,f,g", 0 },
{ "r2pt.dd", 0x48000581, 0xb400007e, "e,f,g", 0 },
{ "r2ap1.ss", 0x48000402, 0xb40001fd, "e,f,g", 0 },
{ "r2ap1.sd", 0x48000482, 0xb400017d, "e,f,g", 0 },
{ "r2ap1.dd", 0x48000582, 0xb400007d, "e,f,g", 0 },
{ "r2apt.ss", 0x48000403, 0xb40001fc, "e,f,g", 0 },
{ "r2apt.sd", 0x48000483, 0xb400017c, "e,f,g", 0 },
{ "r2apt.dd", 0x48000583, 0xb400007c, "e,f,g", 0 },
{ "i2p1.ss", 0x48000404, 0xb40001fb, "e,f,g", 0 },
{ "i2p1.sd", 0x48000484, 0xb400017b, "e,f,g", 0 },
{ "i2p1.dd", 0x48000584, 0xb400007b, "e,f,g", 0 },
{ "i2pt.ss", 0x48000405, 0xb40001fa, "e,f,g", 0 },
{ "i2pt.sd", 0x48000485, 0xb400017a, "e,f,g", 0 },
{ "i2pt.dd", 0x48000585, 0xb400007a, "e,f,g", 0 },
{ "i2ap1.ss", 0x48000406, 0xb40001f9, "e,f,g", 0 },
{ "i2ap1.sd", 0x48000486, 0xb4000179, "e,f,g", 0 },
{ "i2ap1.dd", 0x48000586, 0xb4000079, "e,f,g", 0 },
{ "i2apt.ss", 0x48000407, 0xb40001f8, "e,f,g", 0 },
{ "i2apt.sd", 0x48000487, 0xb4000178, "e,f,g", 0 },
{ "i2apt.dd", 0x48000587, 0xb4000078, "e,f,g", 0 },
{ "rat1p2.ss", 0x48000408, 0xb40001f7, "e,f,g", 0 },
{ "rat1p2.sd", 0x48000488, 0xb4000177, "e,f,g", 0 },
{ "rat1p2.dd", 0x48000588, 0xb4000077, "e,f,g", 0 },
{ "m12apm.ss", 0x48000409, 0xb40001f6, "e,f,g", 0 },
{ "m12apm.sd", 0x48000489, 0xb4000176, "e,f,g", 0 },
{ "m12apm.dd", 0x48000589, 0xb4000076, "e,f,g", 0 },
{ "ra1p2.ss", 0x4800040a, 0xb40001f5, "e,f,g", 0 },
{ "ra1p2.sd", 0x4800048a, 0xb4000175, "e,f,g", 0 },
{ "ra1p2.dd", 0x4800058a, 0xb4000075, "e,f,g", 0 },
{ "m12ttpa.ss", 0x4800040b, 0xb40001f4, "e,f,g", 0 },
{ "m12ttpa.sd", 0x4800048b, 0xb4000174, "e,f,g", 0 },
{ "m12ttpa.dd", 0x4800058b, 0xb4000074, "e,f,g", 0 },
{ "iat1p2.ss", 0x4800040c, 0xb40001f3, "e,f,g", 0 },
{ "iat1p2.sd", 0x4800048c, 0xb4000173, "e,f,g", 0 },
{ "iat1p2.dd", 0x4800058c, 0xb4000073, "e,f,g", 0 },
{ "m12tpm.ss", 0x4800040d, 0xb40001f2, "e,f,g", 0 },
{ "m12tpm.sd", 0x4800048d, 0xb4000172, "e,f,g", 0 },
{ "m12tpm.dd", 0x4800058d, 0xb4000072, "e,f,g", 0 },
{ "ia1p2.ss", 0x4800040e, 0xb40001f1, "e,f,g", 0 },
{ "ia1p2.sd", 0x4800048e, 0xb4000171, "e,f,g", 0 },
{ "ia1p2.dd", 0x4800058e, 0xb4000071, "e,f,g", 0 },
{ "m12tpa.ss", 0x4800040f, 0xb40001f0, "e,f,g", 0 },
{ "m12tpa.sd", 0x4800048f, 0xb4000170, "e,f,g", 0 },
{ "m12tpa.dd", 0x4800058f, 0xb4000070, "e,f,g", 0 },
/* Floating Point Escape Instruction Format - pfsm.p fsrc1,fsrc2,fdest */
{ "r2s1.ss", 0x48000410, 0xb40003ef, "e,f,g", 0 },
{ "r2s1.sd", 0x48000490, 0xb400036f, "e,f,g", 0 },
{ "r2s1.dd", 0x48000590, 0xb400026f, "e,f,g", 0 },
{ "r2st.ss", 0x48000411, 0xb40003ee, "e,f,g", 0 },
{ "r2st.sd", 0x48000491, 0xb400036e, "e,f,g", 0 },
{ "r2st.dd", 0x48000591, 0xb400026e, "e,f,g", 0 },
{ "r2as1.ss", 0x48000412, 0xb40003ed, "e,f,g", 0 },
{ "r2as1.sd", 0x48000492, 0xb400036d, "e,f,g", 0 },
{ "r2as1.dd", 0x48000592, 0xb400026d, "e,f,g", 0 },
{ "r2ast.ss", 0x48000413, 0xb40003ec, "e,f,g", 0 },
{ "r2ast.sd", 0x48000493, 0xb400036c, "e,f,g", 0 },
{ "r2ast.dd", 0x48000593, 0xb400026c, "e,f,g", 0 },
{ "i2s1.ss", 0x48000414, 0xb40003eb, "e,f,g", 0 },
{ "i2s1.sd", 0x48000494, 0xb400036b, "e,f,g", 0 },
{ "i2s1.dd", 0x48000594, 0xb400026b, "e,f,g", 0 },
{ "i2st.ss", 0x48000415, 0xb40003ea, "e,f,g", 0 },
{ "i2st.sd", 0x48000495, 0xb400036a, "e,f,g", 0 },
{ "i2st.dd", 0x48000595, 0xb400026a, "e,f,g", 0 },
{ "i2as1.ss", 0x48000416, 0xb40003e9, "e,f,g", 0 },
{ "i2as1.sd", 0x48000496, 0xb4000369, "e,f,g", 0 },
{ "i2as1.dd", 0x48000596, 0xb4000269, "e,f,g", 0 },
{ "i2ast.ss", 0x48000417, 0xb40003e8, "e,f,g", 0 },
{ "i2ast.sd", 0x48000497, 0xb4000368, "e,f,g", 0 },
{ "i2ast.dd", 0x48000597, 0xb4000268, "e,f,g", 0 },
{ "rat1s2.ss", 0x48000418, 0xb40003e7, "e,f,g", 0 },
{ "rat1s2.sd", 0x48000498, 0xb4000367, "e,f,g", 0 },
{ "rat1s2.dd", 0x48000598, 0xb4000267, "e,f,g", 0 },
{ "m12asm.ss", 0x48000419, 0xb40003e6, "e,f,g", 0 },
{ "m12asm.sd", 0x48000499, 0xb4000366, "e,f,g", 0 },
{ "m12asm.dd", 0x48000599, 0xb4000266, "e,f,g", 0 },
{ "ra1s2.ss", 0x4800041a, 0xb40003e5, "e,f,g", 0 },
{ "ra1s2.sd", 0x4800049a, 0xb4000365, "e,f,g", 0 },
{ "ra1s2.dd", 0x4800059a, 0xb4000265, "e,f,g", 0 },
{ "m12ttsa.ss", 0x4800041b, 0xb40003e4, "e,f,g", 0 },
{ "m12ttsa.sd", 0x4800049b, 0xb4000364, "e,f,g", 0 },
{ "m12ttsa.dd", 0x4800059b, 0xb4000264, "e,f,g", 0 },
{ "iat1s2.ss", 0x4800041c, 0xb40003e3, "e,f,g", 0 },
{ "iat1s2.sd", 0x4800049c, 0xb4000363, "e,f,g", 0 },
{ "iat1s2.dd", 0x4800059c, 0xb4000263, "e,f,g", 0 },
{ "m12tsm.ss", 0x4800041d, 0xb40003e2, "e,f,g", 0 },
{ "m12tsm.sd", 0x4800049d, 0xb4000362, "e,f,g", 0 },
{ "m12tsm.dd", 0x4800059d, 0xb4000262, "e,f,g", 0 },
{ "ia1s2.ss", 0x4800041e, 0xb40003e1, "e,f,g", 0 },
{ "ia1s2.sd", 0x4800049e, 0xb4000361, "e,f,g", 0 },
{ "ia1s2.dd", 0x4800059e, 0xb4000261, "e,f,g", 0 },
{ "m12tsa.ss", 0x4800041f, 0xb40003e0, "e,f,g", 0 },
{ "m12tsa.sd", 0x4800049f, 0xb4000360, "e,f,g", 0 },
{ "m12tsa.dd", 0x4800059f, 0xb4000260, "e,f,g", 0 },
{ "r2s1.ss", 0x48000410, 0xb40001ef, "e,f,g", 0 },
{ "r2s1.sd", 0x48000490, 0xb400016f, "e,f,g", 0 },
{ "r2s1.dd", 0x48000590, 0xb400006f, "e,f,g", 0 },
{ "r2st.ss", 0x48000411, 0xb40001ee, "e,f,g", 0 },
{ "r2st.sd", 0x48000491, 0xb400016e, "e,f,g", 0 },
{ "r2st.dd", 0x48000591, 0xb400006e, "e,f,g", 0 },
{ "r2as1.ss", 0x48000412, 0xb40001ed, "e,f,g", 0 },
{ "r2as1.sd", 0x48000492, 0xb400016d, "e,f,g", 0 },
{ "r2as1.dd", 0x48000592, 0xb400006d, "e,f,g", 0 },
{ "r2ast.ss", 0x48000413, 0xb40001ec, "e,f,g", 0 },
{ "r2ast.sd", 0x48000493, 0xb400016c, "e,f,g", 0 },
{ "r2ast.dd", 0x48000593, 0xb400006c, "e,f,g", 0 },
{ "i2s1.ss", 0x48000414, 0xb40001eb, "e,f,g", 0 },
{ "i2s1.sd", 0x48000494, 0xb400016b, "e,f,g", 0 },
{ "i2s1.dd", 0x48000594, 0xb400006b, "e,f,g", 0 },
{ "i2st.ss", 0x48000415, 0xb40001ea, "e,f,g", 0 },
{ "i2st.sd", 0x48000495, 0xb400016a, "e,f,g", 0 },
{ "i2st.dd", 0x48000595, 0xb400006a, "e,f,g", 0 },
{ "i2as1.ss", 0x48000416, 0xb40001e9, "e,f,g", 0 },
{ "i2as1.sd", 0x48000496, 0xb4000169, "e,f,g", 0 },
{ "i2as1.dd", 0x48000596, 0xb4000069, "e,f,g", 0 },
{ "i2ast.ss", 0x48000417, 0xb40001e8, "e,f,g", 0 },
{ "i2ast.sd", 0x48000497, 0xb4000168, "e,f,g", 0 },
{ "i2ast.dd", 0x48000597, 0xb4000068, "e,f,g", 0 },
{ "rat1s2.ss", 0x48000418, 0xb40001e7, "e,f,g", 0 },
{ "rat1s2.sd", 0x48000498, 0xb4000167, "e,f,g", 0 },
{ "rat1s2.dd", 0x48000598, 0xb4000067, "e,f,g", 0 },
{ "m12asm.ss", 0x48000419, 0xb40001e6, "e,f,g", 0 },
{ "m12asm.sd", 0x48000499, 0xb4000166, "e,f,g", 0 },
{ "m12asm.dd", 0x48000599, 0xb4000066, "e,f,g", 0 },
{ "ra1s2.ss", 0x4800041a, 0xb40001e5, "e,f,g", 0 },
{ "ra1s2.sd", 0x4800049a, 0xb4000165, "e,f,g", 0 },
{ "ra1s2.dd", 0x4800059a, 0xb4000065, "e,f,g", 0 },
{ "m12ttsa.ss", 0x4800041b, 0xb40001e4, "e,f,g", 0 },
{ "m12ttsa.sd", 0x4800049b, 0xb4000164, "e,f,g", 0 },
{ "m12ttsa.dd", 0x4800059b, 0xb4000064, "e,f,g", 0 },
{ "iat1s2.ss", 0x4800041c, 0xb40001e3, "e,f,g", 0 },
{ "iat1s2.sd", 0x4800049c, 0xb4000163, "e,f,g", 0 },
{ "iat1s2.dd", 0x4800059c, 0xb4000063, "e,f,g", 0 },
{ "m12tsm.ss", 0x4800041d, 0xb40001e2, "e,f,g", 0 },
{ "m12tsm.sd", 0x4800049d, 0xb4000162, "e,f,g", 0 },
{ "m12tsm.dd", 0x4800059d, 0xb4000062, "e,f,g", 0 },
{ "ia1s2.ss", 0x4800041e, 0xb40001e1, "e,f,g", 0 },
{ "ia1s2.sd", 0x4800049e, 0xb4000161, "e,f,g", 0 },
{ "ia1s2.dd", 0x4800059e, 0xb4000061, "e,f,g", 0 },
{ "m12tsa.ss", 0x4800041f, 0xb40001e0, "e,f,g", 0 },
{ "m12tsa.sd", 0x4800049f, 0xb4000160, "e,f,g", 0 },
{ "m12tsa.dd", 0x4800059f, 0xb4000060, "e,f,g", 0 },
/* Floating Point Escape Instruction Format - pfmam.p fsrc1,fsrc2,fdest */
{ "mr2p1.ss", 0x48000000, 0xb40007ff, "e,f,g", 0 },
{ "mr2p1.sd", 0x48000080, 0xb400077f, "e,f,g", 0 },
{ "mr2p1.dd", 0x48000180, 0xb400067f, "e,f,g", 0 },
{ "mr2pt.ss", 0x48000001, 0xb40007fe, "e,f,g", 0 },
{ "mr2pt.sd", 0x48000081, 0xb400077e, "e,f,g", 0 },
{ "mr2pt.dd", 0x48000181, 0xb400067e, "e,f,g", 0 },
{ "mr2mp1.ss", 0x48000002, 0xb40007fd, "e,f,g", 0 },
{ "mr2mp1.sd", 0x48000082, 0xb400077d, "e,f,g", 0 },
{ "mr2mp1.dd", 0x48000182, 0xb400067d, "e,f,g", 0 },
{ "mr2mpt.ss", 0x48000003, 0xb40007fc, "e,f,g", 0 },
{ "mr2mpt.sd", 0x48000083, 0xb400077c, "e,f,g", 0 },
{ "mr2mpt.dd", 0x48000183, 0xb400067c, "e,f,g", 0 },
{ "mi2p1.ss", 0x48000004, 0xb40007fb, "e,f,g", 0 },
{ "mi2p1.sd", 0x48000084, 0xb400077b, "e,f,g", 0 },
{ "mi2p1.dd", 0x48000184, 0xb400067b, "e,f,g", 0 },
{ "mi2pt.ss", 0x48000005, 0xb40007fa, "e,f,g", 0 },
{ "mi2pt.sd", 0x48000085, 0xb400077a, "e,f,g", 0 },
{ "mi2pt.dd", 0x48000185, 0xb400067a, "e,f,g", 0 },
{ "mi2mp1.ss", 0x48000006, 0xb40007f9, "e,f,g", 0 },
{ "mi2mp1.sd", 0x48000086, 0xb4000779, "e,f,g", 0 },
{ "mi2mp1.dd", 0x48000186, 0xb4000679, "e,f,g", 0 },
{ "mi2mpt.ss", 0x48000007, 0xb40007f8, "e,f,g", 0 },
{ "mi2mpt.sd", 0x48000087, 0xb4000778, "e,f,g", 0 },
{ "mi2mpt.dd", 0x48000187, 0xb4000678, "e,f,g", 0 },
{ "mrmt1p2.ss", 0x48000008, 0xb40007f7, "e,f,g", 0 },
{ "mrmt1p2.sd", 0x48000088, 0xb4000777, "e,f,g", 0 },
{ "mrmt1p2.dd", 0x48000188, 0xb4000677, "e,f,g", 0 },
{ "mm12mpm.ss", 0x48000009, 0xb40007f6, "e,f,g", 0 },
{ "mm12mpm.sd", 0x48000089, 0xb4000776, "e,f,g", 0 },
{ "mm12mpm.dd", 0x48000189, 0xb4000676, "e,f,g", 0 },
{ "mrm1p2.ss", 0x4800000a, 0xb40007f5, "e,f,g", 0 },
{ "mrm1p2.sd", 0x4800008a, 0xb4000775, "e,f,g", 0 },
{ "mrm1p2.dd", 0x4800018a, 0xb4000675, "e,f,g", 0 },
{ "mm12ttpm.ss",0x4800000b, 0xb40007f4, "e,f,g", 0 },
{ "mm12ttpm.sd",0x4800008b, 0xb4000774, "e,f,g", 0 },
{ "mm12ttpm.dd",0x4800018b, 0xb4000674, "e,f,g", 0 },
{ "mimt1p2.ss", 0x4800000c, 0xb40007f3, "e,f,g", 0 },
{ "mimt1p2.sd", 0x4800008c, 0xb4000773, "e,f,g", 0 },
{ "mimt1p2.dd", 0x4800018c, 0xb4000673, "e,f,g", 0 },
{ "mm12tpm.ss", 0x4800000d, 0xb40007f2, "e,f,g", 0 },
{ "mm12tpm.sd", 0x4800008d, 0xb4000772, "e,f,g", 0 },
{ "mm12tpm.dd", 0x4800018d, 0xb4000672, "e,f,g", 0 },
{ "mim1p2.ss", 0x4800000e, 0xb40007f1, "e,f,g", 0 },
{ "mim1p2.sd", 0x4800008e, 0xb4000771, "e,f,g", 0 },
{ "mim1p2.dd", 0x4800018e, 0xb4000671, "e,f,g", 0 },
{ "mr2p1.ss", 0x48000000, 0xb40005ff, "e,f,g", 0 },
{ "mr2p1.sd", 0x48000080, 0xb400057f, "e,f,g", 0 },
{ "mr2p1.dd", 0x48000180, 0xb400047f, "e,f,g", 0 },
{ "mr2pt.ss", 0x48000001, 0xb40005fe, "e,f,g", 0 },
{ "mr2pt.sd", 0x48000081, 0xb400057e, "e,f,g", 0 },
{ "mr2pt.dd", 0x48000181, 0xb400047e, "e,f,g", 0 },
{ "mr2mp1.ss", 0x48000002, 0xb40005fd, "e,f,g", 0 },
{ "mr2mp1.sd", 0x48000082, 0xb400057d, "e,f,g", 0 },
{ "mr2mp1.dd", 0x48000182, 0xb400047d, "e,f,g", 0 },
{ "mr2mpt.ss", 0x48000003, 0xb40005fc, "e,f,g", 0 },
{ "mr2mpt.sd", 0x48000083, 0xb400057c, "e,f,g", 0 },
{ "mr2mpt.dd", 0x48000183, 0xb400047c, "e,f,g", 0 },
{ "mi2p1.ss", 0x48000004, 0xb40005fb, "e,f,g", 0 },
{ "mi2p1.sd", 0x48000084, 0xb400057b, "e,f,g", 0 },
{ "mi2p1.dd", 0x48000184, 0xb400047b, "e,f,g", 0 },
{ "mi2pt.ss", 0x48000005, 0xb40005fa, "e,f,g", 0 },
{ "mi2pt.sd", 0x48000085, 0xb400057a, "e,f,g", 0 },
{ "mi2pt.dd", 0x48000185, 0xb400047a, "e,f,g", 0 },
{ "mi2mp1.ss", 0x48000006, 0xb40005f9, "e,f,g", 0 },
{ "mi2mp1.sd", 0x48000086, 0xb4000579, "e,f,g", 0 },
{ "mi2mp1.dd", 0x48000186, 0xb4000479, "e,f,g", 0 },
{ "mi2mpt.ss", 0x48000007, 0xb40005f8, "e,f,g", 0 },
{ "mi2mpt.sd", 0x48000087, 0xb4000578, "e,f,g", 0 },
{ "mi2mpt.dd", 0x48000187, 0xb4000478, "e,f,g", 0 },
{ "mrmt1p2.ss", 0x48000008, 0xb40005f7, "e,f,g", 0 },
{ "mrmt1p2.sd", 0x48000088, 0xb4000577, "e,f,g", 0 },
{ "mrmt1p2.dd", 0x48000188, 0xb4000477, "e,f,g", 0 },
{ "mm12mpm.ss", 0x48000009, 0xb40005f6, "e,f,g", 0 },
{ "mm12mpm.sd", 0x48000089, 0xb4000576, "e,f,g", 0 },
{ "mm12mpm.dd", 0x48000189, 0xb4000476, "e,f,g", 0 },
{ "mrm1p2.ss", 0x4800000a, 0xb40005f5, "e,f,g", 0 },
{ "mrm1p2.sd", 0x4800008a, 0xb4000575, "e,f,g", 0 },
{ "mrm1p2.dd", 0x4800018a, 0xb4000475, "e,f,g", 0 },
{ "mm12ttpm.ss",0x4800000b, 0xb40005f4, "e,f,g", 0 },
{ "mm12ttpm.sd",0x4800008b, 0xb4000574, "e,f,g", 0 },
{ "mm12ttpm.dd",0x4800018b, 0xb4000474, "e,f,g", 0 },
{ "mimt1p2.ss", 0x4800000c, 0xb40005f3, "e,f,g", 0 },
{ "mimt1p2.sd", 0x4800008c, 0xb4000573, "e,f,g", 0 },
{ "mimt1p2.dd", 0x4800018c, 0xb4000473, "e,f,g", 0 },
{ "mm12tpm.ss", 0x4800000d, 0xb40005f2, "e,f,g", 0 },
{ "mm12tpm.sd", 0x4800008d, 0xb4000572, "e,f,g", 0 },
{ "mm12tpm.dd", 0x4800018d, 0xb4000472, "e,f,g", 0 },
{ "mim1p2.ss", 0x4800000e, 0xb40005f1, "e,f,g", 0 },
{ "mim1p2.sd", 0x4800008e, 0xb4000571, "e,f,g", 0 },
{ "mim1p2.dd", 0x4800018e, 0xb4000471, "e,f,g", 0 },
/* Floating Point Escape Instruction Format - pfmsm.p fsrc1,fsrc2,fdest */
{ "mr2s1.ss", 0x48000010, 0xb40007ef, "e,f,g", 0 },
{ "mr2s1.sd", 0x48000090, 0xb400076f, "e,f,g", 0 },
{ "mr2s1.dd", 0x48000190, 0xb400066f, "e,f,g", 0 },
{ "mr2st.ss", 0x48000011, 0xb40007ee, "e,f,g", 0 },
{ "mr2st.sd", 0x48000091, 0xb400076e, "e,f,g", 0 },
{ "mr2st.dd", 0x48000191, 0xb400066e, "e,f,g", 0 },
{ "mr2ms1.ss", 0x48000012, 0xb40007ed, "e,f,g", 0 },
{ "mr2ms1.sd", 0x48000092, 0xb400076d, "e,f,g", 0 },
{ "mr2ms1.dd", 0x48000192, 0xb400066d, "e,f,g", 0 },
{ "mr2mst.ss", 0x48000013, 0xb40007ec, "e,f,g", 0 },
{ "mr2mst.sd", 0x48000093, 0xb400076c, "e,f,g", 0 },
{ "mr2mst.dd", 0x48000193, 0xb400066c, "e,f,g", 0 },
{ "mi2s1.ss", 0x48000014, 0xb40007eb, "e,f,g", 0 },
{ "mi2s1.sd", 0x48000094, 0xb400076b, "e,f,g", 0 },
{ "mi2s1.dd", 0x48000194, 0xb400066b, "e,f,g", 0 },
{ "mi2st.ss", 0x48000015, 0xb40007ea, "e,f,g", 0 },
{ "mi2st.sd", 0x48000095, 0xb400076a, "e,f,g", 0 },
{ "mi2st.dd", 0x48000195, 0xb400066a, "e,f,g", 0 },
{ "mi2ms1.ss", 0x48000016, 0xb40007e9, "e,f,g", 0 },
{ "mi2ms1.sd", 0x48000096, 0xb4000769, "e,f,g", 0 },
{ "mi2ms1.dd", 0x48000196, 0xb4000669, "e,f,g", 0 },
{ "mi2mst.ss", 0x48000017, 0xb40007e8, "e,f,g", 0 },
{ "mi2mst.sd", 0x48000097, 0xb4000768, "e,f,g", 0 },
{ "mi2mst.dd", 0x48000197, 0xb4000668, "e,f,g", 0 },
{ "mrmt1s2.ss", 0x48000018, 0xb40007e7, "e,f,g", 0 },
{ "mrmt1s2.sd", 0x48000098, 0xb4000767, "e,f,g", 0 },
{ "mrmt1s2.dd", 0x48000198, 0xb4000667, "e,f,g", 0 },
{ "mm12msm.ss", 0x48000019, 0xb40007e6, "e,f,g", 0 },
{ "mm12msm.sd", 0x48000099, 0xb4000766, "e,f,g", 0 },
{ "mm12msm.dd", 0x48000199, 0xb4000666, "e,f,g", 0 },
{ "mrm1s2.ss", 0x4800001a, 0xb40007e5, "e,f,g", 0 },
{ "mrm1s2.sd", 0x4800009a, 0xb4000765, "e,f,g", 0 },
{ "mrm1s2.dd", 0x4800019a, 0xb4000665, "e,f,g", 0 },
{ "mm12ttsm.ss",0x4800001b, 0xb40007e4, "e,f,g", 0 },
{ "mm12ttsm.sd",0x4800009b, 0xb4000764, "e,f,g", 0 },
{ "mm12ttsm.dd",0x4800019b, 0xb4000664, "e,f,g", 0 },
{ "mimt1s2.ss", 0x4800001c, 0xb40007e3, "e,f,g", 0 },
{ "mimt1s2.sd", 0x4800009c, 0xb4000763, "e,f,g", 0 },
{ "mimt1s2.dd", 0x4800019c, 0xb4000663, "e,f,g", 0 },
{ "mm12tsm.ss", 0x4800001d, 0xb40007e2, "e,f,g", 0 },
{ "mm12tsm.sd", 0x4800009d, 0xb4000762, "e,f,g", 0 },
{ "mm12tsm.dd", 0x4800019d, 0xb4000662, "e,f,g", 0 },
{ "mim1s2.ss", 0x4800001e, 0xb40007e1, "e,f,g", 0 },
{ "mim1s2.sd", 0x4800009e, 0xb4000761, "e,f,g", 0 },
{ "mim1s2.dd", 0x4800019e, 0xb4000661, "e,f,g", 0 },
{ "mr2s1.ss", 0x48000010, 0xb40005ef, "e,f,g", 0 },
{ "mr2s1.sd", 0x48000090, 0xb400056f, "e,f,g", 0 },
{ "mr2s1.dd", 0x48000190, 0xb400046f, "e,f,g", 0 },
{ "mr2st.ss", 0x48000011, 0xb40005ee, "e,f,g", 0 },
{ "mr2st.sd", 0x48000091, 0xb400056e, "e,f,g", 0 },
{ "mr2st.dd", 0x48000191, 0xb400046e, "e,f,g", 0 },
{ "mr2ms1.ss", 0x48000012, 0xb40005ed, "e,f,g", 0 },
{ "mr2ms1.sd", 0x48000092, 0xb400056d, "e,f,g", 0 },
{ "mr2ms1.dd", 0x48000192, 0xb400046d, "e,f,g", 0 },
{ "mr2mst.ss", 0x48000013, 0xb40005ec, "e,f,g", 0 },
{ "mr2mst.sd", 0x48000093, 0xb400056c, "e,f,g", 0 },
{ "mr2mst.dd", 0x48000193, 0xb400046c, "e,f,g", 0 },
{ "mi2s1.ss", 0x48000014, 0xb40005eb, "e,f,g", 0 },
{ "mi2s1.sd", 0x48000094, 0xb400056b, "e,f,g", 0 },
{ "mi2s1.dd", 0x48000194, 0xb400046b, "e,f,g", 0 },
{ "mi2st.ss", 0x48000015, 0xb40005ea, "e,f,g", 0 },
{ "mi2st.sd", 0x48000095, 0xb400056a, "e,f,g", 0 },
{ "mi2st.dd", 0x48000195, 0xb400046a, "e,f,g", 0 },
{ "mi2ms1.ss", 0x48000016, 0xb40005e9, "e,f,g", 0 },
{ "mi2ms1.sd", 0x48000096, 0xb4000569, "e,f,g", 0 },
{ "mi2ms1.dd", 0x48000196, 0xb4000469, "e,f,g", 0 },
{ "mi2mst.ss", 0x48000017, 0xb40005e8, "e,f,g", 0 },
{ "mi2mst.sd", 0x48000097, 0xb4000568, "e,f,g", 0 },
{ "mi2mst.dd", 0x48000197, 0xb4000468, "e,f,g", 0 },
{ "mrmt1s2.ss", 0x48000018, 0xb40005e7, "e,f,g", 0 },
{ "mrmt1s2.sd", 0x48000098, 0xb4000567, "e,f,g", 0 },
{ "mrmt1s2.dd", 0x48000198, 0xb4000467, "e,f,g", 0 },
{ "mm12msm.ss", 0x48000019, 0xb40005e6, "e,f,g", 0 },
{ "mm12msm.sd", 0x48000099, 0xb4000566, "e,f,g", 0 },
{ "mm12msm.dd", 0x48000199, 0xb4000466, "e,f,g", 0 },
{ "mrm1s2.ss", 0x4800001a, 0xb40005e5, "e,f,g", 0 },
{ "mrm1s2.sd", 0x4800009a, 0xb4000565, "e,f,g", 0 },
{ "mrm1s2.dd", 0x4800019a, 0xb4000465, "e,f,g", 0 },
{ "mm12ttsm.ss",0x4800001b, 0xb40005e4, "e,f,g", 0 },
{ "mm12ttsm.sd",0x4800009b, 0xb4000564, "e,f,g", 0 },
{ "mm12ttsm.dd",0x4800019b, 0xb4000464, "e,f,g", 0 },
{ "mimt1s2.ss", 0x4800001c, 0xb40005e3, "e,f,g", 0 },
{ "mimt1s2.sd", 0x4800009c, 0xb4000563, "e,f,g", 0 },
{ "mimt1s2.dd", 0x4800019c, 0xb4000463, "e,f,g", 0 },
{ "mm12tsm.ss", 0x4800001d, 0xb40005e2, "e,f,g", 0 },
{ "mm12tsm.sd", 0x4800009d, 0xb4000562, "e,f,g", 0 },
{ "mm12tsm.dd", 0x4800019d, 0xb4000462, "e,f,g", 0 },
{ "mim1s2.ss", 0x4800001e, 0xb40005e1, "e,f,g", 0 },
{ "mim1s2.sd", 0x4800009e, 0xb4000561, "e,f,g", 0 },
{ "mim1s2.dd", 0x4800019e, 0xb4000461, "e,f,g", 0 },
{ "fmul.ss", 0x48000020, 0xb40007df, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */
{ "fmul.sd", 0x480000a0, 0xb400075f, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */
{ "fmul.dd", 0x480001a0, 0xb400065f, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */
{ "pfmul.ss", 0x48000420, 0xb40003df, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */
{ "pfmul.sd", 0x480004a0, 0xb400035f, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */
{ "pfmul.dd", 0x480005a0, 0xb400025f, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */
{ "pfmul3.dd", 0x480005a4, 0xb400025b, "e,f,g", 0 }, /* pfmul3.p fsrc1,fsrc2,fdest */
{ "fmlow.dd", 0x480001a1, 0xb400065e, "e,f,g", 0 }, /* fmlow.dd fsrc1,fsrc2,fdest */
{ "frcp.ss", 0x48000022, 0xb40007dd, "f,g", 0 }, /* frcp.p fsrc2,fdest */
{ "frcp.sd", 0x480000a2, 0xb400075d, "f,g", 0 }, /* frcp.p fsrc2,fdest */
{ "frcp.dd", 0x480001a2, 0xb400065d, "f,g", 0 }, /* frcp.p fsrc2,fdest */
{ "frsqr.ss", 0x48000023, 0xb40007dc, "f,g", 0 }, /* frsqr.p fsrc2,fdest */
{ "frsqr.sd", 0x480000a3, 0xb400075c, "f,g", 0 }, /* frsqr.p fsrc2,fdest */
{ "frsqr.dd", 0x480001a3, 0xb400065c, "f,g", 0 }, /* frsqr.p fsrc2,fdest */
{ "fadd.ss", 0x48000030, 0xb40007cf, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */
{ "fadd.sd", 0x480000b0, 0xb400074f, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */
{ "fadd.dd", 0x480001b0, 0xb400064f, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */
{ "pfadd.ss", 0x48000430, 0xb40003cf, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */
{ "pfadd.sd", 0x480004b0, 0xb400034f, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */
{ "pfadd.dd", 0x480005b0, 0xb400024f, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */
{ "fsub.ss", 0x48000031, 0xb40007ce, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */
{ "fsub.sd", 0x480000b1, 0xb400074e, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */
{ "fsub.dd", 0x480001b1, 0xb400064e, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */
{ "pfsub.ss", 0x48000431, 0xb40003ce, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */
{ "pfsub.sd", 0x480004b1, 0xb400034e, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */
{ "pfsub.dd", 0x480005b1, 0xb400024e, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */
{ "fix.ss", 0x48000032, 0xb40007cd, "e,g", 0 }, /* fix.p fsrc1,fdest */
{ "fix.sd", 0x480000b2, 0xb400074d, "e,g", 0 }, /* fix.p fsrc1,fdest */
{ "fix.dd", 0x480001b2, 0xb400064d, "e,g", 0 }, /* fix.p fsrc1,fdest */
{ "pfix.ss", 0x48000432, 0xb40003cd, "e,g", 0 }, /* pfix.p fsrc1,fdest */
{ "pfix.sd", 0x480004b2, 0xb400034d, "e,g", 0 }, /* pfix.p fsrc1,fdest */
{ "pfix.dd", 0x480005b2, 0xb400024d, "e,g", 0 }, /* pfix.p fsrc1,fdest */
{ "famov.ss", 0x48000033, 0xb40007cc, "e,g", 0 }, /* famov.p fsrc1,fdest */
{ "famov.ds", 0x48000133, 0xb40006cc, "e,g", 0 }, /* famov.p fsrc1,fdest */
{ "famov.sd", 0x480000b3, 0xb400074c, "e,g", 0 }, /* famov.p fsrc1,fdest */
{ "famov.dd", 0x480001b3, 0xb400064c, "e,g", 0 }, /* famov.p fsrc1,fdest */
{ "pfamov.ss", 0x48000433, 0xb40003cc, "e,g", 0 }, /* pfamov.p fsrc1,fdest */
{ "pfamov.ds", 0x48000533, 0xb40002cc, "e,g", 0 }, /* pfamov.p fsrc1,fdest */
{ "pfamov.sd", 0x480004b3, 0xb400034c, "e,g", 0 }, /* pfamov.p fsrc1,fdest */
{ "pfamov.dd", 0x480005b3, 0xb400024c, "e,g", 0 }, /* pfamov.p fsrc1,fdest */
{ "fmul.ss", 0x48000020, 0xb40005df, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */
{ "fmul.sd", 0x480000a0, 0xb400055f, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */
{ "fmul.dd", 0x480001a0, 0xb400045f, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */
{ "pfmul.ss", 0x48000420, 0xb40001df, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */
{ "pfmul.sd", 0x480004a0, 0xb400015f, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */
{ "pfmul.dd", 0x480005a0, 0xb400005f, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */
{ "pfmul3.dd", 0x480005a4, 0xb400005b, "e,f,g", 0 }, /* pfmul3.p fsrc1,fsrc2,fdest */
{ "fmlow.dd", 0x480001a1, 0xb400045e, "e,f,g", 0 }, /* fmlow.dd fsrc1,fsrc2,fdest */
{ "frcp.ss", 0x48000022, 0xb40005dd, "f,g", 0 }, /* frcp.p fsrc2,fdest */
{ "frcp.sd", 0x480000a2, 0xb400055d, "f,g", 0 }, /* frcp.p fsrc2,fdest */
{ "frcp.dd", 0x480001a2, 0xb400045d, "f,g", 0 }, /* frcp.p fsrc2,fdest */
{ "frsqr.ss", 0x48000023, 0xb40005dc, "f,g", 0 }, /* frsqr.p fsrc2,fdest */
{ "frsqr.sd", 0x480000a3, 0xb400055c, "f,g", 0 }, /* frsqr.p fsrc2,fdest */
{ "frsqr.dd", 0x480001a3, 0xb400045c, "f,g", 0 }, /* frsqr.p fsrc2,fdest */
{ "fadd.ss", 0x48000030, 0xb40005cf, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */
{ "fadd.sd", 0x480000b0, 0xb400054f, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */
{ "fadd.dd", 0x480001b0, 0xb400044f, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */
{ "pfadd.ss", 0x48000430, 0xb40001cf, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */
{ "pfadd.sd", 0x480004b0, 0xb400014f, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */
{ "pfadd.dd", 0x480005b0, 0xb400004f, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */
{ "fsub.ss", 0x48000031, 0xb40005ce, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */
{ "fsub.sd", 0x480000b1, 0xb400054e, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */
{ "fsub.dd", 0x480001b1, 0xb400044e, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */
{ "pfsub.ss", 0x48000431, 0xb40001ce, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */
{ "pfsub.sd", 0x480004b1, 0xb400014e, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */
{ "pfsub.dd", 0x480005b1, 0xb400004e, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */
{ "fix.ss", 0x48000032, 0xb40005cd, "e,g", 0 }, /* fix.p fsrc1,fdest */
{ "fix.sd", 0x480000b2, 0xb400054d, "e,g", 0 }, /* fix.p fsrc1,fdest */
{ "fix.dd", 0x480001b2, 0xb400044d, "e,g", 0 }, /* fix.p fsrc1,fdest */
{ "pfix.ss", 0x48000432, 0xb40001cd, "e,g", 0 }, /* pfix.p fsrc1,fdest */
{ "pfix.sd", 0x480004b2, 0xb400014d, "e,g", 0 }, /* pfix.p fsrc1,fdest */
{ "pfix.dd", 0x480005b2, 0xb400004d, "e,g", 0 }, /* pfix.p fsrc1,fdest */
{ "famov.ss", 0x48000033, 0xb40005cc, "e,g", 0 }, /* famov.p fsrc1,fdest */
{ "famov.ds", 0x48000133, 0xb40004cc, "e,g", 0 }, /* famov.p fsrc1,fdest */
{ "famov.sd", 0x480000b3, 0xb400054c, "e,g", 0 }, /* famov.p fsrc1,fdest */
{ "famov.dd", 0x480001b3, 0xb400044c, "e,g", 0 }, /* famov.p fsrc1,fdest */
{ "pfamov.ss", 0x48000433, 0xb40001cc, "e,g", 0 }, /* pfamov.p fsrc1,fdest */
{ "pfamov.ds", 0x48000533, 0xb40000cc, "e,g", 0 }, /* pfamov.p fsrc1,fdest */
{ "pfamov.sd", 0x480004b3, 0xb400014c, "e,g", 0 }, /* pfamov.p fsrc1,fdest */
{ "pfamov.dd", 0x480005b3, 0xb400004c, "e,g", 0 }, /* pfamov.p fsrc1,fdest */
/* pfgt has R bit cleared; pfle has R bit set */
{ "pfgt.ss", 0x48000434, 0xb40003cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */
{ "pfgt.sd", 0x48000434, 0xb40003cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */
{ "pfgt.dd", 0x48000534, 0xb40002cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */
{ "pfgt.ss", 0x48000434, 0xb40001cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */
{ "pfgt.dd", 0x48000534, 0xb40000cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */
/* pfgt has R bit cleared; pfle has R bit set */
{ "pfle.ss", 0x480004b4, 0xb400034b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */
{ "pfle.sd", 0x480004b4, 0xb400034b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */
{ "pfle.dd", 0x480005b4, 0xb400024b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */
{ "ftrunc.ss", 0x4800003a, 0xb40007c5, "e,g", 0 }, /* ftrunc.p fsrc1,fdest */
{ "ftrunc.sd", 0x480000ba, 0xb4000745, "e,g", 0 }, /* ftrunc.p fsrc1,fdest */
{ "ftrunc.dd", 0x480001ba, 0xb4000645, "e,g", 0 }, /* ftrunc.p fsrc1,fdest */
{ "pftrunc.ss", 0x4800043a, 0xb40003c5, "e,g", 0 }, /* pftrunc.p fsrc1,fdest */
{ "pftrunc.sd", 0x480004ba, 0xb4000345, "e,g", 0 }, /* pftrunc.p fsrc1,fdest */
{ "pftrunc.dd", 0x480005ba, 0xb4000245, "e,g", 0 }, /* pftrunc.p fsrc1,fdest */
{ "fxfr", 0x48000040, 0xb40007bf, "e,d", 0 }, /* fxfr fsrc1,idest */
{ "fiadd.ss", 0x48000049, 0xb40007b6, "e,f,g", 0 }, /* fiadd.w fsrc1,fsrc2,fdest */
{ "fiadd.dd", 0x480001c9, 0xb4000636, "e,f,g", 0 }, /* fiadd.w fsrc1,fsrc2,fdest */
{ "pfiadd.ss", 0x48000449, 0xb40003b6, "e,f,g", 0 }, /* pfiadd.w fsrc1,fsrc2,fdest */
{ "pfiadd.dd", 0x480005c9, 0xb4000236, "e,f,g", 0 }, /* pfiadd.w fsrc1,fsrc2,fdest */
{ "fisub.ss", 0x4800004d, 0xb40007b2, "e,f,g", 0 }, /* fisub.w fsrc1,fsrc2,fdest */
{ "fisub.dd", 0x480001cd, 0xb4000632, "e,f,g", 0 }, /* fisub.w fsrc1,fsrc2,fdest */
{ "pfisub.ss", 0x4800044d, 0xb40003b2, "e,f,g", 0 }, /* pfisub.w fsrc1,fsrc2,fdest */
{ "pfisub.dd", 0x480005cd, 0xb4000232, "e,f,g", 0 }, /* pfisub.w fsrc1,fsrc2,fdest */
{ "fzchkl", 0x48000057, 0xb40007a8, "e,f,g", 0 }, /* fzchkl fsrc1,fsrc2,fdest */
{ "pfzchkl", 0x48000457, 0xb40003a8, "e,f,g", 0 }, /* pfzchkl fsrc1,fsrc2,fdest */
{ "fzchks", 0x4800005f, 0xb40007a0, "e,f,g", 0 }, /* fzchks fsrc1,fsrc2,fdest */
{ "pfzchks", 0x4800045f, 0xb40003a0, "e,f,g", 0 }, /* pfzchks fsrc1,fsrc2,fdest */
{ "faddp", 0x48000050, 0xb40007af, "e,f,g", 0 }, /* faddp fsrc1,fsrc2,fdest */
{ "pfaddp", 0x48000450, 0xb40003af, "e,f,g", 0 }, /* pfaddp fsrc1,fsrc2,fdest */
{ "faddz", 0x48000051, 0xb40007ae, "e,f,g", 0 }, /* faddz fsrc1,fsrc2,fdest */
{ "pfaddz", 0x48000451, 0xb40003ae, "e,f,g", 0 }, /* pfaddz fsrc1,fsrc2,fdest */
{ "form", 0x4800005a, 0xb40007a5, "e,g", 0 }, /* form fsrc1,fdest */
{ "pform", 0x4800045a, 0xb40003a5, "e,g", 0 }, /* pform fsrc1,fdest */
{ "pfle.ss", 0x480004b4, 0xb400014b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */
{ "pfle.dd", 0x480005b4, 0xb400004b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */
{ "pfeq.ss", 0x48000435, 0xb40001ca, "e,f,g", 0 }, /* pfeq.p fsrc1,fsrc2,fdest */
{ "pfeq.dd", 0x48000535, 0xb40000ca, "e,f,g", 0 }, /* pfeq.p fsrc1,fsrc2,fdest */
{ "ftrunc.ss", 0x4800003a, 0xb40005c5, "e,g", 0 }, /* ftrunc.p fsrc1,fdest */
{ "ftrunc.sd", 0x480000ba, 0xb4000545, "e,g", 0 }, /* ftrunc.p fsrc1,fdest */
{ "ftrunc.dd", 0x480001ba, 0xb4000445, "e,g", 0 }, /* ftrunc.p fsrc1,fdest */
{ "pftrunc.ss", 0x4800043a, 0xb40001c5, "e,g", 0 }, /* pftrunc.p fsrc1,fdest */
{ "pftrunc.sd", 0x480004ba, 0xb4000145, "e,g", 0 }, /* pftrunc.p fsrc1,fdest */
{ "pftrunc.dd", 0x480005ba, 0xb4000045, "e,g", 0 }, /* pftrunc.p fsrc1,fdest */
{ "fxfr", 0x48000040, 0xb40005bf, "e,d", 0 }, /* fxfr fsrc1,idest */
{ "fiadd.ss", 0x48000049, 0xb40005b6, "e,f,g", 0 }, /* fiadd.w fsrc1,fsrc2,fdest */
{ "fiadd.dd", 0x480001c9, 0xb4000436, "e,f,g", 0 }, /* fiadd.w fsrc1,fsrc2,fdest */
{ "pfiadd.ss", 0x48000449, 0xb40001b6, "e,f,g", 0 }, /* pfiadd.w fsrc1,fsrc2,fdest */
{ "pfiadd.dd", 0x480005c9, 0xb4000036, "e,f,g", 0 }, /* pfiadd.w fsrc1,fsrc2,fdest */
{ "fisub.ss", 0x4800004d, 0xb40005b2, "e,f,g", 0 }, /* fisub.w fsrc1,fsrc2,fdest */
{ "fisub.dd", 0x480001cd, 0xb4000432, "e,f,g", 0 }, /* fisub.w fsrc1,fsrc2,fdest */
{ "pfisub.ss", 0x4800044d, 0xb40001b2, "e,f,g", 0 }, /* pfisub.w fsrc1,fsrc2,fdest */
{ "pfisub.dd", 0x480005cd, 0xb4000032, "e,f,g", 0 }, /* pfisub.w fsrc1,fsrc2,fdest */
{ "fzchkl", 0x480001d7, 0xb4000428, "e,f,g", 0 }, /* fzchkl fsrc1,fsrc2,fdest */
{ "pfzchkl", 0x480005d7, 0xb4000028, "e,f,g", 0 }, /* pfzchkl fsrc1,fsrc2,fdest */
{ "fzchks", 0x4800015f, 0xb4000420, "e,f,g", 0 }, /* fzchks fsrc1,fsrc2,fdest */
{ "pfzchks", 0x4800055f, 0xb4000020, "e,f,g", 0 }, /* pfzchks fsrc1,fsrc2,fdest */
{ "faddp", 0x48000050, 0xb40005af, "e,f,g", 0 }, /* faddp fsrc1,fsrc2,fdest */
{ "pfaddp", 0x48000450, 0xb40001af, "e,f,g", 0 }, /* pfaddp fsrc1,fsrc2,fdest */
{ "faddz", 0x480001d1, 0xb400042e, "e,f,g", 0 }, /* faddz fsrc1,fsrc2,fdest */
{ "pfaddz", 0x480005d1, 0xb400002e, "e,f,g", 0 }, /* pfaddz fsrc1,fsrc2,fdest */
{ "form", 0x480001da, 0xb4000425, "e,g", 0 }, /* form fsrc1,fdest */
{ "pform", 0x480005da, 0xb4000025, "e,g", 0 }, /* pform fsrc1,fdest */
/* Floating point pseudo-instructions */
{ "fmov.ss", 0x48000049, 0xb7e007b6, "e,g", 0 }, /* fiadd.ss fsrc1,f0,fdest */
{ "fmov.dd", 0x480001c9, 0xb7e00636, "e,g", 0 }, /* fiadd.dd fsrc1,f0,fdest */
{ "fmov.sd", 0x480000b0, 0xb7e0074f, "e,g", 0 }, /* fadd.sd fsrc1,f0,fdest */
{ "fmov.ds", 0x48000130, 0xb7e006cf, "e,g", 0 }, /* fadd.ds fsrc1,f0,fdest */
{ "pfmov.ds", 0x48000530, 0xb73002cf, "e,g", 0 }, /* pfadd.ds fsrc1,f0,fdest */
{ "pfmov.dd", 0x480005c9, 0xb7e00236, "e,g", 0 }, /* pfiadd.dd fsrc1,f0,fdest */
{ "fmov.ss", 0x48000049, 0xb7e005b6, "e,g", 0 }, /* fiadd.ss fsrc1,f0,fdest */
{ "fmov.dd", 0x480001c9, 0xb7e00436, "e,g", 0 }, /* fiadd.dd fsrc1,f0,fdest */
{ "fmov.sd", 0x480000b0, 0xb7e0054f, "e,g", 0 }, /* fadd.sd fsrc1,f0,fdest */
{ "fmov.ds", 0x48000130, 0xb7e004cf, "e,g", 0 }, /* fadd.ds fsrc1,f0,fdest */
{ "pfmov.ds", 0x48000530, 0xb73000cf, "e,g", 0 }, /* pfadd.ds fsrc1,f0,fdest */
{ "pfmov.dd", 0x480005c9, 0xb7e00036, "e,g", 0 }, /* pfiadd.dd fsrc1,f0,fdest */
{ 0, 0, 0, 0, 0 },
};

4
opcodes/Makefile.in
View File

@ -168,6 +168,7 @@ CFILES = \
i370-dis.c \
i370-opc.c \
i386-dis.c \
i860-dis.c \
i960-dis.c \
ia64-dis.c \
ia64-opc-a.c \
@ -247,6 +248,7 @@ ALL_MACHINES = \
i386-dis.lo \
i370-dis.lo \
i370-opc.lo \
i860-dis.lo \
i960-dis.lo \
ia64-dis.lo \
ia64-opc.lo \
@ -866,6 +868,8 @@ i370-opc.lo: i370-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/opcode/i370.h
i386-dis.lo: i386-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
$(INCDIR)/ansidecl.h sysdep.h config.h opintl.h
i860-dis.lo: i860-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
$(INCDIR)/ansidecl.h $(INCDIR)/opcode/i860.h
i960-dis.lo: i960-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h $(BFD_H)
ia64-dis.lo: ia64-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \

321
opcodes/configure vendored
View File

File diff suppressed because it is too large Load Diff

2
opcodes/configure.in
View File

@ -165,7 +165,7 @@ if test x${all_targets} = xfalse ; then
bfd_hppa_arch) ta="$ta hppa-dis.lo" ;;
bfd_i370_arch) ta="$ta i370-dis.lo i370-opc.lo" ;;
bfd_i386_arch) ta="$ta i386-dis.lo" ;;
bfd_i860_arch) ;;
bfd_i860_arch) ta="$ta i860-dis.lo" ;;
bfd_i960_arch) ta="$ta i960-dis.lo" ;;
bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;;
bfd_m32r_arch) ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;;

6
opcodes/disassemble.c
View File

@ -33,6 +33,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#define ARCH_hppa
#define ARCH_i370
#define ARCH_i386
#define ARCH_i860
#define ARCH_i960
#define ARCH_ia64
#define ARCH_fr30
@ -152,6 +153,11 @@ disassembler (abfd)
disassemble = print_insn_i386_att;
break;
#endif
#ifdef ARCH_i860
case bfd_arch_i860:
disassemble = print_insn_i860;
break;
#endif
#ifdef ARCH_i960
case bfd_arch_i960:
disassemble = print_insn_i960;

288
opcodes/i860-dis.c Normal file
View File

@ -0,0 +1,288 @@
/* Disassembler for the i860.
Copyright 2000 Free Software Foundation, Inc.
Contributed by Jason Eckhardt <jle@cygnus.com>.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "dis-asm.h"
#include "opcode/i860.h"
/* Later we should probably choose the prefix based on which OS flavor. */
#define I860_REG_PREFIX "%"
/* Integer register names (encoded as 0..31 in the instruction). */
static const char *const grnames[] =
{"r0", "r1", "sp", "fp", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"};
/* FP register names (encoded as 0..31 in the instruction). */
static const char *const frnames[] =
{"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"};
/* Control/status register names (encoded as 0..5 in the instruction). */
static const char *const crnames[] =
{"fir", "psr", "dirbase", "db", "fsr", "epsr", "", ""};
/* Prototypes. */
static int sign_ext PARAMS((unsigned int, int));
static void print_br_address PARAMS((disassemble_info *, bfd_vma, int));
/* True if opcode is xor, xorh, and, andh, or, orh, andnot, andnoth. */
#define BITWISE_OP(op) ((op) == 0x30 || (op) == 0x31 \
|| (op) == 0x34 || (op) == 0x35 \
|| (op) == 0x38 || (op) == 0x39 \
|| (op) == 0x3c || (op) == 0x3d \
|| (op) == 0x33 || (op) == 0x37 \
|| (op) == 0x3b || (op) == 0x3f)
/* Sign extend N-bit number. */
static int
sign_ext (x, n)
unsigned int x;
int n;
{
int t;
t = x >> (n - 1);
t = ((-t) << n) | x;
return t;
}
/* Print a PC-relative branch offset. VAL is the sign extended value
from the branch instruction. */
static void
print_br_address (info, memaddr, val)
disassemble_info *info;
bfd_vma memaddr;
int val;
{
int adj = memaddr + 4 + (val << 2);
(*info->fprintf_func) (info->stream, "0x%08x", adj);
/* Attempt to obtain a symbol for the target address. */
if (info->print_address_func && adj != 0)
{
(*info->fprintf_func) (info->stream, "\t// ");
(*info->print_address_func) (adj, info);
}
}
/* Print one instruction. */
int
print_insn_i860 (memaddr, info)
bfd_vma memaddr;
disassemble_info *info;
{
bfd_byte buff[4];
unsigned int insn, i;
int status;
const struct i860_opcode *opcode = 0;
status = (*info->read_memory_func) (memaddr, buff, sizeof (buff), info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
/* Note that i860 instructions are always accessed as little endian
data, regardless of the endian mode of the i860. */
insn = bfd_getl32 (buff);
status = 0;
i = 0;
while (i860_opcodes[i].name != NULL)
{
opcode = &i860_opcodes[i];
if ((insn & opcode->match) == opcode->match
&& (insn & opcode->lose) == 0)
{
status = 1;
break;
}
++i;
}
if (status == 0)
{
/* Instruction not in opcode table. */
(*info->fprintf_func) (info->stream, ".long %#08x", insn);
}
else
{
const char *s;
int val;
/* If this a flop and its dual bit is set, prefix with 'd.'. */
if ((insn & 0xfc000000) == 0x48000000 && (insn & 0x200))
(*info->fprintf_func) (info->stream, "d.%s\t", opcode->name);
else
(*info->fprintf_func) (info->stream, "%s\t", opcode->name);
for (s = opcode->args; *s; s++)
{
switch (*s)
{
/* Integer register (src1). */
case '1':
(*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
grnames[(insn >> 11) & 0x1f]);
break;
/* Integer register (src2). */
case '2':
(*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
grnames[(insn >> 21) & 0x1f]);
break;
/* Integer destination register. */
case 'd':
(*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
grnames[(insn >> 16) & 0x1f]);
break;
/* Floating-point register (src1). */
case 'e':
(*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
frnames[(insn >> 11) & 0x1f]);
break;
/* Floating-point register (src2). */
case 'f':
(*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
frnames[(insn >> 21) & 0x1f]);
break;
/* Floating-point destination register. */
case 'g':
(*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
frnames[(insn >> 16) & 0x1f]);
break;
/* Control register. */
case 'c':
(*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
crnames[(insn >> 21) & 0x7]);
break;
/* 16-bit immediate (sign extend, except for bitwise ops). */
case 'i':
if (BITWISE_OP ((insn & 0xfc000000) >> 26))
(*info->fprintf_func) (info->stream, "0x%04x",
(unsigned int) (insn & 0xffff));
else
(*info->fprintf_func) (info->stream, "%d",
sign_ext ((insn & 0xffff), 16));
break;
/* 16-bit immediate, aligned (2^0, ld.b). */
case 'I':
(*info->fprintf_func) (info->stream, "%d",
sign_ext ((insn & 0xffff), 16));
break;
/* 16-bit immediate, aligned (2^1, ld.s). */
case 'J':
(*info->fprintf_func) (info->stream, "%d",
sign_ext ((insn & 0xfffe), 16));
break;
/* 16-bit immediate, aligned (2^2, ld.l, {p}fld.l, fst.l). */
case 'K':
(*info->fprintf_func) (info->stream, "%d",
sign_ext ((insn & 0xfffc), 16));
break;
/* 16-bit immediate, aligned (2^3, {p}fld.d, fst.d). */
case 'L':
(*info->fprintf_func) (info->stream, "%d",
sign_ext ((insn & 0xfff8), 16));
break;
/* 16-bit immediate, aligned (2^4, {p}fld.q, fst.q). */
case 'M':
(*info->fprintf_func) (info->stream, "%d",
sign_ext ((insn & 0xfff0), 16));
break;
/* 5-bit immediate (zero extend). */
case '5':
(*info->fprintf_func) (info->stream, "%d",
((insn >> 11) & 0x1f));
break;
/* Split 16 bit immediate (20..16:10..0). */
case 's':
val = ((insn >> 5) & 0xf800) | (insn & 0x07ff);
(*info->fprintf_func) (info->stream, "%d",
sign_ext (val, 16));
break;
/* Split 16 bit immediate, aligned. (2^0, st.b). */
case 'S':
val = ((insn >> 5) & 0xf800) | (insn & 0x07ff);
(*info->fprintf_func) (info->stream, "%d",
sign_ext (val, 16));
break;
/* Split 16 bit immediate, aligned. (2^1, st.s). */
case 'T':
val = ((insn >> 5) & 0xf800) | (insn & 0x07fe);
(*info->fprintf_func) (info->stream, "%d",
sign_ext (val, 16));
break;
/* Split 16 bit immediate, aligned. (2^2, st.l). */
case 'U':
val = ((insn >> 5) & 0xf800) | (insn & 0x07fc);
(*info->fprintf_func) (info->stream, "%d",
sign_ext (val, 16));
break;
/* 26-bit PC relative immediate (lbroff). */
case 'l':
val = sign_ext ((insn & 0x03ffffff), 26);
print_br_address (info, memaddr, val);
break;
/* 16-bit PC relative immediate (sbroff). */
case 'r':
val = sign_ext ((((insn >> 5) & 0xf800) | (insn & 0x07ff)), 16);
print_br_address (info, memaddr, val);
break;
default:
(*info->fprintf_func) (info->stream, "%c", *s);
break;
}
}
}
return sizeof (insn);
}