[GAS][ARM][3/3]Add armv8.2 fp16 scalar instruction support. Based on SE_H instruction shape.
gas/ 2016-02-24 Renlin Li <renlin.li@arm.com> * config/tc-arm.c (BAD_FP16): New error message macro. (do_scalar_fp16_v82_encode): Change the coproc field to 9 for armv8.2 fp16 scalar instructions. (neon_check_type): Allow different size from key. (do_vfp_nsyn_add_sub): Add support SE_H shape support. (try_vfp_nsyn): Likewise. (do_vfp_nsyn_mla_mls): Likewise. (do_vfp_nsyn_fma_fms): Likewise. (do_vfp_nsyn_ldm_stm): Likewise (do_vfp_nsyn_sqrt): Likewise (do_vfp_nsyn_div): Likewise (do_vfp_nsyn_nmul): Likewise. (do_vfp_nsyn_cmp): Likewise. (do_neon_shll): Likewise. (do_vfp_nsyn_cvt_fpv8): Likewise. (do_neon_cvttb_2): Likewise. (do_neon_mov): Likewise. (do_neon_rshift_round_imm): Likewise. (do_neon_ldr_str): Likewise. (do_vfp_nsyn_fpv8): Likewise. (do_vmaxnm): Likewise. (do_vrint_1): Likewise. (insns): New entry for vins, vmovx. (md_apply_fix): Left shift 1 bit for fp16 vldr/vstr. * testsuite/gas/arm/armv8-2-fp16-scalar-thumb.d: New. * testsuite/gas/arm/armv8-2-fp16-scalar.d: New. * testsuite/gas/arm/armv8-2-fp16-scalar.s: New. * testsuite/gas/arm/armv8-2-fp16-scalar-bad.s: New * testsuite/gas/arm/armv8-2-fp16-scalar-bad.d: New * testsuite/gas/arm/armv8-2-fp16-scalar-bad.l: New
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Renlin Li
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@ -1,3 +1,36 @@
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2016-02-24 Renlin Li <renlin.li@arm.com>
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* config/tc-arm.c (BAD_FP16): New error message macro.
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(do_scalar_fp16_v82_encode): Change the coproc field to 9 for armv8.2
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fp16 scalar instructions.
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(neon_check_type): Allow different size from key.
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(do_vfp_nsyn_add_sub): Add support SE_H shape support.
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(try_vfp_nsyn): Likewise.
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(do_vfp_nsyn_mla_mls): Likewise.
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(do_vfp_nsyn_fma_fms): Likewise.
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(do_vfp_nsyn_ldm_stm): Likewise
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(do_vfp_nsyn_sqrt): Likewise
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(do_vfp_nsyn_div): Likewise
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(do_vfp_nsyn_nmul): Likewise.
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(do_vfp_nsyn_cmp): Likewise.
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(do_neon_shll): Likewise.
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(do_vfp_nsyn_cvt_fpv8): Likewise.
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(do_neon_cvttb_2): Likewise.
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(do_neon_mov): Likewise.
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(do_neon_rshift_round_imm): Likewise.
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(do_neon_ldr_str): Likewise.
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(do_vfp_nsyn_fpv8): Likewise.
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(do_vmaxnm): Likewise.
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(do_vrint_1): Likewise.
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(insns): New entry for vins, vmovx.
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(md_apply_fix): Left shift 1 bit for fp16 vldr/vstr.
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* testsuite/gas/arm/armv8-2-fp16-scalar-thumb.d: New.
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* testsuite/gas/arm/armv8-2-fp16-scalar.d: New.
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* testsuite/gas/arm/armv8-2-fp16-scalar.s: New.
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* testsuite/gas/arm/armv8-2-fp16-scalar-bad.s: New
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* testsuite/gas/arm/armv8-2-fp16-scalar-bad.d: New
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* testsuite/gas/arm/armv8-2-fp16-scalar-bad.l: New
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2016-02-24 Renlin Li <renlin.li@arm.com>
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* config/tc-arm.c (NEON_ENC_TAB): Add fp16 instruction shape.
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@ -784,7 +784,8 @@ struct asm_opcode
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_("cannot use register index with PC-relative addressing")
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#define BAD_PC_WRITEBACK \
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_("cannot use writeback with PC-relative addressing")
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#define BAD_RANGE _("branch out of range")
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#define BAD_RANGE _("branch out of range")
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#define BAD_FP16 _("selected processor does not support fp16 instruction")
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#define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
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static struct hash_control * arm_ops_hsh;
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@ -7263,6 +7264,26 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
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#define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
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/* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
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The only binary encoding difference is the Coprocessor number. Coprocessor
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9 is used for half-precision calculations or conversions. The format of the
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instruction is the same as the equivalent Coprocessor 10 instuction that
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exists for Single-Precision operation. */
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static void
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do_scalar_fp16_v82_encode (void)
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{
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if (inst.cond != COND_ALWAYS)
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as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
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" the behaviour is UNPREDICTABLE"));
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constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16),
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_(BAD_FP16));
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inst.instruction = (inst.instruction & 0xfffff0ff) | 0x900;
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mark_feature_used (&arm_ext_fp16);
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}
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/* If VAL can be encoded in the immediate field of an ARM instruction,
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return the encoded form. Otherwise, return FAIL. */
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@ -13896,6 +13917,18 @@ neon_check_type (unsigned els, enum neon_shape ns, ...)
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else
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match = g_size;
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/* FP16 will use a single precision register. */
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if (regwidth == 32 && match == 16)
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{
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if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16))
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match = regwidth;
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else
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{
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inst.error = _(BAD_FP16);
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return badtype;
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}
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}
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if (regwidth != match)
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{
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first_error (_("operand size must match register width"));
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@ -13987,12 +14020,16 @@ do_vfp_nsyn_add_sub (enum neon_shape rs)
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{
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int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
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if (rs == NS_FFF)
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if (rs == NS_FFF || rs == NS_HHH)
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{
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if (is_add)
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do_vfp_nsyn_opcode ("fadds");
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else
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do_vfp_nsyn_opcode ("fsubs");
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/* ARMv8.2 fp16 instruction. */
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if (rs == NS_HHH)
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do_scalar_fp16_v82_encode ();
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}
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else
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{
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@ -14015,15 +14052,14 @@ try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
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switch (args)
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{
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case 2:
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rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
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et = neon_check_type (2, rs,
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N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
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rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
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et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
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break;
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case 3:
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rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
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et = neon_check_type (3, rs,
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N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
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rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
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et = neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
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N_F_ALL | N_KEY | N_VFP);
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break;
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default:
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@ -14045,12 +14081,16 @@ do_vfp_nsyn_mla_mls (enum neon_shape rs)
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{
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int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
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if (rs == NS_FFF)
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if (rs == NS_FFF || rs == NS_HHH)
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{
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if (is_mla)
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do_vfp_nsyn_opcode ("fmacs");
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else
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do_vfp_nsyn_opcode ("fnmacs");
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/* ARMv8.2 fp16 instruction. */
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if (rs == NS_HHH)
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do_scalar_fp16_v82_encode ();
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}
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else
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{
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@ -14066,12 +14106,16 @@ do_vfp_nsyn_fma_fms (enum neon_shape rs)
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{
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int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
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if (rs == NS_FFF)
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if (rs == NS_FFF || rs == NS_HHH)
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{
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if (is_fma)
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do_vfp_nsyn_opcode ("ffmas");
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else
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do_vfp_nsyn_opcode ("ffnmas");
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/* ARMv8.2 fp16 instruction. */
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if (rs == NS_HHH)
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do_scalar_fp16_v82_encode ();
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}
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else
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{
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@ -14085,8 +14129,14 @@ do_vfp_nsyn_fma_fms (enum neon_shape rs)
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static void
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do_vfp_nsyn_mul (enum neon_shape rs)
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{
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if (rs == NS_FFF)
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do_vfp_nsyn_opcode ("fmuls");
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if (rs == NS_FFF || rs == NS_HHH)
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{
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do_vfp_nsyn_opcode ("fmuls");
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/* ARMv8.2 fp16 instruction. */
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if (rs == NS_HHH)
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do_scalar_fp16_v82_encode ();
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}
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else
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do_vfp_nsyn_opcode ("fmuld");
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}
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@ -14095,14 +14145,18 @@ static void
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do_vfp_nsyn_abs_neg (enum neon_shape rs)
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{
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int is_neg = (inst.instruction & 0x80) != 0;
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neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
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neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_VFP | N_KEY);
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if (rs == NS_FF)
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if (rs == NS_FF || rs == NS_HH)
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{
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if (is_neg)
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do_vfp_nsyn_opcode ("fnegs");
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else
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do_vfp_nsyn_opcode ("fabss");
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/* ARMv8.2 fp16 instruction. */
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if (rs == NS_HH)
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do_scalar_fp16_v82_encode ();
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}
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else
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{
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@ -14139,11 +14193,17 @@ do_vfp_nsyn_ldm_stm (int is_dbmode)
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static void
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do_vfp_nsyn_sqrt (void)
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{
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enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
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neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
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enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
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neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
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if (rs == NS_FF)
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do_vfp_nsyn_opcode ("fsqrts");
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if (rs == NS_FF || rs == NS_HH)
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{
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do_vfp_nsyn_opcode ("fsqrts");
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/* ARMv8.2 fp16 instruction. */
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if (rs == NS_HH)
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do_scalar_fp16_v82_encode ();
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}
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else
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do_vfp_nsyn_opcode ("fsqrtd");
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}
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@ -14151,12 +14211,18 @@ do_vfp_nsyn_sqrt (void)
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static void
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do_vfp_nsyn_div (void)
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{
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enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
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enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
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neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
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N_F32 | N_F64 | N_KEY | N_VFP);
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N_F_ALL | N_KEY | N_VFP);
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if (rs == NS_FFF)
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do_vfp_nsyn_opcode ("fdivs");
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if (rs == NS_FFF || rs == NS_HHH)
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{
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do_vfp_nsyn_opcode ("fdivs");
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/* ARMv8.2 fp16 instruction. */
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if (rs == NS_HHH)
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do_scalar_fp16_v82_encode ();
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}
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else
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do_vfp_nsyn_opcode ("fdivd");
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}
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@ -14164,14 +14230,18 @@ do_vfp_nsyn_div (void)
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static void
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do_vfp_nsyn_nmul (void)
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{
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enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
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enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
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neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
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N_F32 | N_F64 | N_KEY | N_VFP);
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N_F_ALL | N_KEY | N_VFP);
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if (rs == NS_FFF)
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if (rs == NS_FFF || rs == NS_HHH)
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{
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NEON_ENCODE (SINGLE, inst);
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do_vfp_sp_dyadic ();
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/* ARMv8.2 fp16 instruction. */
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if (rs == NS_HHH)
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do_scalar_fp16_v82_encode ();
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}
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else
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{
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@ -14179,17 +14249,19 @@ do_vfp_nsyn_nmul (void)
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do_vfp_dp_rd_rn_rm ();
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}
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do_vfp_cond_or_thumb ();
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}
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static void
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do_vfp_nsyn_cmp (void)
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{
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enum neon_shape rs;
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if (inst.operands[1].isreg)
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{
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enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
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neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
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rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
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neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
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if (rs == NS_FF)
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if (rs == NS_FF || rs == NS_HH)
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{
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NEON_ENCODE (SINGLE, inst);
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do_vfp_sp_monadic ();
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@ -14202,8 +14274,8 @@ do_vfp_nsyn_cmp (void)
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}
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else
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{
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enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
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neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
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rs = neon_select_shape (NS_HI, NS_FI, NS_DI, NS_NULL);
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neon_check_type (2, rs, N_F_ALL | N_KEY | N_VFP, N_EQK);
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switch (inst.instruction & 0x0fffffff)
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{
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@ -14217,7 +14289,7 @@ do_vfp_nsyn_cmp (void)
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abort ();
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}
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if (rs == NS_FI)
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if (rs == NS_FI || rs == NS_HI)
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{
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NEON_ENCODE (SINGLE, inst);
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do_vfp_sp_compare_z ();
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@ -14229,6 +14301,10 @@ do_vfp_nsyn_cmp (void)
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}
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}
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do_vfp_cond_or_thumb ();
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/* ARMv8.2 fp16 instruction. */
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if (rs == NS_HI || rs == NS_HH)
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do_scalar_fp16_v82_encode ();
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}
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static void
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@ -15194,6 +15270,13 @@ do_neon_shll (void)
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/* Half-precision conversions. */ \
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CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
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CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
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/* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
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Compared with single/double precision variants, only the co-processor \
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field is different, so the encoding flow is reused here. */ \
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CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
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CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
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CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
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CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
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/* VFP instructions. */ \
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CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
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CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
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@ -15306,6 +15389,13 @@ do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour)
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if (opname)
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do_vfp_nsyn_opcode (opname);
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/* ARMv8.2 fp16 VCVT instruction. */
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if (flavour == neon_cvt_flavour_s32_f16
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|| flavour == neon_cvt_flavour_u32_f16
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|| flavour == neon_cvt_flavour_f16_u32
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|| flavour == neon_cvt_flavour_f16_s32)
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do_scalar_fp16_v82_encode ();
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}
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static void
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@ -15339,6 +15429,11 @@ do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour,
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constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
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_(BAD_FPU));
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if (flavour == neon_cvt_flavour_s32_f16
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|| flavour == neon_cvt_flavour_u32_f16)
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constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16),
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_(BAD_FP16));
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|
||||
set_it_insn_type (OUTSIDE_IT_INSN);
|
||||
|
||||
switch (flavour)
|
||||
|
|
@ -15351,6 +15446,10 @@ do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour,
|
|||
sz = 0;
|
||||
op = 1;
|
||||
break;
|
||||
case neon_cvt_flavour_s32_f16:
|
||||
sz = 0;
|
||||
op = 1;
|
||||
break;
|
||||
case neon_cvt_flavour_u32_f64:
|
||||
sz = 1;
|
||||
op = 0;
|
||||
|
|
@ -15359,6 +15458,10 @@ do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour,
|
|||
sz = 0;
|
||||
op = 0;
|
||||
break;
|
||||
case neon_cvt_flavour_u32_f16:
|
||||
sz = 0;
|
||||
op = 0;
|
||||
break;
|
||||
default:
|
||||
first_error (_("invalid instruction shape"));
|
||||
return;
|
||||
|
|
@ -15377,6 +15480,11 @@ do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour,
|
|||
encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
|
||||
encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm);
|
||||
inst.instruction |= sz << 8;
|
||||
|
||||
/* ARMv8.2 fp16 VCVT instruction. */
|
||||
if (flavour == neon_cvt_flavour_s32_f16
|
||||
||flavour == neon_cvt_flavour_u32_f16)
|
||||
do_scalar_fp16_v82_encode ();
|
||||
inst.instruction |= op << 7;
|
||||
inst.instruction |= rm << 16;
|
||||
inst.instruction |= 0xf0000000;
|
||||
|
|
@ -15405,6 +15513,18 @@ do_neon_cvt_1 (enum neon_cvt_mode mode)
|
|||
return;
|
||||
}
|
||||
|
||||
/* ARMv8.2 fp16 VCVT conversions. */
|
||||
if (mode == neon_cvt_mode_z
|
||||
&& ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16)
|
||||
&& (flavour == neon_cvt_flavour_s32_f16
|
||||
|| flavour == neon_cvt_flavour_u32_f16)
|
||||
&& (rs == NS_FH))
|
||||
{
|
||||
do_vfp_nsyn_cvtz ();
|
||||
do_scalar_fp16_v82_encode ();
|
||||
return;
|
||||
}
|
||||
|
||||
/* VFP rather than Neon conversions. */
|
||||
if (flavour >= neon_cvt_flavour_first_fp)
|
||||
{
|
||||
|
|
@ -15970,8 +16090,9 @@ static void
|
|||
do_neon_mov (void)
|
||||
{
|
||||
enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
|
||||
NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
|
||||
NS_NULL);
|
||||
NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR,
|
||||
NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
|
||||
NS_HR, NS_RH, NS_HI, NS_NULL);
|
||||
struct neon_type_el et;
|
||||
const char *ldconst = 0;
|
||||
|
||||
|
|
@ -16149,6 +16270,7 @@ do_neon_mov (void)
|
|||
do_vfp_nsyn_opcode ("fcpys");
|
||||
break;
|
||||
|
||||
case NS_HI:
|
||||
case NS_FI: /* case 10 (fconsts). */
|
||||
ldconst = "fconsts";
|
||||
encode_fconstd:
|
||||
|
|
@ -16156,17 +16278,29 @@ do_neon_mov (void)
|
|||
{
|
||||
inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
|
||||
do_vfp_nsyn_opcode (ldconst);
|
||||
|
||||
/* ARMv8.2 fp16 vmov.f16 instruction. */
|
||||
if (rs == NS_HI)
|
||||
do_scalar_fp16_v82_encode ();
|
||||
}
|
||||
else
|
||||
first_error (_("immediate out of range"));
|
||||
break;
|
||||
|
||||
case NS_RH:
|
||||
case NS_RF: /* case 12 (fmrs). */
|
||||
do_vfp_nsyn_opcode ("fmrs");
|
||||
/* ARMv8.2 fp16 vmov.f16 instruction. */
|
||||
if (rs == NS_RH)
|
||||
do_scalar_fp16_v82_encode ();
|
||||
break;
|
||||
|
||||
case NS_HR:
|
||||
case NS_FR: /* case 13 (fmsr). */
|
||||
do_vfp_nsyn_opcode ("fmsr");
|
||||
/* ARMv8.2 fp16 vmov.f16 instruction. */
|
||||
if (rs == NS_HR)
|
||||
do_scalar_fp16_v82_encode ();
|
||||
break;
|
||||
|
||||
/* The encoders for the fmrrs and fmsrr instructions expect three operands
|
||||
|
|
@ -16222,6 +16356,21 @@ do_neon_rshift_round_imm (void)
|
|||
et.size - imm);
|
||||
}
|
||||
|
||||
static void
|
||||
do_neon_movhf (void)
|
||||
{
|
||||
enum neon_shape rs = neon_select_shape (NS_HH, NS_NULL);
|
||||
constraint (rs != NS_HH, _("invalid suffix"));
|
||||
|
||||
constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
|
||||
_(BAD_FPU));
|
||||
|
||||
do_vfp_sp_monadic ();
|
||||
|
||||
inst.is_neon = 1;
|
||||
inst.instruction |= 0xf0000000;
|
||||
}
|
||||
|
||||
static void
|
||||
do_neon_movl (void)
|
||||
{
|
||||
|
|
@ -16398,6 +16547,10 @@ do_neon_ldr_str (void)
|
|||
do_vfp_nsyn_opcode ("flds");
|
||||
else
|
||||
do_vfp_nsyn_opcode ("fsts");
|
||||
|
||||
/* ARMv8.2 vldr.16/vstr.16 instruction. */
|
||||
if (inst.vectype.el[0].size == 16)
|
||||
do_scalar_fp16_v82_encode ();
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -16755,8 +16908,14 @@ do_vfp_nsyn_fpv8 (enum neon_shape rs)
|
|||
|
||||
NEON_ENCODE (FPV8, inst);
|
||||
|
||||
if (rs == NS_FFF)
|
||||
do_vfp_sp_dyadic ();
|
||||
if (rs == NS_FFF || rs == NS_HHH)
|
||||
{
|
||||
do_vfp_sp_dyadic ();
|
||||
|
||||
/* ARMv8.2 fp16 instruction. */
|
||||
if (rs == NS_HHH)
|
||||
do_scalar_fp16_v82_encode ();
|
||||
}
|
||||
else
|
||||
do_vfp_dp_rd_rn_rm ();
|
||||
|
||||
|
|
@ -16792,7 +16951,7 @@ do_vmaxnm (void)
|
|||
static void
|
||||
do_vrint_1 (enum neon_cvt_mode mode)
|
||||
{
|
||||
enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_QQ, NS_NULL);
|
||||
enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_QQ, NS_NULL);
|
||||
struct neon_type_el et;
|
||||
|
||||
if (rs == NS_NULL)
|
||||
|
|
@ -16804,7 +16963,8 @@ do_vrint_1 (enum neon_cvt_mode mode)
|
|||
constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
|
||||
_(BAD_FPU));
|
||||
|
||||
et = neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
|
||||
et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY
|
||||
| N_VFP);
|
||||
if (et.type != NT_invtype)
|
||||
{
|
||||
/* VFP encodings. */
|
||||
|
|
@ -16813,7 +16973,7 @@ do_vrint_1 (enum neon_cvt_mode mode)
|
|||
set_it_insn_type (OUTSIDE_IT_INSN);
|
||||
|
||||
NEON_ENCODE (FPV8, inst);
|
||||
if (rs == NS_FF)
|
||||
if (rs == NS_FF || rs == NS_HH)
|
||||
do_vfp_sp_monadic ();
|
||||
else
|
||||
do_vfp_dp_rd_rm ();
|
||||
|
|
@ -16832,6 +16992,10 @@ do_vrint_1 (enum neon_cvt_mode mode)
|
|||
|
||||
inst.instruction |= (rs == NS_DD) << 8;
|
||||
do_vfp_cond_or_thumb ();
|
||||
|
||||
/* ARMv8.2 fp16 vrint instruction. */
|
||||
if (rs == NS_HH)
|
||||
do_scalar_fp16_v82_encode ();
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -20036,6 +20200,15 @@ static const struct asm_opcode insns[] =
|
|||
NCE(vmov, 0, 1, (VMOV), neon_mov),
|
||||
NCE(vmovq, 0, 1, (VMOV), neon_mov),
|
||||
|
||||
#undef ARM_VARIANT
|
||||
#define ARM_VARIANT & arm_ext_fp16
|
||||
#undef THUMB_VARIANT
|
||||
#define THUMB_VARIANT & arm_ext_fp16
|
||||
/* New instructions added from v8.2, allowing the extraction and insertion of
|
||||
the upper 16 bits of a 32-bit vector register. */
|
||||
NCE (vmovx, eb00a40, 2, (RVS, RVS), neon_movhf),
|
||||
NCE (vins, eb00ac0, 2, (RVS, RVS), neon_movhf),
|
||||
|
||||
#undef THUMB_VARIANT
|
||||
#define THUMB_VARIANT & fpu_neon_ext_v1
|
||||
#undef ARM_VARIANT
|
||||
|
|
@ -23156,7 +23329,20 @@ md_apply_fix (fixS * fixP,
|
|||
|
||||
case BFD_RELOC_ARM_CP_OFF_IMM:
|
||||
case BFD_RELOC_ARM_T32_CP_OFF_IMM:
|
||||
if (value < -1023 || value > 1023 || (value & 3))
|
||||
if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM)
|
||||
newval = md_chars_to_number (buf, INSN_SIZE);
|
||||
else
|
||||
newval = get_thumb32_insn (buf);
|
||||
if ((newval & 0x0f200f00) == 0x0d000900)
|
||||
{
|
||||
/* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
|
||||
has permitted values that are multiples of 2, in the range 0
|
||||
to 510. */
|
||||
if (value < -510 || value > 510 || (value & 1))
|
||||
as_bad_where (fixP->fx_file, fixP->fx_line,
|
||||
_("co-processor offset out of range"));
|
||||
}
|
||||
else if (value < -1023 || value > 1023 || (value & 3))
|
||||
as_bad_where (fixP->fx_file, fixP->fx_line,
|
||||
_("co-processor offset out of range"));
|
||||
cp_off_common:
|
||||
|
|
@ -23173,6 +23359,17 @@ md_apply_fix (fixS * fixP,
|
|||
else
|
||||
{
|
||||
newval &= 0xff7fff00;
|
||||
if ((newval & 0x0f200f00) == 0x0d000900)
|
||||
{
|
||||
/* This is a fp16 vstr/vldr.
|
||||
|
||||
It requires the immediate offset in the instruction is shifted
|
||||
left by 1 to be a half-word offset.
|
||||
|
||||
Here, left shift by 1 first, and later right shift by 2
|
||||
should get the right offset. */
|
||||
value <<= 1;
|
||||
}
|
||||
newval |= (value >> 2) | (sign ? INDEX_UP : 0);
|
||||
}
|
||||
if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
|
||||
|
|
|
|||
|
|
@ -0,0 +1,4 @@
|
|||
#name: Invalid armv8.2-a scalar fp16
|
||||
#source: armv8-2-fp16-scalar-bad.s
|
||||
#as: -march=armv8.2-a+fp16 -mfpu=fp-armv8
|
||||
#error-output: armv8-2-fp16-scalar-bad.l
|
||||
|
|
@ -0,0 +1,206 @@
|
|||
.*: Assembler messages:
|
||||
.*:73: Error: immediate value out of range -- `vcvt.s32.f16 s11,s11,#33'
|
||||
.*:74: Error: immediate value out of range, expected range \[1, 32\] -- `vcvt.u32.f16 s11,s11,#0'
|
||||
.*:75: Error: immediate value out of range -- `vcvt.f16.s32 s12,s12,#34'
|
||||
.*:76: Error: immediate value out of range -- `vcvt.f16.u32 s12,s12,#-1'
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:80: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:80: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:80: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:80: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:80: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:80: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:80: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:80: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:80: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:80: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:80: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:80: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:80: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:80: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:80: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:80: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:80: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:80: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:80: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:80: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:80: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:80: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:80: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:80: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:81: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:81: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:81: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:81: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:81: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:81: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:81: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:81: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:81: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:81: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:81: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:81: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:82: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:82: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:82: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:82: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:82: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:82: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:82: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:82: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:82: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:82: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:82: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:82: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:83: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:83: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:83: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:83: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:83: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:83: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:83: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:83: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:83: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:83: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:83: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:83: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:83: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:83: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:83: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:83: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:83: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:83: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:83: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:83: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:83: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:83: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:83: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:83: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:84: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:84: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:84: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:84: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:84: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:84: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:84: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:84: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:84: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:84: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:84: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:84: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:84: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:84: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:84: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:84: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:84: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:84: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:84: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:84: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:84: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:84: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:84: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:84: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:85: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:85: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:85: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:85: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:85: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:85: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:85: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:85: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:85: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:85: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:85: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:85: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:86: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:86: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:86: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:86: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:86: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:86: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:86: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:86: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:86: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:86: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:86: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:86: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:86: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:86: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:86: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:86: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:86: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:86: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
|
||||
.*:68: Error: co-processor offset out of range
|
||||
.*:69: Error: co-processor offset out of range
|
||||
.*:70: Error: co-processor offset out of range
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
.macro f16_sss_arithmetic reg0, reg1, reg2
|
||||
.irp op, vdiv, vfma, vfms, vfnma, vfnms, vmla, vmls, vmul, vnmla, vnmls, vnmul, vsub
|
||||
.irp cond, eq.f16, ne.f16, ge.f16, lt.f16, gt.f16, le.f16
|
||||
\op\cond s\reg0, s\reg1, s\reg2
|
||||
.endr
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.macro f16_ss_arithmetic reg0, reg1
|
||||
.irp op, vabs, vadd, vsqrt, vneg
|
||||
.irp cond, eq.f16, ne.f16, ge.f16, lt.f16, gt.f16, le.f16
|
||||
\op\cond s\reg0, s\reg1
|
||||
.endr
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.macro f16_si_cmp reg0, imm
|
||||
.irp op, vcmp, vcmpe
|
||||
.irp cond, eq.f16, ne.f16, ge.f16, lt.f16, gt.f16, le.f16
|
||||
\op\cond s\reg0, \imm
|
||||
.endr
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.macro f16_ss_cmp reg0, reg1
|
||||
.irp op, vcmp, vcmpe
|
||||
.irp cond, eq.f16, ne.f16, ge.f16, lt.f16, gt.f16, le.f16
|
||||
\op\cond s\reg0, s\reg1
|
||||
.endr
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.macro f16_ss_cvt reg0, reg1
|
||||
.irp cond, eq, ne, ge, lt, gt, le
|
||||
.irp mode, .s32.f16, .u32.f16, .f16.s32, .f16.u32
|
||||
vcvt\cond\mode s\reg0, s\reg1
|
||||
.endr
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.macro f16_ssi_cvt_imm32 reg0, reg1, imm
|
||||
.irp cond, eq, ne, ge, lt, gt, le
|
||||
.irp mode, .s32.f16, .u32.f16, .f16.s32, .f16.u32
|
||||
vcvt\cond\mode s\reg0, s\reg1, \imm
|
||||
.endr
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.macro f16_ss_cvt_r reg0, reg1
|
||||
.irp cond, eq, ne, ge, lt, gt, le
|
||||
.irp mode, .s32.f16, .u32.f16
|
||||
vcvtr\cond\mode s\reg0, s\reg1
|
||||
.endr
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.macro f16_ss_vrint reg0, reg1
|
||||
.irp op, vrintr, vrintx, vrintz
|
||||
.irp cond, eq.f16, ne.f16, ge.f16, lt.f16, gt.f16, le.f16
|
||||
\op\cond s\reg0, s\reg1
|
||||
.endr
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.text
|
||||
|
||||
@ invalied immediate range
|
||||
vldr.16 s6, [pc, #-511]
|
||||
vldr.16 s6, [pc, #111]
|
||||
vldr.16 s3, [pc, #511]
|
||||
|
||||
@ invalid immediate range
|
||||
vcvt.s32.f16 s11, s11, #33
|
||||
vcvt.u32.f16 s11, s11, #0
|
||||
vcvt.f16.s32 s12, s12, #34
|
||||
vcvt.f16.u32 s12, s12, #-1
|
||||
|
||||
@ armv8.2 fp16 scalar instruction cannot be conditional
|
||||
f16_sss_arithmetic 0, 1, 2
|
||||
f16_ss_arithmetic 0, 1
|
||||
f16_si_cmp 2, #0.0
|
||||
f16_ss_cmp 0, 1
|
||||
f16_ss_cvt 1, 8
|
||||
f16_ssi_cvt_imm32 2, 2, #29
|
||||
f16_ss_cvt_r 0, 10
|
||||
f16_ss_vrint 3, 11
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
#name: ARM v8.2 FP16 support on scalar (Thumb)
|
||||
#source: armv8-2-fp16-scalar.s
|
||||
#objdump: -d
|
||||
#as: -march=armv8.2-a+fp16 -mfpu=fp-armv8 -mthumb
|
||||
#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
|
||||
|
||||
.*: +file format .*arm.*
|
||||
Disassembly of section .text:
|
||||
|
||||
00000000 <label-0xc>:
|
||||
0: ee00 1910 vmov.f16 s0, r1
|
||||
4: ee10 0990 vmov.f16 r0, s1
|
||||
8: eeb0 0900 vmov.f16 s0, #0 ; 0x40000000 2.0
|
||||
|
||||
0000000c <label>:
|
||||
c: 00000ffe .word 0x00000ffe
|
||||
10: ed5f 1904 vldr.16 s3, \[pc, #-8\] ; c <label>
|
||||
14: ed1f 3902 vldr.16 s6, \[pc, #-4\] ; 14 <label\+0x8>
|
||||
18: eddf 1902 vldr.16 s3, \[pc, #4\] ; 20 <label\+0x14>
|
||||
1c: edd0 0902 vldr.16 s1, \[r0, #4\]
|
||||
20: ed10 1902 vldr.16 s2, \[r0, #-4\]
|
||||
24: ed80 3902 vstr.16 s6, \[r0, #4\]
|
||||
28: ed40 5902 vstr.16 s11, \[r0, #-4\]
|
||||
2c: eec6 298c vdiv.f16 s5, s13, s24
|
||||
30: eee6 298c vfma.f16 s5, s13, s24
|
||||
34: eee6 29cc vfms.f16 s5, s13, s24
|
||||
38: eed6 29cc vfnma.f16 s5, s13, s24
|
||||
3c: eed6 298c vfnms.f16 s5, s13, s24
|
||||
40: fec6 298c vmaxnm.f16 s5, s13, s24
|
||||
44: fec6 29cc vminnm.f16 s5, s13, s24
|
||||
48: ee46 298c vmla.f16 s5, s13, s24
|
||||
4c: ee46 29cc vmls.f16 s5, s13, s24
|
||||
50: ee66 298c vmul.f16 s5, s13, s24
|
||||
54: ee56 29cc vnmla.f16 s5, s13, s24
|
||||
58: ee56 298c vnmls.f16 s5, s13, s24
|
||||
5c: ee66 29cc vnmul.f16 s5, s13, s24
|
||||
60: ee76 29cc vsub.f16 s5, s13, s24
|
||||
64: eef0 29c6 vabs.f16 s5, s12
|
||||
68: ee72 2986 vadd.f16 s5, s5, s12
|
||||
6c: eef1 29c6 vsqrt.f16 s5, s12
|
||||
70: eef1 2946 vneg.f16 s5, s12
|
||||
74: eeb5 1940 vcmp.f16 s2, #0.0
|
||||
78: eeb5 19c0 vcmpe.f16 s2, #0.0
|
||||
7c: eef4 2966 vcmp.f16 s5, s13
|
||||
80: eef4 29e6 vcmpe.f16 s5, s13
|
||||
84: fe46 29ab vseleq.f16 s5, s13, s23
|
||||
88: fe66 29ab vselge.f16 s5, s13, s23
|
||||
8c: fe56 29ab vselvs.f16 s5, s13, s23
|
||||
90: eefd 19c4 vcvt.s32.f16 s3, s8
|
||||
94: eefc 19c4 vcvt.u32.f16 s3, s8
|
||||
98: eef8 19c4 vcvt.f16.s32 s3, s8
|
||||
9c: eef8 1944 vcvt.f16.u32 s3, s8
|
||||
a0: eefa 39e1 vcvt.f16.s32 s7, s7, #29
|
||||
a4: eefb 39e1 vcvt.f16.u32 s7, s7, #29
|
||||
a8: eefe 39e1 vcvt.s32.f16 s7, s7, #29
|
||||
ac: eeff 39e1 vcvt.u32.f16 s7, s7, #29
|
||||
b0: fefc 29c5 vcvta.s32.f16 s5, s10
|
||||
b4: fefc 2945 vcvta.u32.f16 s5, s10
|
||||
b8: feff 29c5 vcvtm.s32.f16 s5, s10
|
||||
bc: feff 2945 vcvtm.u32.f16 s5, s10
|
||||
c0: fefd 29c5 vcvtn.s32.f16 s5, s10
|
||||
c4: fefd 2945 vcvtn.u32.f16 s5, s10
|
||||
c8: fefe 29c5 vcvtp.s32.f16 s5, s10
|
||||
cc: fefe 2945 vcvtp.u32.f16 s5, s10
|
||||
d0: eefc 2945 vcvtr.u32.f16 s5, s10
|
||||
d4: eefd 2945 vcvtr.s32.f16 s5, s10
|
||||
d8: fef8 1965 vrinta.f16 s3, s11
|
||||
dc: fefb 1965 vrintm.f16 s3, s11
|
||||
e0: fef9 1965 vrintn.f16 s3, s11
|
||||
e4: fefa 1965 vrintp.f16 s3, s11
|
||||
e8: eef6 1965 vrintr.f16 s3, s11
|
||||
ec: eef7 1965 vrintx.f16 s3, s11
|
||||
f0: eef6 19e5 vrintz.f16 s3, s11
|
||||
f4: fef0 2ae4 vins.f16 s5, s9
|
||||
f8: fef0 2a64 vmovx.f16 s5, s9
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
#name: ARM v8.2 FP16 support on scalar
|
||||
#source: armv8-2-fp16-scalar.s
|
||||
#objdump: -d
|
||||
#as: -march=armv8.2-a+fp16 -mfpu=fp-armv8
|
||||
#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
|
||||
|
||||
.*: +file format .*arm.*
|
||||
Disassembly of section .text:
|
||||
|
||||
00000000 <label-0xc>:
|
||||
0: ee001910 vmov.f16 s0, r1
|
||||
4: ee100990 vmov.f16 r0, s1
|
||||
8: eeb00900 vmov.f16 s0, #0 ; 0x40000000 2.0
|
||||
|
||||
0000000c <label>:
|
||||
c: 00000ffe .word 0x00000ffe
|
||||
10: ed5f1906 vldr.16 s3, \[pc, #-12\] ; c <label>
|
||||
14: ed1f3902 vldr.16 s6, \[pc, #-4\] ; 18 <label\+0xc>
|
||||
18: eddf1902 vldr.16 s3, \[pc, #4\] ; 24 <label\+0x18>
|
||||
1c: edd00902 vldr.16 s1, \[r0, #4\]
|
||||
20: ed101902 vldr.16 s2, \[r0, #-4\]
|
||||
24: ed803902 vstr.16 s6, \[r0, #4\]
|
||||
28: ed405902 vstr.16 s11, \[r0, #-4\]
|
||||
2c: eec6298c vdiv.f16 s5, s13, s24
|
||||
30: eee6298c vfma.f16 s5, s13, s24
|
||||
34: eee629cc vfms.f16 s5, s13, s24
|
||||
38: eed629cc vfnma.f16 s5, s13, s24
|
||||
3c: eed6298c vfnms.f16 s5, s13, s24
|
||||
40: fec6298c vmaxnm.f16 s5, s13, s24
|
||||
44: fec629cc vminnm.f16 s5, s13, s24
|
||||
48: ee46298c vmla.f16 s5, s13, s24
|
||||
4c: ee4629cc vmls.f16 s5, s13, s24
|
||||
50: ee66298c vmul.f16 s5, s13, s24
|
||||
54: ee5629cc vnmla.f16 s5, s13, s24
|
||||
58: ee56298c vnmls.f16 s5, s13, s24
|
||||
5c: ee6629cc vnmul.f16 s5, s13, s24
|
||||
60: ee7629cc vsub.f16 s5, s13, s24
|
||||
64: eef029c6 vabs.f16 s5, s12
|
||||
68: ee722986 vadd.f16 s5, s5, s12
|
||||
6c: eef129c6 vsqrt.f16 s5, s12
|
||||
70: eef12946 vneg.f16 s5, s12
|
||||
74: eeb51940 vcmp.f16 s2, #0.0
|
||||
78: eeb519c0 vcmpe.f16 s2, #0.0
|
||||
7c: eef42966 vcmp.f16 s5, s13
|
||||
80: eef429e6 vcmpe.f16 s5, s13
|
||||
84: fe4629ab vseleq.f16 s5, s13, s23
|
||||
88: fe6629ab vselge.f16 s5, s13, s23
|
||||
8c: fe5629ab vselvs.f16 s5, s13, s23
|
||||
90: eefd19c4 vcvt.s32.f16 s3, s8
|
||||
94: eefc19c4 vcvt.u32.f16 s3, s8
|
||||
98: eef819c4 vcvt.f16.s32 s3, s8
|
||||
9c: eef81944 vcvt.f16.u32 s3, s8
|
||||
a0: eefa39e1 vcvt.f16.s32 s7, s7, #29
|
||||
a4: eefb39e1 vcvt.f16.u32 s7, s7, #29
|
||||
a8: eefe39e1 vcvt.s32.f16 s7, s7, #29
|
||||
ac: eeff39e1 vcvt.u32.f16 s7, s7, #29
|
||||
b0: fefc29c5 vcvta.s32.f16 s5, s10
|
||||
b4: fefc2945 vcvta.u32.f16 s5, s10
|
||||
b8: feff29c5 vcvtm.s32.f16 s5, s10
|
||||
bc: feff2945 vcvtm.u32.f16 s5, s10
|
||||
c0: fefd29c5 vcvtn.s32.f16 s5, s10
|
||||
c4: fefd2945 vcvtn.u32.f16 s5, s10
|
||||
c8: fefe29c5 vcvtp.s32.f16 s5, s10
|
||||
cc: fefe2945 vcvtp.u32.f16 s5, s10
|
||||
d0: eefc2945 vcvtr.u32.f16 s5, s10
|
||||
d4: eefd2945 vcvtr.s32.f16 s5, s10
|
||||
d8: fef81965 vrinta.f16 s3, s11
|
||||
dc: fefb1965 vrintm.f16 s3, s11
|
||||
e0: fef91965 vrintn.f16 s3, s11
|
||||
e4: fefa1965 vrintp.f16 s3, s11
|
||||
e8: eef61965 vrintr.f16 s3, s11
|
||||
ec: eef71965 vrintx.f16 s3, s11
|
||||
f0: eef619e5 vrintz.f16 s3, s11
|
||||
f4: fef02ae4 vins.f16 s5, s9
|
||||
f8: fef02a64 vmovx.f16 s5, s9
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
.macro f16_sss_arithmetic reg0, reg1, reg2
|
||||
.irp op, vdiv.f16, vfma.f16, vfms.f16, vfnma.f16, vfnms.f16, vmaxnm.f16, vminnm.f16, vmla.f16, vmls.f16, vmul.f16, vnmla.f16, vnmls.f16, vnmul.f16, vsub.f16
|
||||
\op s\reg0, s\reg1, s\reg2
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.macro f16_ss_arithmetic reg0, reg1
|
||||
.irp op, vabs.f16, vadd.f16, vsqrt.f16, vneg.f16
|
||||
\op s\reg0, s\reg1
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.macro f16_si_cmp reg0, imm
|
||||
.irp op, vcmp.f16, vcmpe.f16
|
||||
\op s\reg0, \imm
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.macro f16_ss_cmp reg0, reg1
|
||||
.irp op, vcmp.f16, vcmpe.f16
|
||||
\op s\reg0, s\reg1
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.macro f16_sss_vsel reg0, reg1, reg2
|
||||
.irp op, vseleq.f16 vselge.f16, vselvs.f16
|
||||
\op s\reg0, s\reg1, s\reg2
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.macro f16_ss_cvt reg0, reg1
|
||||
.irp op, vcvt.s32.f16, vcvt.u32.f16, vcvt.f16.s32, vcvt.f16.u32
|
||||
\op s\reg0, s\reg1
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.macro f16_ssi_cvt_imm32 reg0, reg1, imm
|
||||
.irp op, vcvt.f16.s32, vcvt.f16.u32, vcvt.s32.f16, vcvt.u32.f16
|
||||
\op s\reg0, s\reg1, \imm
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.macro f16_ss_cvt_amnpr reg0, reg1
|
||||
.irp op, vcvta.s32.f16, vcvta.u32.f16, vcvtm.s32.f16, vcvtm.u32.f16, vcvtn.s32.f16, vcvtn.u32.f16, vcvtp.s32.f16, vcvtp.u32.f16, vcvtr.u32.f16, vcvtr.s32.f16
|
||||
\op s\reg0, s\reg1
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.macro f16_ss_vrint reg0, reg1
|
||||
.irp op, vrinta.f16, vrintm.f16, vrintn.f16, vrintp.f16, vrintr.f16, vrintx.f16, vrintz.f16
|
||||
\op s\reg0, s\reg1
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.macro f16_ss_mov reg0, reg1
|
||||
.irp op, vins.f16, vmovx.f16
|
||||
\op s\reg0, s\reg1
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.text
|
||||
|
||||
vmov.f16 s0, r1
|
||||
vmov.f16 r0, s1
|
||||
vmov.f16 s0, #2.0
|
||||
label:
|
||||
.word 0xffe
|
||||
vldr.16 s3, label
|
||||
|
||||
vldr.16 s6, [pc, #-4]
|
||||
vldr.16 s3, [pc, #4]
|
||||
vldr.16 s1, [r0, #4]
|
||||
vldr.16 s2, [r0, #-4]
|
||||
vstr.16 s6 , [r0, #4]
|
||||
vstr.16 s11 , [r0, #-4]
|
||||
|
||||
f16_sss_arithmetic 5, 13, 24
|
||||
f16_ss_arithmetic 5, 12
|
||||
f16_si_cmp 2, #0.0
|
||||
f16_ss_cmp 5, 13
|
||||
f16_sss_vsel 5, 13, 23
|
||||
f16_ss_cvt 3, 8
|
||||
f16_ssi_cvt_imm32 7, 7, #29
|
||||
f16_ss_cvt_amnpr 5, 10
|
||||
f16_ss_vrint 3, 11
|
||||
f16_ss_mov 5, 9
|
||||
Loading…
Reference in New Issue