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[AArch64][Patch 4/5] Support HINT aliases taking operands. 

The Statistical Profile Extension adds the instruction PSB CSYNC as an
alias for the HINT #17 instruction. This patch adds support for aliases
of HINT which take an operand, adding a table to store operand names and
their matching hint number as well as encoding and decoding functions
for such operands. Parsing and printing the operands are deferred to any
support added for aliases with such operands.

include/opcode/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (aarch64_hint_options): Declare.
	(aarch64_opnd_info): Add field hint_option.

opcodes/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm.c (aarch64_ins_hint): New.
	* aarch64-asm.h (aarch64_ins_hint): Declare.
	* aarch64-dis.c (aarch64_ext_hint): New.
	* aarch64-dis.h (aarch64_ext_hint): Declare.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-opc.c (aarch64_hint_options): New.
	* aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.

Change-Id: I2205038fc1c47d3025d1f0bc2fbf405b5575b287
This commit is contained in:
Matthew Wahab 2015-12-11 10:11:27 +00:00
parent a0f7013add
commit 9ed608f98b
10 changed files with 75 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
include/opcode/ChangeLog
View File

@ -1,3 +1,8 @@
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (aarch64_hint_options): Declare.
(aarch64_opnd_info): Add field hint_option.
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (AARCH64_FEATURE_PROFILE): New.

2
include/opcode/aarch64.h
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@ -653,6 +653,7 @@ struct aarch64_name_value_pair
extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
extern const struct aarch64_name_value_pair aarch64_prfops [32];
extern const struct aarch64_name_value_pair aarch64_hint_options [];
typedef struct
{
@ -786,6 +787,7 @@ struct aarch64_opnd_info
aarch64_insn pstatefield;
const aarch64_sys_ins_reg *sysins_op;
const struct aarch64_name_value_pair *barrier;
const struct aarch64_name_value_pair *hint_option;
const struct aarch64_name_value_pair *prfop;
};

10
opcodes/ChangeLog
View File

@ -1,3 +1,13 @@
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm.c (aarch64_ins_hint): New.
* aarch64-asm.h (aarch64_ins_hint): Declare.
* aarch64-dis.c (aarch64_ext_hint): New.
* aarch64-dis.h (aarch64_ext_hint): Declare.
* aarch64-opc-2.c: Regenerate.
* aarch64-opc.c (aarch64_hint_options): New.
* aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.

13
opcodes/aarch64-asm.c
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@ -667,6 +667,19 @@ aarch64_ins_prfop (const aarch64_operand *self ATTRIBUTE_UNUSED,
return NULL;
}
/* Encode the hint number for instructions that alias HINT but take an
operand. */
const char *
aarch64_ins_hint (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED)
{
/* CRm:op2. */
insert_fields (code, info->hint_option->value, 0, 2, FLD_op2, FLD_CRm);
return NULL;
}
/* Encode the extended register operand for e.g.
STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
const char *

1
opcodes/aarch64-asm.h
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@ -64,6 +64,7 @@ AARCH64_DECL_OPD_INSERTER (ins_sysreg);
AARCH64_DECL_OPD_INSERTER (ins_pstatefield);
AARCH64_DECL_OPD_INSERTER (ins_sysins_op);
AARCH64_DECL_OPD_INSERTER (ins_barrier);
AARCH64_DECL_OPD_INSERTER (ins_hint);
AARCH64_DECL_OPD_INSERTER (ins_prfop);
AARCH64_DECL_OPD_INSERTER (ins_reg_extended);
AARCH64_DECL_OPD_INSERTER (ins_reg_shifted);

27
opcodes/aarch64-dis.c
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@ -1067,6 +1067,33 @@ aarch64_ext_prfop (const aarch64_operand *self ATTRIBUTE_UNUSED,
return 1;
}
/* Decode the hint number for an alias taking an operand. Set info->hint_option
to the matching name/value pair in aarch64_hint_options. */
int
aarch64_ext_hint (const aarch64_operand *self ATTRIBUTE_UNUSED,
aarch64_opnd_info *info,
aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED)
{
/* CRm:op2. */
unsigned hint_number;
int i;
hint_number = extract_fields (code, 0, 2, FLD_CRm, FLD_op2);
for (i = 0; aarch64_hint_options[i].name != NULL; i++)
{
if (hint_number == aarch64_hint_options[i].value)
{
info->hint_option = &(aarch64_hint_options[i]);
return 1;
}
}
return 0;
}
/* Decode the extended register operand for e.g.
STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
int

1
opcodes/aarch64-dis.h
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@ -86,6 +86,7 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_sysreg);
AARCH64_DECL_OPD_EXTRACTOR (ext_pstatefield);
AARCH64_DECL_OPD_EXTRACTOR (ext_sysins_op);
AARCH64_DECL_OPD_EXTRACTOR (ext_barrier);
AARCH64_DECL_OPD_EXTRACTOR (ext_hint);
AARCH64_DECL_OPD_EXTRACTOR (ext_prfop);
AARCH64_DECL_OPD_EXTRACTOR (ext_reg_extended);
AARCH64_DECL_OPD_EXTRACTOR (ext_reg_shifted);

4
opcodes/aarch64-opc-2.c
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@ -107,11 +107,11 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_SYSTEM, "PSTATEFIELD", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a PSTATE field name"},
{AARCH64_OPND_CLASS_SYSTEM, "SYSREG_AT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address translation operation specifier"},
{AARCH64_OPND_CLASS_SYSTEM, "SYSREG_DC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a data cache maintenance operation specifier"},
{AARCH64_OPND_CLASS_SYSTEM, "SYSREG_IC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an instructin cache maintenance operation specifier"},
{AARCH64_OPND_CLASS_SYSTEM, "SYSREG_IC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an instruction cache maintenance operation specifier"},
{AARCH64_OPND_CLASS_SYSTEM, "SYSREG_TLBI", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a TBL invalidation operation specifier"},
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a barrier option name"},
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER_ISB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the ISB option name SY or an optional 4-bit unsigned immediate"},
{AARCH64_OPND_CLASS_SYSTEM, "PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an prefetch operation specifier"},
{AARCH64_OPND_CLASS_SYSTEM, "PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a prefetch operation specifier"},
{AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"},
};

12
opcodes/aarch64-opc.c
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@ -335,6 +335,18 @@ const struct aarch64_name_value_pair aarch64_barrier_options[16] =
{ "sy", 0xf },
};
/* Table describing the operands supported by the aliases of the HINT
instruction.
The name column is the operand that is accepted for the alias. The value
column is the hint number of the alias. The list of operands is terminated
by NULL in the name column. */
const struct aarch64_name_value_pair aarch64_hint_options[] =
{
{ NULL, 0x0 },
};
/* op -> op: load = 0 instruction = 1 store = 2
l -> level: 1-3
t -> temporal: temporal (retained) = 0 non-temporal (streaming) = 1 */

4
opcodes/aarch64-tbl.h
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@ -2654,7 +2654,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
Y(SYSTEM, sysins_op, "SYSREG_DC", 0, F(), \
"a data cache maintenance operation specifier") \
Y(SYSTEM, sysins_op, "SYSREG_IC", 0, F(), \
"an instructin cache maintenance operation specifier") \
"an instruction cache maintenance operation specifier") \
Y(SYSTEM, sysins_op, "SYSREG_TLBI", 0, F(), \
"a TBL invalidation operation specifier") \
Y(SYSTEM, barrier, "BARRIER", 0, F(), \
@ -2662,4 +2662,4 @@ struct aarch64_opcode aarch64_opcode_table[] =
Y(SYSTEM, barrier, "BARRIER_ISB", 0, F(), \
"the ISB option name SY or an optional 4-bit unsigned immediate") \
Y(SYSTEM, prfop, "PRFOP", 0, F(), \
"an prefetch operation specifier")
"a prefetch operation specifier")