From 9f79e88693dae859f838bcf684158e6e6f8f3b6b Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Thu, 22 Mar 2018 08:32:50 +0100 Subject: [PATCH] x86: fix swapped operand handling for BNDMOV The wrong placement of the Load attribute in the templates prevented this from working. The disassembler also didn't handle this consistently with other similar dual-encoding insns. --- gas/ChangeLog | 7 +++++++ gas/testsuite/gas/i386/opts-intel.d | 4 ++++ gas/testsuite/gas/i386/opts.d | 4 ++++ gas/testsuite/gas/i386/opts.s | 8 ++++++++ gas/testsuite/gas/i386/sse2avx-opts-intel.d | 4 ++++ gas/testsuite/gas/i386/sse2avx-opts.d | 4 ++++ opcodes/ChangeLog | 8 ++++++++ opcodes/i386-dis.c | 14 +++++++++++--- opcodes/i386-opc.tbl | 4 ++-- opcodes/i386-tbl.h | 4 ++-- 10 files changed, 54 insertions(+), 7 deletions(-) diff --git a/gas/ChangeLog b/gas/ChangeLog index 00a4edc39a..6abb853234 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,10 @@ +2018-03-22 Jan Beulich + + * testsuite/gas/i386/opts.s: Add bndmov cases. + * testsuite/gas/i386/opts.d, testsuite/gas/i386/opts-intel.d, + testsuite/gas/i386/sse2avx-opts.d, + testsuite/gas/i386/sse2avx-opts-intel.d: Adjust expectations. + 2018-03-22 Jan Beulich * config/tc-i386.c (match_mem_size): Extend sub-xmmword diff --git a/gas/testsuite/gas/i386/opts-intel.d b/gas/testsuite/gas/i386/opts-intel.d index 9913c82aa0..4c546eeda3 100644 --- a/gas/testsuite/gas/i386/opts-intel.d +++ b/gas/testsuite/gas/i386/opts-intel.d @@ -166,6 +166,8 @@ Disassembly of section .text: [ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s xmm2,xmm6,xmm4 [ ]*[a-f0-9]+: 0f 6f e0 movq mm4,mm0 [ ]*[a-f0-9]+: 0f 7f c4 movq.s mm4,mm0 +[ ]*[a-f0-9]+: 66 0f 1a d1 bndmov bnd2,bnd1 +[ ]*[a-f0-9]+: 66 0f 1b ca bndmov.s bnd2,bnd1 [ ]*[a-f0-9]+: 00 d1 add cl,dl [ ]*[a-f0-9]+: 02 ca add.s cl,dl [ ]*[a-f0-9]+: 66 01 d1 add cx,dx @@ -270,4 +272,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s xmm2,xmm6,xmm4 [ ]*[a-f0-9]+: 0f 6f e0 movq mm4,mm0 [ ]*[a-f0-9]+: 0f 7f c4 movq.s mm4,mm0 +[ ]*[a-f0-9]+: 66 0f 1a ca bndmov bnd1,bnd2 +[ ]*[a-f0-9]+: 66 0f 1b d1 bndmov.s bnd1,bnd2 #pass diff --git a/gas/testsuite/gas/i386/opts.d b/gas/testsuite/gas/i386/opts.d index 4dc385ac78..af6cdf06cd 100644 --- a/gas/testsuite/gas/i386/opts.d +++ b/gas/testsuite/gas/i386/opts.d @@ -165,6 +165,8 @@ Disassembly of section .text: [ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s %xmm4,%xmm6,%xmm2 [ ]*[a-f0-9]+: 0f 6f e0 movq %mm0,%mm4 [ ]*[a-f0-9]+: 0f 7f c4 movq.s %mm0,%mm4 +[ ]*[a-f0-9]+: 66 0f 1a d1 bndmov %bnd1,%bnd2 +[ ]*[a-f0-9]+: 66 0f 1b ca bndmov.s %bnd1,%bnd2 [ ]*[a-f0-9]+: 00 d1 addb %dl,%cl [ ]*[a-f0-9]+: 02 ca addb.s %dl,%cl [ ]*[a-f0-9]+: 66 01 d1 addw %dx,%cx @@ -269,4 +271,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s %xmm4,%xmm6,%xmm2 [ ]*[a-f0-9]+: 0f 6f e0 movq %mm0,%mm4 [ ]*[a-f0-9]+: 0f 7f c4 movq.s %mm0,%mm4 +[ ]*[a-f0-9]+: 66 0f 1a ca bndmov %bnd2,%bnd1 +[ ]*[a-f0-9]+: 66 0f 1b d1 bndmov.s %bnd2,%bnd1 #pass diff --git a/gas/testsuite/gas/i386/opts.s b/gas/testsuite/gas/i386/opts.s index 4bd8e2c2f0..262ce1cbaf 100644 --- a/gas/testsuite/gas/i386/opts.s +++ b/gas/testsuite/gas/i386/opts.s @@ -172,6 +172,10 @@ _start: movq %mm0,%mm4 movq.s %mm0,%mm4 +# Tests for op bnd, bnd + bndmov %bnd1,%bnd2 + bndmov.s %bnd1,%bnd2 + .intel_syntax noprefix # Tests for op reg, reg @@ -287,3 +291,7 @@ _start: # Tests for op mm, mm movq mm4,mm0 movq.s mm4,mm0 + +# Tests for op bnd, bnd + bndmov bnd1,bnd2 + bndmov.s bnd1,bnd2 diff --git a/gas/testsuite/gas/i386/sse2avx-opts-intel.d b/gas/testsuite/gas/i386/sse2avx-opts-intel.d index 392e252c08..3e48cf83a4 100644 --- a/gas/testsuite/gas/i386/sse2avx-opts-intel.d +++ b/gas/testsuite/gas/i386/sse2avx-opts-intel.d @@ -167,6 +167,8 @@ Disassembly of section .text: [ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s xmm2,xmm6,xmm4 [ ]*[a-f0-9]+: 0f 6f e0 movq mm4,mm0 [ ]*[a-f0-9]+: 0f 7f c4 movq.s mm4,mm0 +[ ]*[a-f0-9]+: 66 0f 1a d1 bndmov bnd2,bnd1 +[ ]*[a-f0-9]+: 66 0f 1b ca bndmov.s bnd2,bnd1 [ ]*[a-f0-9]+: 00 d1 add cl,dl [ ]*[a-f0-9]+: 02 ca add.s cl,dl [ ]*[a-f0-9]+: 66 01 d1 add cx,dx @@ -271,4 +273,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s xmm2,xmm6,xmm4 [ ]*[a-f0-9]+: 0f 6f e0 movq mm4,mm0 [ ]*[a-f0-9]+: 0f 7f c4 movq.s mm4,mm0 +[ ]*[a-f0-9]+: 66 0f 1a ca bndmov bnd1,bnd2 +[ ]*[a-f0-9]+: 66 0f 1b d1 bndmov.s bnd1,bnd2 #pass diff --git a/gas/testsuite/gas/i386/sse2avx-opts.d b/gas/testsuite/gas/i386/sse2avx-opts.d index bfeaa7b21b..c0524b78aa 100644 --- a/gas/testsuite/gas/i386/sse2avx-opts.d +++ b/gas/testsuite/gas/i386/sse2avx-opts.d @@ -167,6 +167,8 @@ Disassembly of section .text: [ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s %xmm4,%xmm6,%xmm2 [ ]*[a-f0-9]+: 0f 6f e0 movq %mm0,%mm4 [ ]*[a-f0-9]+: 0f 7f c4 movq.s %mm0,%mm4 +[ ]*[a-f0-9]+: 66 0f 1a d1 bndmov %bnd1,%bnd2 +[ ]*[a-f0-9]+: 66 0f 1b ca bndmov.s %bnd1,%bnd2 [ ]*[a-f0-9]+: 00 d1 addb %dl,%cl [ ]*[a-f0-9]+: 02 ca addb.s %dl,%cl [ ]*[a-f0-9]+: 66 01 d1 addw %dx,%cx @@ -271,4 +273,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s %xmm4,%xmm6,%xmm2 [ ]*[a-f0-9]+: 0f 6f e0 movq %mm0,%mm4 [ ]*[a-f0-9]+: 0f 7f c4 movq.s %mm0,%mm4 +[ ]*[a-f0-9]+: 66 0f 1a ca bndmov %bnd2,%bnd1 +[ ]*[a-f0-9]+: 66 0f 1b d1 bndmov.s %bnd2,%bnd1 #pass diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index c33e5a0047..9f85ce656b 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,11 @@ +2018-03-22 Jan Beulich + + * i386-dis.c (EbndS, bnd_swap_mode): New. + (prefix_table): Use EbndS. + (OP_E_register, OP_E_memory): Also handle bnd_swap_mode. + * i386-opc.tbl (bndmov): Move misplaced Load. + * i386-tlb.h: Re-generate. + 2018-03-22 Jan Beulich * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index be2fd8abc9..d8a6db3ee8 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -248,6 +248,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define Eb { OP_E, b_mode } #define Ebnd { OP_E, bnd_mode } #define EbS { OP_E, b_swap_mode } +#define EbndS { OP_E, bnd_swap_mode } #define Ev { OP_E, v_mode } #define Ev_bnd { OP_E, v_bnd_mode } #define EvS { OP_E, v_swap_mode } @@ -560,7 +561,10 @@ enum dq_mode, /* registers like dq_mode, memory like w_mode. */ dqw_mode, + /* bounds operand */ bnd_mode, + /* bounds operand with operand swapped */ + bnd_swap_mode, /* 4- or 6-byte pointer operand */ f_mode, const_1_mode, @@ -3890,7 +3894,7 @@ static const struct dis386 prefix_table[][4] = { { { MOD_TABLE (MOD_0F1B_PREFIX_0) }, { MOD_TABLE (MOD_0F1B_PREFIX_1) }, - { "bndmov", { Ebnd, Gbnd }, 0 }, + { "bndmov", { EbndS, Gbnd }, 0 }, { "bndcn", { Gbnd, Ev_bnd }, 0 }, }, @@ -15047,6 +15051,7 @@ OP_E_register (int bytemode, int sizeflag) if ((sizeflag & SUFFIX_ALWAYS) && (bytemode == b_swap_mode + || bytemode == bnd_swap_mode || bytemode == v_swap_mode)) swap_operand (); @@ -15076,6 +15081,7 @@ OP_E_register (int bytemode, int sizeflag) names = address_mode == mode_64bit ? names64 : names32; break; case bnd_mode: + case bnd_swap_mode: if (reg > 0x3) { oappend ("(bad)"); @@ -15272,7 +15278,8 @@ OP_E_memory (int bytemode, int sizeflag) int scale = 0; int addr32flag = !((sizeflag & AFLAG) || bytemode == v_bnd_mode - || bytemode == bnd_mode); + || bytemode == bnd_mode + || bytemode == bnd_swap_mode); const char **indexes64 = names64; const char **indexes32 = names32; @@ -15389,7 +15396,8 @@ OP_E_memory (int bytemode, int sizeflag) if ((havebase || haveindex || riprel) && (bytemode != v_bnd_mode) - && (bytemode != bnd_mode)) + && (bytemode != bnd_mode) + && (bytemode != bnd_swap_mode)) used_prefixes |= PREFIX_ADDR; if (havedisp || (intel_syntax && riprel)) diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 26e81ffa60..41ec1bea24 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -2872,8 +2872,8 @@ bnd, 0, 0xf2, None, 1, CpuMPX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf| // MPX instructions. bndmk, 2, 0xf30f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex, RegBND } -bndmov, 2, 0x660f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegBND, RegBND } -bndmov, 2, 0x660f1b, None, 2, CpuMPX, Load|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Xmmword|Unspecified|BaseIndex|RegBND } +bndmov, 2, 0x660f1a, None, 2, CpuMPX, Load|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegBND, RegBND } +bndmov, 2, 0x660f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Xmmword|Unspecified|BaseIndex|RegBND } bndcl, 2, 0xf30f1a, None, 2, CpuMPX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Anysize|BaseIndex, RegBND } bndcl, 2, 0xf30f1a, None, 2, CpuMPX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64|Anysize|BaseIndex, RegBND } bndcu, 2, 0xf20f1a, None, 2, CpuMPX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Anysize|BaseIndex, RegBND } diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index 51f7109c10..c576459d1f 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -69914,7 +69914,7 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, @@ -69931,7 +69931,7 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },