Support for different MIPS IDT processor models.
* mips-tdep.c (mips_processor_type, tmp_mips_processor_type, mips_generic_reg_names, mips_r3041_reg_names, mips_r3051_reg_names, mips_r3081_reg_names, mips_processor_type_table): New globals. (mips_do_registers_info): Don't display register if name is empty. (mips_set_processor_type_command): New command. (mips_show_processor_type_command): New command. (mips_set_processor_type): New function. (mips_read_processor_type): New function. * config/mips/tm-idt.h (DEFAULT_MIPS_TYPE): New macro. * config/mips/tm-mips.h (DEFAULT_MIPS_TYPE): New macro. (NUM_REGS): Increase to account for all CP0 registers. (REGISTER_NAMES): Add empty names for CP0 registers. (FIRST_EMBED_REGNUM, LAST_EMBED_REGNUM): Adjust. (PRID_REGNUM): New macro.
This commit is contained in:
Stan Shebs
parent
f618f758e9
commit
9f9f94aa09
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@ -1,3 +1,22 @@
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Thu Nov 17 17:51:12 1994 Stan Shebs (shebs@andros.cygnus.com)
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Support for different MIPS IDT processor models.
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* mips-tdep.c (mips_processor_type, tmp_mips_processor_type,
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mips_generic_reg_names, mips_r3041_reg_names,
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mips_r3051_reg_names, mips_r3081_reg_names,
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mips_processor_type_table): New globals.
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(mips_do_registers_info): Don't display register if name is empty.
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(mips_set_processor_type_command): New command.
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(mips_show_processor_type_command): New command.
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(mips_set_processor_type): New function.
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(mips_read_processor_type): New function.
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* config/mips/tm-idt.h (DEFAULT_MIPS_TYPE): New macro.
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* config/mips/tm-mips.h (DEFAULT_MIPS_TYPE): New macro.
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(NUM_REGS): Increase to account for all CP0 registers.
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(REGISTER_NAMES): Add empty names for CP0 registers.
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(FIRST_EMBED_REGNUM, LAST_EMBED_REGNUM): Adjust.
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(PRID_REGNUM): New macro.
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Wed Nov 16 16:41:52 1994 Stan Shebs (shebs@andros.cygnus.com)
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* README: Add warning about termcap in Ultrix and OSF/1.
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@ -19,3 +19,6 @@ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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#define TARGET_BYTE_ORDER_SELECTABLE
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#include "mips/tm-bigmips.h"
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#undef DEFAULT_MIPS_TYPE
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#define DEFAULT_MIPS_TYPE "r3051"
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@ -34,13 +34,16 @@ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* Floating point is IEEE compliant */
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#define IEEE_FLOAT
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extern int mips_processor_id;
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/* Some MIPS boards are provided both with and without a floating
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point coprocessor; we provide a user settable variable to tell gdb
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whether there is one or not. */
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extern int mips_fpu;
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/* The name of the usual type of MIPS processor that is in the target
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system. */
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#define DEFAULT_MIPS_TYPE "generic"
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/* Offset from address of function to start of its code.
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Zero on most machines. */
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@ -105,7 +108,7 @@ extern int in_sigtramp PARAMS ((CORE_ADDR, char *));
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/* Number of machine registers */
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#define NUM_REGS 80
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#define NUM_REGS 90
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/* Initializer for an array of names of registers.
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There should be NUM_REGS strings in this initializer. */
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@ -120,8 +123,9 @@ extern int in_sigtramp PARAMS ((CORE_ADDR, char *));
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"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
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"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",\
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"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",\
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"fsr", "fir", "fp", "inx", "rand", "tlblo","ctxt", "tlbhi",\
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"epc", "prid"\
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"fsr", "fir", "fp", "", \
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"", "", "", "", "", "", "", "", \
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"", "", "", "", "", "", "", "", \
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}
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/* Register numbers of various important registers.
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@ -146,8 +150,9 @@ extern int in_sigtramp PARAMS ((CORE_ADDR, char *));
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#define FCRCS_REGNUM 70 /* FP control/status */
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#define FCRIR_REGNUM 71 /* FP implementation/revision */
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#define FP_REGNUM 72 /* Pseudo register that contains true address of executing stack frame */
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#define FIRST_EMBED_REGNUM 73 /* First supervisor register for embedded use */
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#define LAST_EMBED_REGNUM 79 /* Last one */
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#define FIRST_EMBED_REGNUM 74 /* First CP0 register for embedded use */
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#define PRID_REGNUM 89 /* Processor ID */
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#define LAST_EMBED_REGNUM 89 /* Last one */
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/* Define DO_REGISTERS_INFO() to do machine-specific formatting
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of register dumps. */
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@ -156,6 +161,7 @@ extern int in_sigtramp PARAMS ((CORE_ADDR, char *));
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/* Total amount of space needed to store our copies of the machine's
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register state, the array `registers'. */
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#define REGISTER_BYTES (NUM_REGS*MIPS_REGSIZE)
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/* Index within `registers' of the first byte of the space for
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338
gdb/mips-tdep.c
338
gdb/mips-tdep.c
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@ -43,13 +43,95 @@ extern struct obstack frame_cache_obstack;
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static int mips_in_lenient_prologue PARAMS ((CORE_ADDR, CORE_ADDR));
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#endif
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void mips_set_processor_type_command PARAMS ((char *, int));
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static void reinit_frame_cache_sfunc PARAMS ((char *, int,
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struct cmd_list_element *));
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/* This value is the model of MIPS in use. It is derived from the value
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of the PrID register. */
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char *mips_processor_type;
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char *tmp_mips_processor_type;
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/* Some MIPS boards don't support floating point, so we permit the
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user to turn it off. */
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int mips_fpu = 1;
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/* A set of original names, to be used when restoring back to generic
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registers from a specific set. */
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char *mips_generic_reg_names[] = REGISTER_NAMES;
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/* Names of IDT R3041 registers. */
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char *mips_r3041_reg_names[] = {
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"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
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"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
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"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
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"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
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"sr", "lo", "hi", "bad", "cause","pc",
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"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
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"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
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"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
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"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
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"fsr", "fir", "fp", "",
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"", "", "bus", "ccfg", "", "", "", "",
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"", "", "port", "cmp", "", "", "epc", "prid",
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};
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/* Names of IDT R3051 registers. */
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char *mips_r3051_reg_names[] = {
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"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
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"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
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"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
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"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
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"sr", "lo", "hi", "bad", "cause","pc",
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"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
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"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
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"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
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"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
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"fsr", "fir", "fp", "",
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"inx", "rand", "elo", "", "ctxt", "", "", "",
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"", "", "ehi", "", "", "", "epc", "prid",
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};
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/* Names of IDT R3081 registers. */
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char *mips_r3081_reg_names[] = {
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"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
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"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
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"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
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"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
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"sr", "lo", "hi", "bad", "cause","pc",
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"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
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"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
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"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
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"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
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"fsr", "fir", "fp", "",
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"inx", "rand", "elo", "cfg", "ctxt", "", "", "",
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"", "", "ehi", "", "", "", "epc", "prid",
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};
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struct {
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char *name;
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char **regnames;
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} mips_processor_type_table[] = {
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{ "generic", mips_generic_reg_names },
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{ "r3041", mips_r3041_reg_names },
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{ "r3051", mips_r3051_reg_names },
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{ "r3071", mips_r3081_reg_names },
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{ "r3081", mips_r3081_reg_names },
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{ NULL, NULL }
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};
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/* Heuristic_proc_start may hunt through the text section for a long
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time across a 2400 baud serial line. Allows the user to limit this
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search. */
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static unsigned int heuristic_fence_post = 0;
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#define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
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@ -78,7 +160,7 @@ struct linked_proc_info
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void
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mips_find_saved_regs (fci)
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FRAME fci;
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struct frame_info *fci;
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{
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int ireg;
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CORE_ADDR reg_position;
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@ -202,7 +284,7 @@ mips_find_saved_regs (fci)
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static int
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read_next_frame_reg(fi, regno)
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FRAME fi;
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struct frame_info *fi;
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int regno;
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{
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/* If it is the frame for sigtramp we have a complete sigcontext
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@ -244,7 +326,7 @@ read_next_frame_reg(fi, regno)
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int
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mips_frame_saved_pc(frame)
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FRAME frame;
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struct frame_info *frame;
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{
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mips_extra_func_info_t proc_desc = frame->proc_desc;
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/* We have to get the saved pc from the sigcontext
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@ -326,7 +408,7 @@ Otherwise, you told GDB there was a function where there isn't one, or\n\
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static mips_extra_func_info_t
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heuristic_proc_desc(start_pc, limit_pc, next_frame)
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CORE_ADDR start_pc, limit_pc;
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FRAME next_frame;
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struct frame_info *next_frame;
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{
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CORE_ADDR sp = read_next_frame_reg (next_frame, SP_REGNUM);
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CORE_ADDR cur_pc;
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@ -336,11 +418,12 @@ heuristic_proc_desc(start_pc, limit_pc, next_frame)
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unsigned long reg_mask = 0;
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if (start_pc == 0) return NULL;
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memset(&temp_proc_desc, '\0', sizeof(temp_proc_desc));
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memset(&temp_saved_regs, '\0', sizeof(struct frame_saved_regs));
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PROC_LOW_ADDR(&temp_proc_desc) = start_pc;
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memset (&temp_proc_desc, '\0', sizeof(temp_proc_desc));
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memset (&temp_saved_regs, '\0', sizeof(struct frame_saved_regs));
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PROC_LOW_ADDR (&temp_proc_desc) = start_pc;
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if (start_pc + 200 < limit_pc) limit_pc = start_pc + 200;
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if (start_pc + 200 < limit_pc)
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limit_pc = start_pc + 200;
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restart:
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frame_size = 0;
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for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += 4) {
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@ -399,9 +482,9 @@ heuristic_proc_desc(start_pc, limit_pc, next_frame)
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}
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static mips_extra_func_info_t
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find_proc_desc(pc, next_frame)
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CORE_ADDR pc;
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FRAME next_frame;
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find_proc_desc (pc, next_frame)
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CORE_ADDR pc;
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struct frame_info *next_frame;
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{
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mips_extra_func_info_t proc_desc;
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struct block *b = block_for_pc(pc);
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@ -431,7 +514,7 @@ find_proc_desc(pc, next_frame)
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* THEN create a "heuristic" proc_desc (by analyzing
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* the actual code) to replace the "official" proc_desc.
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*/
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proc_desc = (mips_extra_func_info_t)SYMBOL_VALUE(sym);
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proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym);
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if (next_frame == NULL) {
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struct symtab_and_line val;
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struct symbol *proc_symbol =
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@ -445,9 +528,10 @@ find_proc_desc(pc, next_frame)
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}
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if (!proc_symbol || pc < val.pc) {
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mips_extra_func_info_t found_heuristic =
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heuristic_proc_desc(PROC_LOW_ADDR(proc_desc),
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pc, next_frame);
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if (found_heuristic) proc_desc = found_heuristic;
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heuristic_proc_desc (PROC_LOW_ADDR (proc_desc),
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pc, next_frame);
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if (found_heuristic)
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proc_desc = found_heuristic;
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}
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}
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}
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@ -459,10 +543,11 @@ find_proc_desc(pc, next_frame)
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heuristic_proc_desc knows how to create them! */
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register struct linked_proc_info *link;
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for (link = linked_proc_desc_table; link; link = link->next)
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if (PROC_LOW_ADDR(&link->info) <= pc
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&& PROC_HIGH_ADDR(&link->info) > pc)
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return &link->info;
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if (PROC_LOW_ADDR(&link->info) <= pc
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&& PROC_HIGH_ADDR(&link->info) > pc)
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return &link->info;
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if (startaddr == 0)
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startaddr = heuristic_proc_start (pc);
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@ -475,9 +560,9 @@ find_proc_desc(pc, next_frame)
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mips_extra_func_info_t cached_proc_desc;
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FRAME_ADDR
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CORE_ADDR
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mips_frame_chain(frame)
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FRAME frame;
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struct frame_info *frame;
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{
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mips_extra_func_info_t proc_desc;
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CORE_ADDR saved_pc = FRAME_SAVED_PC(frame);
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@ -563,10 +648,10 @@ init_extra_frame_info(fci)
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cache. This allows the rest of info frame to extract the important
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arguments without difficulty. */
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FRAME
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struct frame_info *
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setup_arbitrary_frame (argc, argv)
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int argc;
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FRAME_ADDR *argv;
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CORE_ADDR *argv;
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{
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if (argc != 2)
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error ("MIPS frame specifications require two arguments: sp and pc");
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@ -608,34 +693,33 @@ mips_push_arguments(nargs, args, sp, struct_return, struct_addr)
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accumulate_size = (accumulate_size + 7) & -8;
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m_arg->offset = accumulate_size;
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m_arg->contents = VALUE_CONTENTS(arg);
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#ifndef GDB_TARGET_IS_MIPS64
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accumulate_size = (accumulate_size + m_arg->len + 3) & -4;
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#else
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if (accumulate_size >= 4 * MIPS_REGSIZE)
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accumulate_size = (accumulate_size + m_arg->len + 3) &~ 4;
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if (! GDB_TARGET_IS_MIPS64)
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accumulate_size = (accumulate_size + m_arg->len + 3) & -4;
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else
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{
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static char zeroes[8] = { 0 };
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int len = m_arg->len;
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if (len < 8)
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if (accumulate_size >= 4 * MIPS_REGSIZE)
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accumulate_size = (accumulate_size + m_arg->len + 3) &~ 4;
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else
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{
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#if TARGET_BYTE_ORDER == BIG_ENDIAN
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m_arg->offset += 8 - len;
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#endif
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++m_arg;
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m_arg->len = 8 - len;
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m_arg->contents = zeroes;
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#if TARGET_BYTE_ORDER == BIG_ENDIAN
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m_arg->offset = accumulate_size;
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#else
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m_arg->offset = accumulate_size + len;
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#endif
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++fake_args;
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static char zeroes[8] = { 0 };
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int len = m_arg->len;
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if (len < 8)
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{
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if (TARGET_BYTE_ORDER == BIG_ENDIAN)
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m_arg->offset += 8 - len;
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++m_arg;
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m_arg->len = 8 - len;
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m_arg->contents = zeroes;
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if (TARGET_BYTE_ORDER == BIG_ENDIAN)
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m_arg->offset = accumulate_size;
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else
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m_arg->offset = accumulate_size + len;
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++fake_args;
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}
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accumulate_size = (accumulate_size + len + 7) & ~8;
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}
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accumulate_size = (accumulate_size + len + 7) & ~8;
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}
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#endif
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}
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accumulate_size = (accumulate_size + 7) & (-8);
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if (accumulate_size < 4 * MIPS_REGSIZE)
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@ -759,8 +843,8 @@ void
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mips_pop_frame()
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{
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register int regnum;
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FRAME frame = get_current_frame ();
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CORE_ADDR new_sp = frame->frame;
|
||||
struct frame_info *frame = get_current_frame ();
|
||||
CORE_ADDR new_sp = FRAME_FP (frame);
|
||||
|
||||
mips_extra_func_info_t proc_desc = frame->proc_desc;
|
||||
|
||||
|
|
@ -781,8 +865,6 @@ mips_pop_frame()
|
|||
}
|
||||
write_register (SP_REGNUM, new_sp);
|
||||
flush_cached_frames ();
|
||||
/* We let mips_init_extra_frame_info figure out the frame pointer */
|
||||
set_current_frame (create_new_frame (0, read_pc ()));
|
||||
|
||||
if (proc_desc && PROC_DESC_IS_DUMMY(proc_desc))
|
||||
{
|
||||
|
|
@ -870,48 +952,66 @@ mips_print_register (regnum, all)
|
|||
}
|
||||
|
||||
/* Replacement for generic do_registers_info. */
|
||||
|
||||
void
|
||||
mips_do_registers_info (regnum, fpregs)
|
||||
int regnum;
|
||||
int fpregs;
|
||||
{
|
||||
if (regnum != -1) {
|
||||
if (regnum != -1)
|
||||
{
|
||||
if (*(reg_names[regnum]) == '\0')
|
||||
error ("Not a valid register for the current processor type");
|
||||
|
||||
mips_print_register (regnum, 0);
|
||||
printf_filtered ("\n");
|
||||
}
|
||||
else {
|
||||
for (regnum = 0; regnum < NUM_REGS; ) {
|
||||
if ((!fpregs) && regnum >= FP0_REGNUM && regnum <= FCRIR_REGNUM) {
|
||||
regnum++;
|
||||
continue;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
int did_newline;
|
||||
|
||||
for (regnum = 0; regnum < NUM_REGS; )
|
||||
{
|
||||
if (((!fpregs) && regnum >= FP0_REGNUM && regnum <= FCRIR_REGNUM)
|
||||
|| *(reg_names[regnum]) == '\0')
|
||||
{
|
||||
regnum++;
|
||||
continue;
|
||||
}
|
||||
mips_print_register (regnum, 1);
|
||||
regnum++;
|
||||
if ((regnum & 3) == 0 || regnum == NUM_REGS)
|
||||
printf_filtered (";\n");
|
||||
else
|
||||
printf_filtered ("; ");
|
||||
}
|
||||
}
|
||||
printf_filtered ("; ");
|
||||
did_newline = 0;
|
||||
if ((regnum & 3) == 0)
|
||||
{
|
||||
printf_filtered ("\n");
|
||||
did_newline = 1;
|
||||
}
|
||||
}
|
||||
if (!did_newline)
|
||||
printf_filtered ("\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* Return number of args passed to a frame. described by FIP.
|
||||
Can return -1, meaning no way to tell. */
|
||||
|
||||
int
|
||||
mips_frame_num_args(fip)
|
||||
FRAME fip;
|
||||
mips_frame_num_args (frame)
|
||||
struct frame_info *frame;
|
||||
{
|
||||
#if 0
|
||||
struct chain_info_t *p;
|
||||
#if 0 /* FIXME Use or lose this! */
|
||||
struct chain_info_t *p;
|
||||
|
||||
p = mips_find_cached_frame(FRAME_FP(fip));
|
||||
if (p->valid)
|
||||
return p->the_info.numargs;
|
||||
p = mips_find_cached_frame (FRAME_FP (frame));
|
||||
if (p->valid)
|
||||
return p->the_info.numargs;
|
||||
#endif
|
||||
return -1;
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Is this a branch with a delay slot? */
|
||||
|
||||
static int is_delayed PARAMS ((unsigned long));
|
||||
|
||||
static int
|
||||
|
|
@ -1110,11 +1210,90 @@ in_sigtramp (pc, ignore)
|
|||
return (pc >= sigtramp_address && pc < sigtramp_end);
|
||||
}
|
||||
|
||||
static void reinit_frame_cache_sfunc PARAMS ((char *, int,
|
||||
struct cmd_list_element *));
|
||||
/* Command to set the processor type. */
|
||||
|
||||
void
|
||||
mips_set_processor_type_command (args, from_tty)
|
||||
char *args;
|
||||
int from_tty;
|
||||
{
|
||||
int i;
|
||||
|
||||
if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0')
|
||||
{
|
||||
printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
|
||||
for (i = 0; mips_processor_type_table[i].name != NULL; ++i)
|
||||
printf_unfiltered ("%s\n", mips_processor_type_table[i].name);
|
||||
|
||||
/* Restore the value. */
|
||||
tmp_mips_processor_type = strsave (mips_processor_type);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
if (!mips_set_processor_type (tmp_mips_processor_type))
|
||||
{
|
||||
error ("Unknown processor type `%s'.", tmp_mips_processor_type);
|
||||
/* Restore its value. */
|
||||
tmp_mips_processor_type = strsave (mips_processor_type);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
mips_show_processor_type_command (args, from_tty)
|
||||
char *args;
|
||||
int from_tty;
|
||||
{
|
||||
}
|
||||
|
||||
/* Modify the actual processor type. */
|
||||
|
||||
int
|
||||
mips_set_processor_type (str)
|
||||
char *str;
|
||||
{
|
||||
int i, j;
|
||||
|
||||
if (str == NULL)
|
||||
return;
|
||||
|
||||
for (i = 0; mips_processor_type_table[i].name != NULL; ++i)
|
||||
{
|
||||
if (strcasecmp (str, mips_processor_type_table[i].name) == 0)
|
||||
{
|
||||
mips_processor_type = str;
|
||||
|
||||
for (j = 0; j < NUM_REGS; ++j)
|
||||
reg_names[j] = mips_processor_type_table[i].regnames[j];
|
||||
|
||||
return 1;
|
||||
|
||||
/* FIXME tweak fpu flag too */
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Attempt to identify the particular processor model by reading the
|
||||
processor id. */
|
||||
|
||||
char *
|
||||
mips_read_processor_type ()
|
||||
{
|
||||
int prid;
|
||||
|
||||
prid = read_register (PRID_REGNUM);
|
||||
|
||||
if (prid & ~0xf == 0x700)
|
||||
return savestring ("r3041", strlen("r3041"));
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Just like reinit_frame_cache, but with the right arguments to be
|
||||
callable as an sfunc. */
|
||||
|
||||
static void
|
||||
reinit_frame_cache_sfunc (args, from_tty, c)
|
||||
char *args;
|
||||
|
|
@ -1140,6 +1319,19 @@ Turn off to avoid using floating point instructions when calling functions\n\
|
|||
or dealing with return values.", &setlist),
|
||||
&showlist);
|
||||
|
||||
c = add_set_cmd ("processor", class_support, var_string_noescape,
|
||||
(char *) &tmp_mips_processor_type,
|
||||
"Set the type of MIPS processor in use.\n\
|
||||
Set this to be able to access processor-type-specific registers.\n\
|
||||
",
|
||||
&setlist);
|
||||
c->function.cfunc = mips_set_processor_type_command;
|
||||
c = add_show_from_set (c, &showlist);
|
||||
c->function.cfunc = mips_show_processor_type_command;
|
||||
|
||||
tmp_mips_processor_type = strsave (DEFAULT_MIPS_TYPE);
|
||||
mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE), 0);
|
||||
|
||||
/* We really would like to have both "0" and "unlimited" work, but
|
||||
command.c doesn't deal with that. So make it a var_zinteger
|
||||
because the user can always use "999999" or some such for unlimited. */
|
||||
|
|
|
|||
Loading…
Reference in New Issue