x86: optimize EVEX packed integer logical instructions
As long as there's no write mask as well as no broadcast, and as long
as the scaled Disp8 wouldn't result in a shorter EVEX encoding, encode
VPAND{D,Q}, VPANDN{D,Q}, VPOR{D,Q}, and VPXOR{D,Q} acting on only the
lower 16 XMM/YMM registers using their VEX equivalents with -O1.
Also take the opportunity and avoid looping twice over all operands
when dealing with memory-with-displacement ones.
This commit is contained in:
Jan Beulich
parent
cd546e7bd2
commit
a0a1771e89
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@ -1,3 +1,32 @@
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2019-07-01 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (optimize_encoding): Make j unsigned. Handle
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vpand{d,q}, vpandn{d,q}, vpor{d,q}, and vpxor{d,q}. Also check/
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clear broadcast. Eliminate a loop.
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* doc/c-i386.texi: Update -O1 documentation.
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* testsuite/gas/i386/optimize-1.s,
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testsuite/gas/i386/optimize-2.s,
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testsuite/gas/i386/optimize-3.s,
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testsuite/gas/i386/optimize-5.s,
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testsuite/gas/i386/x86-64-optimize-2.s,
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testsuite/gas/i386/x86-64-optimize-3.s,
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testsuite/gas/i386/x86-64-optimize-4.s,
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testsuite/gas/i386/x86-64-optimize-6.s: Add vpand{d,q},
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vpandn{d,q}, vpor{d,q}, and vpxor{d,q} cases.
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testsuite/gas/i386/optimize-1.d,
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testsuite/gas/i386/optimize-1a.d,
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testsuite/gas/i386/optimize-2.d,
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testsuite/gas/i386/optimize-3.d,
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testsuite/gas/i386/optimize-4.d,
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testsuite/gas/i386/optimize-5.d,
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testsuite/gas/i386/x86-64-optimize-2.d,
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testsuite/gas/i386/x86-64-optimize-2a.d,
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testsuite/gas/i386/x86-64-optimize-2b.d,
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testsuite/gas/i386/x86-64-optimize-3.d,
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testsuite/gas/i386/x86-64-optimize-4.d,
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testsuite/gas/i386/x86-64-optimize-5.d,
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testsuite/gas/i386/x86-64-optimize-6.d: Adjust expectations.
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2019-07-01 Jan Beulich <jbeulich@suse.com>
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* testsuite/gas/i386/avx512f_vpclmulqdq.s,
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@ -3897,7 +3897,7 @@ check_hle (void)
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static void
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optimize_encoding (void)
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{
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int j;
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unsigned int j;
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if (optimize_for_space
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&& i.reg_operands == 1
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@ -4095,10 +4095,13 @@ optimize_encoding (void)
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&& !i.types[0].bitfield.zmmword
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&& !i.types[1].bitfield.zmmword
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&& !i.mask
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&& !i.broadcast
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&& is_evex_encoding (&i.tm)
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&& ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x666f
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|| (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf36f
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|| (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f)
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|| (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f
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|| (i.tm.base_opcode & ~4) == 0x66db
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|| (i.tm.base_opcode & ~4) == 0x66eb)
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&& i.tm.extension_opcode == None)
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{
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/* Optimize: -O1:
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@ -4116,8 +4119,17 @@ optimize_encoding (void)
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-> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
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EVEX VOP mem, %ymmN
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-> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
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VOP, one of vpand, vpandn, vpor, vpxor:
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EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
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-> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
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EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
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-> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
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EVEX VOP{d,q} mem, %xmmM, %xmmN
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-> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
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EVEX VOP{d,q} mem, %ymmM, %ymmN
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-> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
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*/
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for (j = 0; j < 2; j++)
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for (j = 0; j < i.operands; j++)
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if (operand_type_check (i.types[j], disp)
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&& i.op[j].disps->X_op == O_constant)
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{
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@ -4147,16 +4159,12 @@ optimize_encoding (void)
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i.tm.opcode_modifier.vexw = VEXW0;
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i.tm.opcode_modifier.evex = 0;
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i.tm.opcode_modifier.masking = 0;
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i.tm.opcode_modifier.broadcast = 0;
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i.tm.opcode_modifier.disp8memshift = 0;
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i.memshift = 0;
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for (j = 0; j < 2; j++)
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if (operand_type_check (i.types[j], disp)
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&& i.op[j].disps->X_op == O_constant)
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{
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i.types[j].bitfield.disp8
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= fits_in_disp8 (i.op[j].disps->X_add_number);
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break;
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}
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if (j < i.operands)
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i.types[j].bitfield.disp8
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= fits_in_disp8 (i.op[j].disps->X_add_number);
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}
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}
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@ -465,13 +465,17 @@ Optimize instruction encoding with smaller instruction size. @samp{-O}
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and @samp{-O1} encode 64-bit register load instructions with 64-bit
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immediate as 32-bit register load instructions with 31-bit or 32-bits
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immediates, encode 64-bit register clearing instructions with 32-bit
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register clearing instructions and encode 256-bit/512-bit VEX/EVEX
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vector register clearing instructions with 128-bit VEX vector register
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clearing instructions as well as encode 128-bit/256-bit EVEX vector
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register clearing instructions, encode 256-bit/512-bit VEX/EVEX vector
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register clearing instructions with 128-bit VEX vector register
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clearing instructions, encode 128-bit/256-bit EVEX vector
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register load/store instructions with VEX vector register load/store
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instructions. @samp{-O2} includes @samp{-O1} optimization plus
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encodes 256-bit/512-bit EVEX vector register clearing instructions with
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128-bit EVEX vector register clearing instructions.
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instructions, and encode 128-bit/256-bit EVEX packed integer logical
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instructions with 128-bit/256-bit VEX packed integer logical.
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@samp{-O2} includes @samp{-O1} optimization plus encodes
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256-bit/512-bit EVEX vector register clearing instructions with 128-bit
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EVEX vector register clearing instructions.
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@samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit
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and 64-bit register tests with immediate as 8-bit register test with
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immediate. @samp{-O0} turns off this optimization.
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@ -99,4 +99,52 @@ Disassembly of section .text:
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+[a-f0-9]+: 62 f1 7e 28 7f 48 04 vmovdqu32 %ymm1,0x80\(%eax\)
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+[a-f0-9]+: 62 f1 fe 28 7f 48 04 vmovdqu64 %ymm1,0x80\(%eax\)
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+[a-f0-9]+: 62 f1 7d 48 6f 10 vmovdqa32 \(%eax\),%zmm2
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+[a-f0-9]+: c5 .* vpand %xmm2,%xmm3,%xmm4
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+[a-f0-9]+: c5 .* vpand %xmm2,%xmm3,%xmm4
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+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm3,%xmm4
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+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm3,%xmm4
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+[a-f0-9]+: c5 .* vpor %xmm2,%xmm3,%xmm4
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+[a-f0-9]+: c5 .* vpor %xmm2,%xmm3,%xmm4
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+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm3,%xmm4
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+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm3,%xmm4
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+[a-f0-9]+: c5 .* vpand %ymm2,%ymm3,%ymm4
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+[a-f0-9]+: c5 .* vpand %ymm2,%ymm3,%ymm4
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+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm3,%ymm4
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+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm3,%ymm4
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+[a-f0-9]+: c5 .* vpor %ymm2,%ymm3,%ymm4
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+[a-f0-9]+: c5 .* vpor %ymm2,%ymm3,%ymm4
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+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm3,%ymm4
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+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm3,%ymm4
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+[a-f0-9]+: c5 .* vpand 0x70\(%eax\),%xmm2,%xmm3
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+[a-f0-9]+: c5 .* vpand 0x70\(%eax\),%xmm2,%xmm3
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+[a-f0-9]+: c5 .* vpandn 0x70\(%eax\),%xmm2,%xmm3
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+[a-f0-9]+: c5 .* vpandn 0x70\(%eax\),%xmm2,%xmm3
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+[a-f0-9]+: c5 .* vpor 0x70\(%eax\),%xmm2,%xmm3
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+[a-f0-9]+: c5 .* vpor 0x70\(%eax\),%xmm2,%xmm3
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+[a-f0-9]+: c5 .* vpxor 0x70\(%eax\),%xmm2,%xmm3
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+[a-f0-9]+: c5 .* vpxor 0x70\(%eax\),%xmm2,%xmm3
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+[a-f0-9]+: 62 .* vpandd 0x80\(%eax\),%xmm2,%xmm3
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+[a-f0-9]+: 62 .* vpandq 0x80\(%eax\),%xmm2,%xmm3
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+[a-f0-9]+: 62 .* vpandnd 0x80\(%eax\),%xmm2,%xmm3
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+[a-f0-9]+: 62 .* vpandnq 0x80\(%eax\),%xmm2,%xmm3
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+[a-f0-9]+: 62 .* vpord 0x80\(%eax\),%xmm2,%xmm3
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+[a-f0-9]+: 62 .* vporq 0x80\(%eax\),%xmm2,%xmm3
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+[a-f0-9]+: 62 .* vpxord 0x80\(%eax\),%xmm2,%xmm3
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+[a-f0-9]+: 62 .* vpxorq 0x80\(%eax\),%xmm2,%xmm3
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+[a-f0-9]+: c5 .* vpand 0x60\(%eax\),%ymm2,%ymm3
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+[a-f0-9]+: c5 .* vpand 0x60\(%eax\),%ymm2,%ymm3
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+[a-f0-9]+: c5 .* vpandn 0x60\(%eax\),%ymm2,%ymm3
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+[a-f0-9]+: c5 .* vpandn 0x60\(%eax\),%ymm2,%ymm3
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+[a-f0-9]+: c5 .* vpor 0x60\(%eax\),%ymm2,%ymm3
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+[a-f0-9]+: c5 .* vpor 0x60\(%eax\),%ymm2,%ymm3
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+[a-f0-9]+: c5 .* vpxor 0x60\(%eax\),%ymm2,%ymm3
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+[a-f0-9]+: c5 .* vpxor 0x60\(%eax\),%ymm2,%ymm3
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+[a-f0-9]+: 62 .* vpandd 0x80\(%eax\),%ymm2,%ymm3
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+[a-f0-9]+: 62 .* vpandq 0x80\(%eax\),%ymm2,%ymm3
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+[a-f0-9]+: 62 .* vpandnd 0x80\(%eax\),%ymm2,%ymm3
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+[a-f0-9]+: 62 .* vpandnq 0x80\(%eax\),%ymm2,%ymm3
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+[a-f0-9]+: 62 .* vpord 0x80\(%eax\),%ymm2,%ymm3
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+[a-f0-9]+: 62 .* vporq 0x80\(%eax\),%ymm2,%ymm3
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+[a-f0-9]+: 62 .* vpxord 0x80\(%eax\),%ymm2,%ymm3
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+[a-f0-9]+: 62 .* vpxorq 0x80\(%eax\),%ymm2,%ymm3
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#pass
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@ -116,3 +116,57 @@ _start:
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vmovdqu64 %ymm1, 128(%eax)
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vmovdqa32 (%eax), %zmm2
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vpandd %xmm2, %xmm3, %xmm4
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vpandq %xmm2, %xmm3, %xmm4
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vpandnd %xmm2, %xmm3, %xmm4
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vpandnq %xmm2, %xmm3, %xmm4
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vpord %xmm2, %xmm3, %xmm4
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vporq %xmm2, %xmm3, %xmm4
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vpxord %xmm2, %xmm3, %xmm4
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vpxorq %xmm2, %xmm3, %xmm4
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vpandd %ymm2, %ymm3, %ymm4
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vpandq %ymm2, %ymm3, %ymm4
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vpandnd %ymm2, %ymm3, %ymm4
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vpandnq %ymm2, %ymm3, %ymm4
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vpord %ymm2, %ymm3, %ymm4
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vporq %ymm2, %ymm3, %ymm4
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vpxord %ymm2, %ymm3, %ymm4
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vpxorq %ymm2, %ymm3, %ymm4
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vpandd 112(%eax), %xmm2, %xmm3
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vpandq 112(%eax), %xmm2, %xmm3
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vpandnd 112(%eax), %xmm2, %xmm3
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vpandnq 112(%eax), %xmm2, %xmm3
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vpord 112(%eax), %xmm2, %xmm3
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vporq 112(%eax), %xmm2, %xmm3
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vpxord 112(%eax), %xmm2, %xmm3
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vpxorq 112(%eax), %xmm2, %xmm3
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vpandd 128(%eax), %xmm2, %xmm3
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vpandq 128(%eax), %xmm2, %xmm3
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vpandnd 128(%eax), %xmm2, %xmm3
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vpandnq 128(%eax), %xmm2, %xmm3
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vpord 128(%eax), %xmm2, %xmm3
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vporq 128(%eax), %xmm2, %xmm3
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vpxord 128(%eax), %xmm2, %xmm3
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vpxorq 128(%eax), %xmm2, %xmm3
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vpandd 96(%eax), %ymm2, %ymm3
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vpandq 96(%eax), %ymm2, %ymm3
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vpandnd 96(%eax), %ymm2, %ymm3
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vpandnq 96(%eax), %ymm2, %ymm3
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vpord 96(%eax), %ymm2, %ymm3
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vporq 96(%eax), %ymm2, %ymm3
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vpxord 96(%eax), %ymm2, %ymm3
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vpxorq 96(%eax), %ymm2, %ymm3
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vpandd 128(%eax), %ymm2, %ymm3
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vpandq 128(%eax), %ymm2, %ymm3
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vpandnd 128(%eax), %ymm2, %ymm3
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vpandnq 128(%eax), %ymm2, %ymm3
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vpord 128(%eax), %ymm2, %ymm3
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vporq 128(%eax), %ymm2, %ymm3
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vpxord 128(%eax), %ymm2, %ymm3
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vpxorq 128(%eax), %ymm2, %ymm3
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@ -100,4 +100,52 @@ Disassembly of section .text:
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+[a-f0-9]+: 62 f1 7e 28 7f 48 04 vmovdqu32 %ymm1,0x80\(%eax\)
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+[a-f0-9]+: 62 f1 fe 28 7f 48 04 vmovdqu64 %ymm1,0x80\(%eax\)
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+[a-f0-9]+: 62 f1 7d 48 6f 10 vmovdqa32 \(%eax\),%zmm2
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+[a-f0-9]+: c5 .* vpand %xmm2,%xmm3,%xmm4
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+[a-f0-9]+: c5 .* vpand %xmm2,%xmm3,%xmm4
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+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm3,%xmm4
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+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm3,%xmm4
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+[a-f0-9]+: c5 .* vpor %xmm2,%xmm3,%xmm4
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+[a-f0-9]+: c5 .* vpor %xmm2,%xmm3,%xmm4
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+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm3,%xmm4
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+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm3,%xmm4
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+[a-f0-9]+: c5 .* vpand %ymm2,%ymm3,%ymm4
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+[a-f0-9]+: c5 .* vpand %ymm2,%ymm3,%ymm4
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+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm3,%ymm4
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+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm3,%ymm4
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+[a-f0-9]+: c5 .* vpor %ymm2,%ymm3,%ymm4
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+[a-f0-9]+: c5 .* vpor %ymm2,%ymm3,%ymm4
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+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm3,%ymm4
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+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm3,%ymm4
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+[a-f0-9]+: c5 .* vpand 0x70\(%eax\),%xmm2,%xmm3
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+[a-f0-9]+: c5 .* vpand 0x70\(%eax\),%xmm2,%xmm3
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+[a-f0-9]+: c5 .* vpandn 0x70\(%eax\),%xmm2,%xmm3
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+[a-f0-9]+: c5 .* vpandn 0x70\(%eax\),%xmm2,%xmm3
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+[a-f0-9]+: c5 .* vpor 0x70\(%eax\),%xmm2,%xmm3
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+[a-f0-9]+: c5 .* vpor 0x70\(%eax\),%xmm2,%xmm3
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+[a-f0-9]+: c5 .* vpxor 0x70\(%eax\),%xmm2,%xmm3
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+[a-f0-9]+: c5 .* vpxor 0x70\(%eax\),%xmm2,%xmm3
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+[a-f0-9]+: 62 .* vpandd 0x80\(%eax\),%xmm2,%xmm3
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+[a-f0-9]+: 62 .* vpandq 0x80\(%eax\),%xmm2,%xmm3
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+[a-f0-9]+: 62 .* vpandnd 0x80\(%eax\),%xmm2,%xmm3
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+[a-f0-9]+: 62 .* vpandnq 0x80\(%eax\),%xmm2,%xmm3
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+[a-f0-9]+: 62 .* vpord 0x80\(%eax\),%xmm2,%xmm3
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+[a-f0-9]+: 62 .* vporq 0x80\(%eax\),%xmm2,%xmm3
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+[a-f0-9]+: 62 .* vpxord 0x80\(%eax\),%xmm2,%xmm3
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+[a-f0-9]+: 62 .* vpxorq 0x80\(%eax\),%xmm2,%xmm3
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+[a-f0-9]+: c5 .* vpand 0x60\(%eax\),%ymm2,%ymm3
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+[a-f0-9]+: c5 .* vpand 0x60\(%eax\),%ymm2,%ymm3
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+[a-f0-9]+: c5 .* vpandn 0x60\(%eax\),%ymm2,%ymm3
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+[a-f0-9]+: c5 .* vpandn 0x60\(%eax\),%ymm2,%ymm3
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+[a-f0-9]+: c5 .* vpor 0x60\(%eax\),%ymm2,%ymm3
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+[a-f0-9]+: c5 .* vpor 0x60\(%eax\),%ymm2,%ymm3
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+[a-f0-9]+: c5 .* vpxor 0x60\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x60\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandd 0x80\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandq 0x80\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandnd 0x80\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandnq 0x80\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpord 0x80\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vporq 0x80\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpxord 0x80\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpxorq 0x80\(%eax\),%ymm2,%ymm3
|
||||
#pass
|
||||
|
|
|
|||
|
|
@ -89,4 +89,68 @@ Disassembly of section .text:
|
|||
+[a-f0-9]+: 62 f1 ff 89 6f d1 vmovdqu16 %xmm1,%xmm2\{%k1\}\{z\}
|
||||
+[a-f0-9]+: 62 f1 7e 89 6f d1 vmovdqu32 %xmm1,%xmm2\{%k1\}\{z\}
|
||||
+[a-f0-9]+: 62 f1 fe 89 6f d1 vmovdqu64 %xmm1,%xmm2\{%k1\}\{z\}
|
||||
+[a-f0-9]+: c5 .* vpand %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpand %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpor %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpor %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpand %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpand %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpor %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpor %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpand 0x70\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpand 0x70\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x70\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x70\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x70\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x70\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x70\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x70\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandd 0x80\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandq 0x80\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandnd 0x80\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandnq 0x80\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpord 0x80\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vporq 0x80\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpxord 0x80\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpxorq 0x80\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpand 0x60\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpand 0x60\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x60\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x60\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x60\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x60\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x60\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x60\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandd 0x80\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandq 0x80\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandnd 0x80\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandnq 0x80\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpord 0x80\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vporq 0x80\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpxord 0x80\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpxorq 0x80\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandd %xmm2,%xmm3,%xmm4\{%k5\}
|
||||
+[a-f0-9]+: 62 .* vpandq %ymm2,%ymm3,%ymm4\{%k5\}
|
||||
+[a-f0-9]+: 62 .* vpandnd %ymm2,%ymm3,%ymm4\{%k5\}
|
||||
+[a-f0-9]+: 62 .* vpandnq %xmm2,%xmm3,%xmm4\{%k5\}
|
||||
+[a-f0-9]+: 62 .* vpord %xmm2,%xmm3,%xmm4\{%k5\}
|
||||
+[a-f0-9]+: 62 .* vporq %ymm2,%ymm3,%ymm4\{%k5\}
|
||||
+[a-f0-9]+: 62 .* vpxord %ymm2,%ymm3,%ymm4\{%k5\}
|
||||
+[a-f0-9]+: 62 .* vpxorq %xmm2,%xmm3,%xmm4\{%k5\}
|
||||
+[a-f0-9]+: 62 .* vpandd \(%eax\)\{1to8\},%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandq \(%eax\)\{1to2\},%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandnd \(%eax\)\{1to4\},%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandnq \(%eax\)\{1to4\},%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpord \(%eax\)\{1to8\},%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vporq \(%eax\)\{1to2\},%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpxord \(%eax\)\{1to4\},%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpxorq \(%eax\)\{1to4\},%ymm2,%ymm3
|
||||
#pass
|
||||
|
|
|
|||
|
|
@ -97,3 +97,75 @@ _start:
|
|||
vmovdqu16 %xmm1, %xmm2{%k1}{z}
|
||||
vmovdqu32 %xmm1, %xmm2{%k1}{z}
|
||||
vmovdqu64 %xmm1, %xmm2{%k1}{z}
|
||||
|
||||
vpandd %xmm2, %xmm3, %xmm4
|
||||
vpandq %xmm2, %xmm3, %xmm4
|
||||
vpandnd %xmm2, %xmm3, %xmm4
|
||||
vpandnq %xmm2, %xmm3, %xmm4
|
||||
vpord %xmm2, %xmm3, %xmm4
|
||||
vporq %xmm2, %xmm3, %xmm4
|
||||
vpxord %xmm2, %xmm3, %xmm4
|
||||
vpxorq %xmm2, %xmm3, %xmm4
|
||||
|
||||
vpandd %ymm2, %ymm3, %ymm4
|
||||
vpandq %ymm2, %ymm3, %ymm4
|
||||
vpandnd %ymm2, %ymm3, %ymm4
|
||||
vpandnq %ymm2, %ymm3, %ymm4
|
||||
vpord %ymm2, %ymm3, %ymm4
|
||||
vporq %ymm2, %ymm3, %ymm4
|
||||
vpxord %ymm2, %ymm3, %ymm4
|
||||
vpxorq %ymm2, %ymm3, %ymm4
|
||||
|
||||
vpandd 112(%eax), %xmm2, %xmm3
|
||||
vpandq 112(%eax), %xmm2, %xmm3
|
||||
vpandnd 112(%eax), %xmm2, %xmm3
|
||||
vpandnq 112(%eax), %xmm2, %xmm3
|
||||
vpord 112(%eax), %xmm2, %xmm3
|
||||
vporq 112(%eax), %xmm2, %xmm3
|
||||
vpxord 112(%eax), %xmm2, %xmm3
|
||||
vpxorq 112(%eax), %xmm2, %xmm3
|
||||
|
||||
vpandd 128(%eax), %xmm2, %xmm3
|
||||
vpandq 128(%eax), %xmm2, %xmm3
|
||||
vpandnd 128(%eax), %xmm2, %xmm3
|
||||
vpandnq 128(%eax), %xmm2, %xmm3
|
||||
vpord 128(%eax), %xmm2, %xmm3
|
||||
vporq 128(%eax), %xmm2, %xmm3
|
||||
vpxord 128(%eax), %xmm2, %xmm3
|
||||
vpxorq 128(%eax), %xmm2, %xmm3
|
||||
|
||||
vpandd 96(%eax), %ymm2, %ymm3
|
||||
vpandq 96(%eax), %ymm2, %ymm3
|
||||
vpandnd 96(%eax), %ymm2, %ymm3
|
||||
vpandnq 96(%eax), %ymm2, %ymm3
|
||||
vpord 96(%eax), %ymm2, %ymm3
|
||||
vporq 96(%eax), %ymm2, %ymm3
|
||||
vpxord 96(%eax), %ymm2, %ymm3
|
||||
vpxorq 96(%eax), %ymm2, %ymm3
|
||||
|
||||
vpandd 128(%eax), %ymm2, %ymm3
|
||||
vpandq 128(%eax), %ymm2, %ymm3
|
||||
vpandnd 128(%eax), %ymm2, %ymm3
|
||||
vpandnq 128(%eax), %ymm2, %ymm3
|
||||
vpord 128(%eax), %ymm2, %ymm3
|
||||
vporq 128(%eax), %ymm2, %ymm3
|
||||
vpxord 128(%eax), %ymm2, %ymm3
|
||||
vpxorq 128(%eax), %ymm2, %ymm3
|
||||
|
||||
vpandd %xmm2, %xmm3, %xmm4{%k5}
|
||||
vpandq %ymm2, %ymm3, %ymm4{%k5}
|
||||
vpandnd %ymm2, %ymm3, %ymm4{%k5}
|
||||
vpandnq %xmm2, %xmm3, %xmm4{%k5}
|
||||
vpord %xmm2, %xmm3, %xmm4{%k5}
|
||||
vporq %ymm2, %ymm3, %ymm4{%k5}
|
||||
vpxord %ymm2, %ymm3, %ymm4{%k5}
|
||||
vpxorq %xmm2, %xmm3, %xmm4{%k5}
|
||||
|
||||
vpandd (%eax){1to8}, %ymm2, %ymm3
|
||||
vpandq (%eax){1to2}, %xmm2, %xmm3
|
||||
vpandnd (%eax){1to4}, %xmm2, %xmm3
|
||||
vpandnq (%eax){1to4}, %ymm2, %ymm3
|
||||
vpord (%eax){1to8}, %ymm2, %ymm3
|
||||
vporq (%eax){1to2}, %xmm2, %xmm3
|
||||
vpxord (%eax){1to4}, %xmm2, %xmm3
|
||||
vpxorq (%eax){1to4}, %ymm2, %ymm3
|
||||
|
|
|
|||
|
|
@ -15,4 +15,12 @@ Disassembly of section .text:
|
|||
+[a-f0-9]+: 62 f1 ff 08 6f d1 vmovdqu16 %xmm1,%xmm2
|
||||
+[a-f0-9]+: 62 f1 7e 08 6f d1 vmovdqu32 %xmm1,%xmm2
|
||||
+[a-f0-9]+: 62 f1 fe 08 6f d1 vmovdqu64 %xmm1,%xmm2
|
||||
+[a-f0-9]+: 62 .* vpandd %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: 62 .* vpandq %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: 62 .* vpandnd %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: 62 .* vpandnq %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: 62 .* vpord %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: 62 .* vporq %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: 62 .* vpxord %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: 62 .* vpxorq %xmm2,%xmm3,%xmm4
|
||||
#pass
|
||||
|
|
|
|||
|
|
@ -11,3 +11,12 @@ _start:
|
|||
{nooptimize} vmovdqu16 %xmm1, %xmm2
|
||||
{nooptimize} vmovdqu32 %xmm1, %xmm2
|
||||
{nooptimize} vmovdqu64 %xmm1, %xmm2
|
||||
|
||||
{nooptimize} vpandd %xmm2, %xmm3, %xmm4
|
||||
{nooptimize} vpandq %ymm2, %ymm3, %ymm4
|
||||
{nooptimize} vpandnd %ymm2, %ymm3, %ymm4
|
||||
{nooptimize} vpandnq %xmm2, %xmm3, %xmm4
|
||||
{nooptimize} vpord %xmm2, %xmm3, %xmm4
|
||||
{nooptimize} vporq %ymm2, %ymm3, %ymm4
|
||||
{nooptimize} vpxord %ymm2, %ymm3, %ymm4
|
||||
{nooptimize} vpxorq %xmm2, %xmm3, %xmm4
|
||||
|
|
|
|||
|
|
@ -99,6 +99,54 @@ Disassembly of section .text:
|
|||
+[a-f0-9]+: 62 f1 7e 28 7f 48 04 vmovdqu32 %ymm1,0x80\(%eax\)
|
||||
+[a-f0-9]+: 62 f1 fe 28 7f 48 04 vmovdqu64 %ymm1,0x80\(%eax\)
|
||||
+[a-f0-9]+: 62 f1 7d 48 6f 10 vmovdqa32 \(%eax\),%zmm2
|
||||
+[a-f0-9]+: c5 .* vpand %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpand %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpor %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpor %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpand %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpand %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpor %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpor %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpand 0x70\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpand 0x70\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x70\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x70\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x70\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x70\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x70\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x70\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandd 0x80\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandq 0x80\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandnd 0x80\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandnq 0x80\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpord 0x80\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vporq 0x80\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpxord 0x80\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpxorq 0x80\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpand 0x60\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpand 0x60\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x60\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x60\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x60\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x60\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x60\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x60\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandd 0x80\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandq 0x80\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandnd 0x80\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandnq 0x80\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpord 0x80\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vporq 0x80\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpxord 0x80\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpxorq 0x80\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 f1 f5 08 55 e9 vandnpd %xmm1,%xmm1,%xmm5
|
||||
+[a-f0-9]+: 62 f1 f5 08 55 e9 vandnpd %xmm1,%xmm1,%xmm5
|
||||
#pass
|
||||
|
|
|
|||
|
|
@ -99,6 +99,54 @@ Disassembly of section .text:
|
|||
+[a-f0-9]+: 62 f1 7e 28 7f 48 04 vmovdqu32 %ymm1,0x80\(%eax\)
|
||||
+[a-f0-9]+: 62 f1 fe 28 7f 48 04 vmovdqu64 %ymm1,0x80\(%eax\)
|
||||
+[a-f0-9]+: 62 f1 7d 48 6f 10 vmovdqa32 \(%eax\),%zmm2
|
||||
+[a-f0-9]+: c5 .* vpand %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpand %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpor %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpor %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpand %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpand %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpor %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpor %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpand 0x70\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpand 0x70\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x70\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x70\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x70\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x70\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x70\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x70\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandd 0x80\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandq 0x80\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandnd 0x80\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandnq 0x80\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpord 0x80\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vporq 0x80\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpxord 0x80\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpxorq 0x80\(%eax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpand 0x60\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpand 0x60\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x60\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x60\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x60\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x60\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x60\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x60\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandd 0x80\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandq 0x80\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandnd 0x80\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandnq 0x80\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpord 0x80\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vporq 0x80\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpxord 0x80\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpxorq 0x80\(%eax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 f1 f5 08 55 e9 vandnpd %xmm1,%xmm1,%xmm5
|
||||
+[a-f0-9]+: 62 f1 f5 08 55 e9 vandnpd %xmm1,%xmm1,%xmm5
|
||||
+[a-f0-9]+: 62 f1 7d 28 6f d1 vmovdqa32 %ymm1,%ymm2
|
||||
|
|
@ -107,4 +155,12 @@ Disassembly of section .text:
|
|||
+[a-f0-9]+: 62 f1 ff 08 6f d1 vmovdqu16 %xmm1,%xmm2
|
||||
+[a-f0-9]+: 62 f1 7e 08 6f d1 vmovdqu32 %xmm1,%xmm2
|
||||
+[a-f0-9]+: 62 f1 fe 08 6f d1 vmovdqu64 %xmm1,%xmm2
|
||||
+[a-f0-9]+: 62 .* vpandd %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: 62 .* vpandq %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: 62 .* vpandnd %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: 62 .* vpandnq %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: 62 .* vpord %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: 62 .* vporq %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: 62 .* vpxord %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: 62 .* vpxorq %xmm2,%xmm3,%xmm4
|
||||
#pass
|
||||
|
|
|
|||
|
|
@ -13,3 +13,12 @@
|
|||
{evex} vmovdqu16 %xmm1, %xmm2
|
||||
{evex} vmovdqu32 %xmm1, %xmm2
|
||||
{evex} vmovdqu64 %xmm1, %xmm2
|
||||
|
||||
{evex} vpandd %xmm2, %xmm3, %xmm4
|
||||
{evex} vpandq %ymm2, %ymm3, %ymm4
|
||||
{evex} vpandnd %ymm2, %ymm3, %ymm4
|
||||
{evex} vpandnq %xmm2, %xmm3, %xmm4
|
||||
{evex} vpord %xmm2, %xmm3, %xmm4
|
||||
{evex} vporq %ymm2, %ymm3, %ymm4
|
||||
{evex} vpxord %ymm2, %ymm3, %ymm4
|
||||
{evex} vpxorq %xmm2, %xmm3, %xmm4
|
||||
|
|
|
|||
|
|
@ -155,4 +155,52 @@ Disassembly of section .text:
|
|||
+[a-f0-9]+: 62 f1 7e 28 7f 48 04 vmovdqu32 %ymm1,0x80\(%rax\)
|
||||
+[a-f0-9]+: 62 f1 fe 28 7f 48 04 vmovdqu64 %ymm1,0x80\(%rax\)
|
||||
+[a-f0-9]+: 62 f1 7d 48 6f 10 vmovdqa32 \(%rax\),%zmm2
|
||||
+[a-f0-9]+: c5 .* vpand %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c4 .* vpand %xmm12,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm13,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm3,%xmm14
|
||||
+[a-f0-9]+: c5 .* vpor %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c4 .* vpor %xmm12,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm13,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm3,%xmm14
|
||||
+[a-f0-9]+: c5 .* vpand %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c4 .* vpand %ymm12,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm13,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm3,%ymm14
|
||||
+[a-f0-9]+: c5 .* vpor %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c4 .* vpor %ymm12,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm13,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm3,%ymm14
|
||||
+[a-f0-9]+: c5 .* vpand 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpand 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandd 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandq 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandnd 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandnq 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpord 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vporq 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpxord 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpxorq 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpand 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpand 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandd 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandq 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandnd 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandnq 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpord 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vporq 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpxord 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpxorq 0x80\(%rax\),%ymm2,%ymm3
|
||||
#pass
|
||||
|
|
|
|||
|
|
@ -172,3 +172,57 @@ _start:
|
|||
vmovdqu64 %ymm1, 128(%rax)
|
||||
|
||||
vmovdqa32 (%rax), %zmm2
|
||||
|
||||
vpandd %xmm2, %xmm3, %xmm4
|
||||
vpandq %xmm12, %xmm3, %xmm4
|
||||
vpandnd %xmm2, %xmm13, %xmm4
|
||||
vpandnq %xmm2, %xmm3, %xmm14
|
||||
vpord %xmm2, %xmm3, %xmm4
|
||||
vporq %xmm12, %xmm3, %xmm4
|
||||
vpxord %xmm2, %xmm13, %xmm4
|
||||
vpxorq %xmm2, %xmm3, %xmm14
|
||||
|
||||
vpandd %ymm2, %ymm3, %ymm4
|
||||
vpandq %ymm12, %ymm3, %ymm4
|
||||
vpandnd %ymm2, %ymm13, %ymm4
|
||||
vpandnq %ymm2, %ymm3, %ymm14
|
||||
vpord %ymm2, %ymm3, %ymm4
|
||||
vporq %ymm12, %ymm3, %ymm4
|
||||
vpxord %ymm2, %ymm13, %ymm4
|
||||
vpxorq %ymm2, %ymm3, %ymm14
|
||||
|
||||
vpandd 112(%rax), %xmm2, %xmm3
|
||||
vpandq 112(%rax), %xmm2, %xmm3
|
||||
vpandnd 112(%rax), %xmm2, %xmm3
|
||||
vpandnq 112(%rax), %xmm2, %xmm3
|
||||
vpord 112(%rax), %xmm2, %xmm3
|
||||
vporq 112(%rax), %xmm2, %xmm3
|
||||
vpxord 112(%rax), %xmm2, %xmm3
|
||||
vpxorq 112(%rax), %xmm2, %xmm3
|
||||
|
||||
vpandd 128(%rax), %xmm2, %xmm3
|
||||
vpandq 128(%rax), %xmm2, %xmm3
|
||||
vpandnd 128(%rax), %xmm2, %xmm3
|
||||
vpandnq 128(%rax), %xmm2, %xmm3
|
||||
vpord 128(%rax), %xmm2, %xmm3
|
||||
vporq 128(%rax), %xmm2, %xmm3
|
||||
vpxord 128(%rax), %xmm2, %xmm3
|
||||
vpxorq 128(%rax), %xmm2, %xmm3
|
||||
|
||||
vpandd 96(%rax), %ymm2, %ymm3
|
||||
vpandq 96(%rax), %ymm2, %ymm3
|
||||
vpandnd 96(%rax), %ymm2, %ymm3
|
||||
vpandnq 96(%rax), %ymm2, %ymm3
|
||||
vpord 96(%rax), %ymm2, %ymm3
|
||||
vporq 96(%rax), %ymm2, %ymm3
|
||||
vpxord 96(%rax), %ymm2, %ymm3
|
||||
vpxorq 96(%rax), %ymm2, %ymm3
|
||||
|
||||
vpandd 128(%rax), %ymm2, %ymm3
|
||||
vpandq 128(%rax), %ymm2, %ymm3
|
||||
vpandnd 128(%rax), %ymm2, %ymm3
|
||||
vpandnq 128(%rax), %ymm2, %ymm3
|
||||
vpord 128(%rax), %ymm2, %ymm3
|
||||
vporq 128(%rax), %ymm2, %ymm3
|
||||
vpxord 128(%rax), %ymm2, %ymm3
|
||||
vpxorq 128(%rax), %ymm2, %ymm3
|
||||
|
|
|
|||
|
|
@ -156,4 +156,52 @@ Disassembly of section .text:
|
|||
+[a-f0-9]+: 62 f1 7e 28 7f 48 04 vmovdqu32 %ymm1,0x80\(%rax\)
|
||||
+[a-f0-9]+: 62 f1 fe 28 7f 48 04 vmovdqu64 %ymm1,0x80\(%rax\)
|
||||
+[a-f0-9]+: 62 f1 7d 48 6f 10 vmovdqa32 \(%rax\),%zmm2
|
||||
+[a-f0-9]+: c5 .* vpand %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c4 .* vpand %xmm12,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm13,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm3,%xmm14
|
||||
+[a-f0-9]+: c5 .* vpor %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c4 .* vpor %xmm12,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm13,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm3,%xmm14
|
||||
+[a-f0-9]+: c5 .* vpand %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c4 .* vpand %ymm12,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm13,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm3,%ymm14
|
||||
+[a-f0-9]+: c5 .* vpor %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c4 .* vpor %ymm12,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm13,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm3,%ymm14
|
||||
+[a-f0-9]+: c5 .* vpand 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpand 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandd 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandq 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandnd 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandnq 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpord 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vporq 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpxord 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpxorq 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpand 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpand 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandd 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandq 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandnd 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandnq 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpord 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vporq 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpxord 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpxorq 0x80\(%rax\),%ymm2,%ymm3
|
||||
#pass
|
||||
|
|
|
|||
|
|
@ -155,4 +155,52 @@ Disassembly of section .text:
|
|||
+[a-f0-9]+: 62 f1 7e 28 7f 48 04 vmovdqu32 %ymm1,0x80\(%rax\)
|
||||
+[a-f0-9]+: 62 f1 fe 28 7f 48 04 vmovdqu64 %ymm1,0x80\(%rax\)
|
||||
+[a-f0-9]+: 62 f1 7d 48 6f 10 vmovdqa32 \(%rax\),%zmm2
|
||||
+[a-f0-9]+: c5 .* vpand %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c4 .* vpand %xmm12,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm13,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm3,%xmm14
|
||||
+[a-f0-9]+: c5 .* vpor %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c4 .* vpor %xmm12,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm13,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm3,%xmm14
|
||||
+[a-f0-9]+: c5 .* vpand %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c4 .* vpand %ymm12,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm13,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm3,%ymm14
|
||||
+[a-f0-9]+: c5 .* vpor %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c4 .* vpor %ymm12,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm13,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm3,%ymm14
|
||||
+[a-f0-9]+: c5 .* vpand 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpand 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandd 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandq 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandnd 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandnq 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpord 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vporq 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpxord 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpxorq 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpand 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpand 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandd 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandq 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandnd 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandnq 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpord 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vporq 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpxord 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpxorq 0x80\(%rax\),%ymm2,%ymm3
|
||||
#pass
|
||||
|
|
|
|||
|
|
@ -115,4 +115,76 @@ Disassembly of section .text:
|
|||
+[a-f0-9]+: 62 f1 ff 89 6f d1 vmovdqu16 %xmm1,%xmm2\{%k1\}\{z\}
|
||||
+[a-f0-9]+: 62 f1 7e 89 6f d1 vmovdqu32 %xmm1,%xmm2\{%k1\}\{z\}
|
||||
+[a-f0-9]+: 62 f1 fe 89 6f d1 vmovdqu64 %xmm1,%xmm2\{%k1\}\{z\}
|
||||
+[a-f0-9]+: c5 .* vpand %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c4 .* vpand %xmm12,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm13,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm3,%xmm14
|
||||
+[a-f0-9]+: c5 .* vpor %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c4 .* vpor %xmm12,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm13,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm3,%xmm14
|
||||
+[a-f0-9]+: c5 .* vpand %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c4 .* vpand %ymm12,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm13,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm3,%ymm14
|
||||
+[a-f0-9]+: c5 .* vpor %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c4 .* vpor %ymm12,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm13,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm3,%ymm14
|
||||
+[a-f0-9]+: c5 .* vpand 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpand 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandd 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandq 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandnd 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandnq 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpord 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vporq 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpxord 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpxorq 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpand 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpand 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandd 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandq 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandnd 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandnq 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpord 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vporq 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpxord 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpxorq 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandd %xmm22,%xmm23,%xmm24
|
||||
+[a-f0-9]+: 62 .* vpandq %ymm22,%ymm3,%ymm4
|
||||
+[a-f0-9]+: 62 .* vpandnd %ymm2,%ymm23,%ymm4
|
||||
+[a-f0-9]+: 62 .* vpandnq %xmm2,%xmm3,%xmm24
|
||||
+[a-f0-9]+: 62 .* vpord %xmm22,%xmm23,%xmm24
|
||||
+[a-f0-9]+: 62 .* vporq %ymm22,%ymm3,%ymm4
|
||||
+[a-f0-9]+: 62 .* vpxord %ymm2,%ymm23,%ymm4
|
||||
+[a-f0-9]+: 62 .* vpxorq %xmm2,%xmm3,%xmm24
|
||||
+[a-f0-9]+: 62 .* vpandd %xmm2,%xmm3,%xmm4\{%k5\}
|
||||
+[a-f0-9]+: 62 .* vpandq %ymm12,%ymm3,%ymm4\{%k5\}
|
||||
+[a-f0-9]+: 62 .* vpandnd %ymm2,%ymm13,%ymm4\{%k5\}
|
||||
+[a-f0-9]+: 62 .* vpandnq %xmm2,%xmm3,%xmm14\{%k5\}
|
||||
+[a-f0-9]+: 62 .* vpord %xmm2,%xmm3,%xmm4\{%k5\}
|
||||
+[a-f0-9]+: 62 .* vporq %ymm12,%ymm3,%ymm4\{%k5\}
|
||||
+[a-f0-9]+: 62 .* vpxord %ymm2,%ymm13,%ymm4\{%k5\}
|
||||
+[a-f0-9]+: 62 .* vpxorq %xmm2,%xmm3,%xmm14\{%k5\}
|
||||
+[a-f0-9]+: 62 .* vpandd \(%rax\)\{1to8\},%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandq \(%rax\)\{1to2\},%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandnd \(%rax\)\{1to4\},%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandnq \(%rax\)\{1to4\},%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpord \(%rax\)\{1to8\},%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vporq \(%rax\)\{1to2\},%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpxord \(%rax\)\{1to4\},%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpxorq \(%rax\)\{1to4\},%ymm2,%ymm3
|
||||
#pass
|
||||
|
|
|
|||
|
|
@ -126,3 +126,84 @@ _start:
|
|||
vmovdqu16 %xmm1, %xmm2{%k1}{z}
|
||||
vmovdqu32 %xmm1, %xmm2{%k1}{z}
|
||||
vmovdqu64 %xmm1, %xmm2{%k1}{z}
|
||||
|
||||
vpandd %xmm2, %xmm3, %xmm4
|
||||
vpandq %xmm12, %xmm3, %xmm4
|
||||
vpandnd %xmm2, %xmm13, %xmm4
|
||||
vpandnq %xmm2, %xmm3, %xmm14
|
||||
vpord %xmm2, %xmm3, %xmm4
|
||||
vporq %xmm12, %xmm3, %xmm4
|
||||
vpxord %xmm2, %xmm13, %xmm4
|
||||
vpxorq %xmm2, %xmm3, %xmm14
|
||||
|
||||
vpandd %ymm2, %ymm3, %ymm4
|
||||
vpandq %ymm12, %ymm3, %ymm4
|
||||
vpandnd %ymm2, %ymm13, %ymm4
|
||||
vpandnq %ymm2, %ymm3, %ymm14
|
||||
vpord %ymm2, %ymm3, %ymm4
|
||||
vporq %ymm12, %ymm3, %ymm4
|
||||
vpxord %ymm2, %ymm13, %ymm4
|
||||
vpxorq %ymm2, %ymm3, %ymm14
|
||||
|
||||
vpandd 112(%rax), %xmm2, %xmm3
|
||||
vpandq 112(%rax), %xmm2, %xmm3
|
||||
vpandnd 112(%rax), %xmm2, %xmm3
|
||||
vpandnq 112(%rax), %xmm2, %xmm3
|
||||
vpord 112(%rax), %xmm2, %xmm3
|
||||
vporq 112(%rax), %xmm2, %xmm3
|
||||
vpxord 112(%rax), %xmm2, %xmm3
|
||||
vpxorq 112(%rax), %xmm2, %xmm3
|
||||
|
||||
vpandd 128(%rax), %xmm2, %xmm3
|
||||
vpandq 128(%rax), %xmm2, %xmm3
|
||||
vpandnd 128(%rax), %xmm2, %xmm3
|
||||
vpandnq 128(%rax), %xmm2, %xmm3
|
||||
vpord 128(%rax), %xmm2, %xmm3
|
||||
vporq 128(%rax), %xmm2, %xmm3
|
||||
vpxord 128(%rax), %xmm2, %xmm3
|
||||
vpxorq 128(%rax), %xmm2, %xmm3
|
||||
|
||||
vpandd 96(%rax), %ymm2, %ymm3
|
||||
vpandq 96(%rax), %ymm2, %ymm3
|
||||
vpandnd 96(%rax), %ymm2, %ymm3
|
||||
vpandnq 96(%rax), %ymm2, %ymm3
|
||||
vpord 96(%rax), %ymm2, %ymm3
|
||||
vporq 96(%rax), %ymm2, %ymm3
|
||||
vpxord 96(%rax), %ymm2, %ymm3
|
||||
vpxorq 96(%rax), %ymm2, %ymm3
|
||||
|
||||
vpandd 128(%rax), %ymm2, %ymm3
|
||||
vpandq 128(%rax), %ymm2, %ymm3
|
||||
vpandnd 128(%rax), %ymm2, %ymm3
|
||||
vpandnq 128(%rax), %ymm2, %ymm3
|
||||
vpord 128(%rax), %ymm2, %ymm3
|
||||
vporq 128(%rax), %ymm2, %ymm3
|
||||
vpxord 128(%rax), %ymm2, %ymm3
|
||||
vpxorq 128(%rax), %ymm2, %ymm3
|
||||
|
||||
vpandd %xmm22, %xmm23, %xmm24
|
||||
vpandq %ymm22, %ymm3, %ymm4
|
||||
vpandnd %ymm2, %ymm23, %ymm4
|
||||
vpandnq %xmm2, %xmm3, %xmm24
|
||||
vpord %xmm22, %xmm23, %xmm24
|
||||
vporq %ymm22, %ymm3, %ymm4
|
||||
vpxord %ymm2, %ymm23, %ymm4
|
||||
vpxorq %xmm2, %xmm3, %xmm24
|
||||
|
||||
vpandd %xmm2, %xmm3, %xmm4{%k5}
|
||||
vpandq %ymm12, %ymm3, %ymm4{%k5}
|
||||
vpandnd %ymm2, %ymm13, %ymm4{%k5}
|
||||
vpandnq %xmm2, %xmm3, %xmm14{%k5}
|
||||
vpord %xmm2, %xmm3, %xmm4{%k5}
|
||||
vporq %ymm12, %ymm3, %ymm4{%k5}
|
||||
vpxord %ymm2, %ymm13, %ymm4{%k5}
|
||||
vpxorq %xmm2, %xmm3, %xmm14{%k5}
|
||||
|
||||
vpandd (%rax){1to8}, %ymm2, %ymm3
|
||||
vpandq (%rax){1to2}, %xmm2, %xmm3
|
||||
vpandnd (%rax){1to4}, %xmm2, %xmm3
|
||||
vpandnq (%rax){1to4}, %ymm2, %ymm3
|
||||
vpord (%rax){1to8}, %ymm2, %ymm3
|
||||
vporq (%rax){1to2}, %xmm2, %xmm3
|
||||
vpxord (%rax){1to4}, %xmm2, %xmm3
|
||||
vpxorq (%rax){1to4}, %ymm2, %ymm3
|
||||
|
|
|
|||
|
|
@ -15,4 +15,12 @@ Disassembly of section .text:
|
|||
+[a-f0-9]+: 62 f1 ff 08 6f d1 vmovdqu16 %xmm1,%xmm2
|
||||
+[a-f0-9]+: 62 f1 7e 08 6f d1 vmovdqu32 %xmm1,%xmm2
|
||||
+[a-f0-9]+: 62 f1 fe 08 6f d1 vmovdqu64 %xmm1,%xmm2
|
||||
+[a-f0-9]+: 62 .* vpandd %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: 62 .* vpandq %ymm12,%ymm3,%ymm4
|
||||
+[a-f0-9]+: 62 .* vpandnd %ymm2,%ymm13,%ymm4
|
||||
+[a-f0-9]+: 62 .* vpandnq %xmm2,%xmm3,%xmm14
|
||||
+[a-f0-9]+: 62 .* vpord %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: 62 .* vporq %ymm12,%ymm3,%ymm4
|
||||
+[a-f0-9]+: 62 .* vpxord %ymm2,%ymm13,%ymm4
|
||||
+[a-f0-9]+: 62 .* vpxorq %xmm2,%xmm3,%xmm14
|
||||
#pass
|
||||
|
|
|
|||
|
|
@ -11,3 +11,12 @@ _start:
|
|||
{nooptimize} vmovdqu16 %xmm1, %xmm2
|
||||
{nooptimize} vmovdqu32 %xmm1, %xmm2
|
||||
{nooptimize} vmovdqu64 %xmm1, %xmm2
|
||||
|
||||
{nooptimize} vpandd %xmm2, %xmm3, %xmm4
|
||||
{nooptimize} vpandq %ymm12, %ymm3, %ymm4
|
||||
{nooptimize} vpandnd %ymm2, %ymm13, %ymm4
|
||||
{nooptimize} vpandnq %xmm2, %xmm3, %xmm14
|
||||
{nooptimize} vpord %xmm2, %xmm3, %xmm4
|
||||
{nooptimize} vporq %ymm12, %ymm3, %ymm4
|
||||
{nooptimize} vpxord %ymm2, %ymm13, %ymm4
|
||||
{nooptimize} vpxorq %xmm2, %xmm3, %xmm14
|
||||
|
|
|
|||
|
|
@ -155,6 +155,54 @@ Disassembly of section .text:
|
|||
+[a-f0-9]+: 62 f1 7e 28 7f 48 04 vmovdqu32 %ymm1,0x80\(%rax\)
|
||||
+[a-f0-9]+: 62 f1 fe 28 7f 48 04 vmovdqu64 %ymm1,0x80\(%rax\)
|
||||
+[a-f0-9]+: 62 f1 7d 48 6f 10 vmovdqa32 \(%rax\),%zmm2
|
||||
+[a-f0-9]+: c5 .* vpand %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c4 .* vpand %xmm12,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm13,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm3,%xmm14
|
||||
+[a-f0-9]+: c5 .* vpor %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c4 .* vpor %xmm12,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm13,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm3,%xmm14
|
||||
+[a-f0-9]+: c5 .* vpand %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c4 .* vpand %ymm12,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm13,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm3,%ymm14
|
||||
+[a-f0-9]+: c5 .* vpor %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c4 .* vpor %ymm12,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm13,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm3,%ymm14
|
||||
+[a-f0-9]+: c5 .* vpand 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpand 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandd 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandq 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandnd 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandnq 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpord 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vporq 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpxord 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpxorq 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpand 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpand 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandd 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandq 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandnd 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandnq 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpord 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vporq 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpxord 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpxorq 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 f1 f5 08 55 e9 vandnpd %xmm1,%xmm1,%xmm5
|
||||
+[a-f0-9]+: 62 f1 f5 08 55 e9 vandnpd %xmm1,%xmm1,%xmm5
|
||||
+[a-f0-9]+: 62 f1 7d 28 6f d1 vmovdqa32 %ymm1,%ymm2
|
||||
|
|
|
|||
|
|
@ -155,6 +155,54 @@ Disassembly of section .text:
|
|||
+[a-f0-9]+: 62 f1 7e 28 7f 48 04 vmovdqu32 %ymm1,0x80\(%rax\)
|
||||
+[a-f0-9]+: 62 f1 fe 28 7f 48 04 vmovdqu64 %ymm1,0x80\(%rax\)
|
||||
+[a-f0-9]+: 62 f1 7d 48 6f 10 vmovdqa32 \(%rax\),%zmm2
|
||||
+[a-f0-9]+: c5 .* vpand %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c4 .* vpand %xmm12,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm13,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm3,%xmm14
|
||||
+[a-f0-9]+: c5 .* vpor %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c4 .* vpor %xmm12,%xmm3,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm13,%xmm4
|
||||
+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm3,%xmm14
|
||||
+[a-f0-9]+: c5 .* vpand %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c4 .* vpand %ymm12,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm13,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm3,%ymm14
|
||||
+[a-f0-9]+: c5 .* vpor %ymm2,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c4 .* vpor %ymm12,%ymm3,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm13,%ymm4
|
||||
+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm3,%ymm14
|
||||
+[a-f0-9]+: c5 .* vpand 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpand 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x70\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandd 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandq 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandnd 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpandnq 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpord 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vporq 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpxord 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: 62 .* vpxorq 0x80\(%rax\),%xmm2,%xmm3
|
||||
+[a-f0-9]+: c5 .* vpand 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpand 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpandn 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpor 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: c5 .* vpxor 0x60\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandd 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandq 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandnd 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpandnq 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpord 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vporq 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpxord 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 .* vpxorq 0x80\(%rax\),%ymm2,%ymm3
|
||||
+[a-f0-9]+: 62 f1 f5 08 55 e9 vandnpd %xmm1,%xmm1,%xmm5
|
||||
+[a-f0-9]+: 62 f1 f5 08 55 e9 vandnpd %xmm1,%xmm1,%xmm5
|
||||
+[a-f0-9]+: 62 f1 7d 28 6f d1 vmovdqa32 %ymm1,%ymm2
|
||||
|
|
@ -163,4 +211,12 @@ Disassembly of section .text:
|
|||
+[a-f0-9]+: 62 f1 ff 08 6f d1 vmovdqu16 %xmm1,%xmm2
|
||||
+[a-f0-9]+: 62 f1 7e 08 6f d1 vmovdqu32 %xmm1,%xmm2
|
||||
+[a-f0-9]+: 62 f1 fe 08 6f d1 vmovdqu64 %xmm1,%xmm2
|
||||
+[a-f0-9]+: 62 .* vpandd %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: 62 .* vpandq %ymm12,%ymm3,%ymm4
|
||||
+[a-f0-9]+: 62 .* vpandnd %ymm2,%ymm13,%ymm4
|
||||
+[a-f0-9]+: 62 .* vpandnq %xmm2,%xmm3,%xmm14
|
||||
+[a-f0-9]+: 62 .* vpord %xmm2,%xmm3,%xmm4
|
||||
+[a-f0-9]+: 62 .* vporq %ymm12,%ymm3,%ymm4
|
||||
+[a-f0-9]+: 62 .* vpxord %ymm2,%ymm13,%ymm4
|
||||
+[a-f0-9]+: 62 .* vpxorq %xmm2,%xmm3,%xmm14
|
||||
#pass
|
||||
|
|
|
|||
|
|
@ -13,3 +13,12 @@
|
|||
{evex} vmovdqu16 %xmm1, %xmm2
|
||||
{evex} vmovdqu32 %xmm1, %xmm2
|
||||
{evex} vmovdqu64 %xmm1, %xmm2
|
||||
|
||||
{evex} vpandd %xmm2, %xmm3, %xmm4
|
||||
{evex} vpandq %ymm12, %ymm3, %ymm4
|
||||
{evex} vpandnd %ymm2, %ymm13, %ymm4
|
||||
{evex} vpandnq %xmm2, %xmm3, %xmm14
|
||||
{evex} vpord %xmm2, %xmm3, %xmm4
|
||||
{evex} vporq %ymm12, %ymm3, %ymm4
|
||||
{evex} vpxord %ymm2, %ymm13, %ymm4
|
||||
{evex} vpxorq %xmm2, %xmm3, %xmm14
|
||||
|
|
|
|||
|
|
@ -1,3 +1,9 @@
|
|||
2019-07-01 Jan Beulich <jbeulich@suse.com>
|
||||
|
||||
* i386-opc.tbl (and, or): Add Optimize to forms allowing two
|
||||
register operands.
|
||||
* i386-tbl.h: Re-generate.
|
||||
|
||||
2019-07-01 Jan Beulich <jbeulich@suse.com>
|
||||
|
||||
* i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
|
||||
|
|
|
|||
|
|
@ -3754,9 +3754,9 @@ vrcp14pd, 2, 0x664C, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=1|VexW=2|Bro
|
|||
vrsqrt14pd, 2, 0x664E, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
|
||||
|
||||
vpaddd, 3, 0x66FE, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
|
||||
vpandd, 3, 0x66DB, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
|
||||
vpandd, 3, 0x66DB, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
|
||||
vpandnd, 3, 0x66DF, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
|
||||
vpord, 3, 0x66EB, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
|
||||
vpord, 3, 0x66EB, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
|
||||
vpsubd, 3, 0x66FA, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
|
||||
vpunpckhdq, 3, 0x666A, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
|
||||
vpunpckldq, 3, 0x6662, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
|
||||
|
|
@ -3764,9 +3764,9 @@ vpxord, 3, 0x66EF, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexVVVV=1|Ve
|
|||
|
||||
vpaddq, 3, 0x66D4, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
|
||||
vpandnq, 3, 0x66DF, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
|
||||
vpandq, 3, 0x66DB, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
|
||||
vpandq, 3, 0x66DB, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
|
||||
vpmuludq, 3, 0x66F4, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
|
||||
vporq, 3, 0x66EB, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
|
||||
vporq, 3, 0x66EB, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
|
||||
vpsubq, 3, 0x66FB, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
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||||
vpunpckhqdq, 3, 0x666D, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
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||||
vpunpcklqdq, 3, 0x666C, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
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|
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@ -60419,7 +60419,7 @@ const insn_template i386_optab[] =
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0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1,
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||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
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||||
1, 0, 0, 0, 0, 0, 0, 3, 3, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0 },
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||||
1, 0, 0, 0, 0, 0, 0, 3, 3, 0, 0, 7, 0, 0, 1, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 1, 0, 0,
|
||||
0, 0 } },
|
||||
|
|
@ -60457,7 +60457,7 @@ const insn_template i386_optab[] =
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 3, 3, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
1, 0, 0, 0, 0, 0, 0, 3, 3, 0, 0, 7, 0, 0, 1, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 1, 0, 0,
|
||||
0, 0 } },
|
||||
|
|
@ -60514,7 +60514,7 @@ const insn_template i386_optab[] =
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
|
||||
2, 0, 0, 0, 0, 0, 0, 3, 4, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
2, 0, 0, 0, 0, 0, 0, 3, 4, 0, 0, 7, 0, 0, 1, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 0, 0,
|
||||
0, 0 } },
|
||||
|
|
@ -60533,7 +60533,7 @@ const insn_template i386_optab[] =
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
|
||||
2, 0, 0, 0, 0, 0, 0, 3, 4, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
2, 0, 0, 0, 0, 0, 0, 3, 4, 0, 0, 7, 0, 0, 1, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 0, 0,
|
||||
0, 0 } },
|
||||
|
|
|
|||
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Reference in New Issue