[AArch64][5/8] GAS support BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
2015-08-11 Jiong Wang <jiong.wang@arm.com> bfd/ * reloc.c (BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC): New entry. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry for BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC. gas/ * config/tc-aarch64.c (reloc_table): New relocation modifiers. (md_apply_fix): Support BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC. (aarch64_force_relocation): Likewise. gas/testsuite/ * gas/aarch64/reloc-tlsldm_lo12_nc-1.s: New testcase. * gas/aarch64/reloc-tlsldm_lo12_nc-ilp32-1.s: Likewise. * gas/aarch64/reloc-tlsldm_lo12_nc-1.d: New expectation file. * gas/aarch64/reloc-tlsldm_lo12_nc-ilp32-1.d: Likewise.
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@ -1,3 +1,11 @@
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2015-08-11 Jiong Wang <jiong.wang@arm.com>
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* reloc.c (BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC): New entry.
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* bfd-in2.h: Regenerate.
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* libbfd.h: Regenerate.
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* elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry for
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BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC.
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2015-08-11 Jiong Wang <jiong.wang@arm.com>
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* elfnn-aarch64.c (IS_AARCH64_TLS_RELOC): Recognize
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@ -5794,6 +5794,11 @@ BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21. */
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/* AArch64 TLS INITIAL EXEC relocation. */
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BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19,
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/* Unsigned 12 bit byte offset to global offset table entry for a symbols
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tls_index structure. Used in conjunction with
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BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21. */
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BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC,
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/* GOT entry page address for AArch64 TLS Local Dynamic, used with ADRP
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instruction. */
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BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21,
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@ -1026,6 +1026,21 @@ static reloc_howto_type elfNN_aarch64_howto_table[] =
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0x1ffffc, /* dst_mask */
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FALSE), /* pcrel_offset */
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/* ADD: GOT offset G(S) & 0xff8 [no overflow check] */
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HOWTO (AARCH64_R (TLSLD_ADD_LO12_NC), /* type */
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0, /* rightshift */
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2, /* size (0 = byte, 1 = short, 2 = long) */
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12, /* bitsize */
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FALSE, /* pc_relative */
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0, /* bitpos */
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complain_overflow_dont, /* complain_on_overflow */
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bfd_elf_generic_reloc, /* special_function */
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AARCH64_R_STR (TLSLD_ADD_LO12_NC), /* name */
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FALSE, /* partial_inplace */
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0xfff, /* src_mask */
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0xfff, /* dst_mask */
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FALSE), /* pcrel_offset */
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/* Get to the page for the GOT entry for the symbol
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(G(S) - P) using an ADRP instruction. */
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HOWTO (AARCH64_R (TLSLD_ADR_PAGE21), /* type */
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@ -2759,6 +2759,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
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"BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC",
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"BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC",
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"BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19",
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"BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC",
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"BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21",
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"BFD_RELOC_AARCH64_TLSLD_ADR_PREL21",
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"BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2",
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@ -6843,6 +6843,12 @@ ENUM
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BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
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ENUMDOC
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AArch64 TLS INITIAL EXEC relocation.
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ENUM
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BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
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ENUMDOC
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Unsigned 12 bit byte offset to global offset table entry for a symbols
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tls_index structure. Used in conjunction with
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BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21.
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ENUM
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BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
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ENUMDOC
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@ -1,3 +1,9 @@
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2015-08-11 Jiong Wang <jiong.wang@arm.com>
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* config/tc-aarch64.c (reloc_table): New relocation modifiers.
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(md_apply_fix): Support BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC.
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(aarch64_force_relocation): Likewise.
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2015-08-11 Jiong Wang <jiong.wang@arm.com>
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* config/tc-aarch64.c (reloc_table): New relocation modifiers.
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@ -2513,6 +2513,15 @@ static struct reloc_table_entry reloc_table[] = {
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0,
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0},
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/* 12 bit offset into the page containing GOT TLS entry for a symbol */
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{"tlsldm_lo12_nc", 0,
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0, /* adr_type */
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0,
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0,
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BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC,
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0,
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0},
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/* Get to the page containing GOT TLS entry for a symbol */
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{"gottprel", 0,
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0, /* adr_type */
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@ -6778,6 +6787,7 @@ md_apply_fix (fixS * fixP, valueT * valP, segT seg)
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case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC:
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case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
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case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19:
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case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC:
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case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21:
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case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21:
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case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
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@ -6989,6 +6999,7 @@ aarch64_force_relocation (struct fix *fixp)
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case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC:
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case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
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case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19:
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case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC:
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case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21:
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case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21:
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case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
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@ -1,3 +1,10 @@
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2015-08-11 Jiong Wang <jiong.wang@arm.com>
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* gas/aarch64/reloc-tlsldm_lo12_nc-1.s: New testcase.
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* gas/aarch64/reloc-tlsldm_lo12_nc-ilp32-1.s: Likewise.
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* gas/aarch64/reloc-tlsldm_lo12_nc-1.d: New expectation file.
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* gas/aarch64/reloc-tlsldm_lo12_nc-ilp32-1.d: Likewise.
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2015-08-11 Jiong Wang <jiong.wang@arm.com>
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* gas/aarch64/reloc-tlsldm-page-1.s: New testcase.
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10
gas/testsuite/gas/aarch64/reloc-tlsldm_lo12_nc-1.d
Normal file
10
gas/testsuite/gas/aarch64/reloc-tlsldm_lo12_nc-1.d
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@ -0,0 +1,10 @@
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#objdump: -dr
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.*: file format .*
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Disassembly of section \.text:
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0000000000000000 <.*>:
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0: 91000000 add x0, x0, #0x0
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0: R_AARCH64_TLSLD_ADD_LO12_NC x
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5
gas/testsuite/gas/aarch64/reloc-tlsldm_lo12_nc-1.s
Normal file
5
gas/testsuite/gas/aarch64/reloc-tlsldm_lo12_nc-1.s
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@ -0,0 +1,5 @@
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// Test file for AArch64 GAS -- reloc 519
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func:
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// BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
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add x0, x0, #:tlsldm_lo12_nc:x
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gas/testsuite/gas/aarch64/reloc-tlsldm_lo12_nc-ilp32-1.d
Normal file
11
gas/testsuite/gas/aarch64/reloc-tlsldm_lo12_nc-ilp32-1.d
Normal file
@ -0,0 +1,11 @@
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#as: -mabi=ilp32
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#objdump: -dr
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.*: file format .*
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Disassembly of section \.text:
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00000000 <.*>:
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0: 91000000 add x0, x0, #0x0
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0: R_AARCH64_P32_TLSLD_ADD_LO12_NC x
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gas/testsuite/gas/aarch64/reloc-tlsldm_lo12_nc-ilp32-1.s
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5
gas/testsuite/gas/aarch64/reloc-tlsldm_lo12_nc-ilp32-1.s
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// Test file for AArch64 GAS -- reloc 85
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func:
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// BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
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add x0, x0, #:tlsldm_lo12_nc:x
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