x86: slightly rearrange struct insn_template

This avoids holes between the individual fields, (potentially) shrinking
the overall template table size by 4 bytes per entry.

opcodes/ChangeLog

@@ -1,3 +1,11 @@
+2019-10-30  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-gen.c (output_i386_opcode): Change order of fields
+	emitted to output.
+	* i386-opc.h (struct insn_template): Move operands field.
+	Convert extension_opcode field to unsigned short.
+	* i386-tbl.h: Re-generate.
+
 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 
 	* i386-gen.c (process_i386_opcode_modifier): Report bogus uses

opcodes/i386-gen.c

@@ -1294,8 +1294,7 @@ output_i386_opcode (FILE *table, const char *name, char *str,
     }
 
   fprintf (table, "  { \"%s\", %s, %s, %s, %s,\n",
-	   name, operands, base_opcode, extension_opcode,
+	   name, base_opcode, extension_opcode, opcode_length, operands);
-	   opcode_length);
 
   process_i386_cpu_flag (table, cpu_flags, 0, ",", "    ", lineno);
 

opcodes/i386-opc.h

@@ -852,9 +852,6 @@ typedef struct insn_template
   /* instruction name sans width suffix ("mov" for movl insns) */
   char *name;
 
-  /* how many operands */
-  unsigned int operands;
-
   /* base_opcode is the fundamental opcode byte without optional
      prefix(es).  */
   unsigned int base_opcode;
@@ -871,12 +868,15 @@ typedef struct insn_template
      AMD 3DNow! instructions.
      If this template has no extension opcode (the usual case) use None
      Instructions */
-  unsigned int extension_opcode;
+  unsigned short extension_opcode;
 #define None 0xffff		/* If no extension_opcode is possible.  */
 
   /* Opcode length.  */
   unsigned char opcode_length;
 
+  /* how many operands */
+  unsigned char operands;
+
   /* cpu feature flags */
   i386_cpu_flags cpu_flags;