x86: slightly rearrange struct insn_template
This avoids holes between the individual fields, (potentially) shrinking the overall template table size by 4 bytes per entry.
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@ -1,3 +1,11 @@
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2019-10-30 Jan Beulich <jbeulich@suse.com>
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* i386-gen.c (output_i386_opcode): Change order of fields
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emitted to output.
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* i386-opc.h (struct insn_template): Move operands field.
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Convert extension_opcode field to unsigned short.
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* i386-tbl.h: Re-generate.
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2019-10-30 Jan Beulich <jbeulich@suse.com>
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* i386-gen.c (process_i386_opcode_modifier): Report bogus uses
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@ -1294,8 +1294,7 @@ output_i386_opcode (FILE *table, const char *name, char *str,
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}
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fprintf (table, " { \"%s\", %s, %s, %s, %s,\n",
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name, operands, base_opcode, extension_opcode,
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opcode_length);
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name, base_opcode, extension_opcode, opcode_length, operands);
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process_i386_cpu_flag (table, cpu_flags, 0, ",", " ", lineno);
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@ -852,9 +852,6 @@ typedef struct insn_template
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/* instruction name sans width suffix ("mov" for movl insns) */
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char *name;
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/* how many operands */
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unsigned int operands;
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/* base_opcode is the fundamental opcode byte without optional
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prefix(es). */
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unsigned int base_opcode;
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@ -871,12 +868,15 @@ typedef struct insn_template
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AMD 3DNow! instructions.
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If this template has no extension opcode (the usual case) use None
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Instructions */
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unsigned int extension_opcode;
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unsigned short extension_opcode;
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#define None 0xffff /* If no extension_opcode is possible. */
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/* Opcode length. */
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unsigned char opcode_length;
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/* how many operands */
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unsigned char operands;
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/* cpu feature flags */
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i386_cpu_flags cpu_flags;
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7824
opcodes/i386-tbl.h
7824
opcodes/i386-tbl.h
File diff suppressed because it is too large
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