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* autoconf correction 

* merge from internal repo -> sourceware

2000-03-02  Frank Ch. Eigler  <fche@redhat.com>

	* configure: Regenerated.

Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>

	* interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
	calls, conditional on the simulator being in verbose mode.
This commit is contained in:
Frank Ch. Eigler 2000-03-02 18:14:02 +00:00
parent 58fddbac5a
commit a3027dd748
4 changed files with 193 additions and 167 deletions
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9
sim/mips/ChangeLog
View File

@ -1,3 +1,12 @@
2000-03-02 Frank Ch. Eigler <fche@redhat.com>
* configure: Regenerated.
Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
* interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
calls, conditional on the simulator being in verbose mode.
Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
* sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary

322
sim/mips/configure vendored
View File

File diff suppressed because it is too large Load Diff

7
sim/mips/interp.c
View File

@ -2078,6 +2078,9 @@ store_fpr (SIM_DESC sd,
fmt = fmt_uninterpreted;
case fmt_single :
case fmt_word :
if (STATE_VERBOSE_P(SD))
sim_io_eprintf (SD, "Warning: PC 0x%s: interp.c store_fpr DEADCODE\n",
pr_addr(cia));
FGR[fpr] = (((uword64)0xDEADC0DE << 32) | (value & 0xFFFFFFFF));
FPR_STATE[fpr] = fmt;
break;
@ -3225,6 +3228,10 @@ decode_coproc (SIM_DESC sd,
/* 28 = TagLo R4000 VR4100 VR4300 */
/* 29 = TagHi R4000 VR4100 VR4300 */
/* 30 = ErrorEPC R4000 VR4100 VR4300 */
if (STATE_VERBOSE_P(SD))
sim_io_eprintf (SD,
"Warning: PC 0x%s:interp.c decode_coproc DEADC0DE\n",
(unsigned)cia);
GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
/* CPR[0,rd] = GPR[rt]; */
default:

22
sim/mips/mips.igen
View File

@ -3031,7 +3031,13 @@
else if ((FS & 0x1) == 0)
PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
else
PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
{
if (STATE_VERBOSE_P(SD))
sim_io_eprintf (SD,
"Warning: PC 0x%x: semantic_DMxC1_COP1Sa 32-bit use of odd FPR number\n",
CIA);
PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
}
}
}
010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64::DMxC1
@ -3055,7 +3061,12 @@
else if ((FS & 0x1) == 0)
GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
else
GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
{
if (STATE_VERBOSE_P(SD))
sim_io_eprintf (SD,
"Warning: PC 0x%x: DMxC1 32-bit use of odd FPR number\n", CIA);
GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
}
}
}
@ -3194,7 +3205,12 @@
if (X)
{ /*MTC1*/
if (SizeFGR() == 64)
PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
{
if (STATE_VERBOSE_P(SD))
sim_io_eprintf (SD,
"Warning: PC 0x%x: MTC1 not DMTC1 with 64 bit regs\n", CIA);
PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
}
else
PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
}