* config/tc-mips.c (mips_opts): Fix comment, all ASE fields are set
to -1. (file_ase_mips16): New veriable. (mips_eabi64): Remove. (CPU_HAS_MIPS16): New define. (CPU_HAS_MDMX): Fix data type. (md_begin): Code cleanup. Use file_ase_mips16. (mips_elf_final_processing): Handle mips16 header flag. Handle EABI flag without intermediate variable.
This commit is contained in:
Thiemo Seufer
parent
437ee9d5ca
commit
a4672219e1
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@ -1,3 +1,15 @@
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2002-06-08 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
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* config/tc-mips.c (mips_opts): Fix comment, all ASE fields are set
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to -1.
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(file_ase_mips16): New veriable.
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(mips_eabi64): Remove.
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(CPU_HAS_MIPS16): New define.
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(CPU_HAS_MDMX): Fix data type.
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(md_begin): Code cleanup. Use file_ase_mips16.
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(mips_elf_final_processing): Handle mips16 header flag.
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Handle EABI flag without intermediate variable.
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2002-06-08 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
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* doc/as.texinfo: Update MIPS documentation.
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@ -186,7 +186,7 @@ static int file_mips_gp32 = -1;
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static int file_mips_fp32 = -1;
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/* This is the struct we use to hold the current set of options. Note
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that we must set the isa field to ISA_UNKNOWN and the mips16 field to
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that we must set the isa field to ISA_UNKNOWN and the ASE fields to
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-1 to indicate that they have not been initialized. */
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static struct mips_set_options mips_opts =
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@ -203,6 +203,10 @@ unsigned long mips_cprmask[4];
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/* MIPS ISA we are using for this output file. */
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static int file_mips_isa = ISA_UNKNOWN;
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/* True if -mips16 was passed or implied by arguments passed on the
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command line (e.g., by -march). */
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static int file_ase_mips16;
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/* True if -mips3d was passed or implied by arguments passed on the
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command line (e.g., by -march). */
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static int file_ase_mips3d;
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@ -221,9 +225,6 @@ static int mips_arch = CPU_UNKNOWN;
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are optimizing. */
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static int mips_tune = CPU_UNKNOWN;
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/* Whether we should mark the file EABI64 or EABI32. */
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static int mips_eabi64 = 0;
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/* If they asked for mips1 or mips2 and a cpu that is
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mips3 or greater, then mark the object file 32BITMODE. */
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static int mips_32bitmode = 0;
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@ -277,12 +278,16 @@ static int mips_32bitmode = 0;
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#define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
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/* Return true if the given CPU supports the MIPS16 ASE. */
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#define CPU_HAS_MIPS16(cpu) \
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(strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0)
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/* Return true if the given CPU supports the MIPS3D ASE. */
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#define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
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)
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/* Return true if the given CPU supports the MDMX ASE. */
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#define CPU_HAS_MDMX(cpu) (0 \
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#define CPU_HAS_MDMX(cpu) (false \
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)
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/* Whether the processor uses hardware interlocks to protect
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@ -10419,7 +10424,6 @@ mips_after_parse_args ()
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const char *cpu;
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char *a = NULL;
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int mips_isa_from_cpu;
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int target_cpu_had_mips16 = 0;
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const struct mips_cpu_info *ci;
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/* GP relative stuff not working for PE */
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@ -10440,15 +10444,6 @@ mips_after_parse_args ()
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cpu = a;
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}
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if (strncmp (cpu, "mips16", sizeof "mips16" - 1) == 0)
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{
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target_cpu_had_mips16 = 1;
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cpu += sizeof "mips16" - 1;
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}
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if (mips_opts.mips16 < 0)
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mips_opts.mips16 = target_cpu_had_mips16;
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/* Backward compatibility for historic -mcpu= option. Check for
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incompatible options, warn if -mcpu is used. */
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if (mips_cpu != CPU_UNKNOWN
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@ -10611,13 +10606,6 @@ mips_after_parse_args ()
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if (mips_opts.isa == ISA_MIPS1 && mips_trap)
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as_bad (_("trap exception not supported at ISA 1"));
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/* Set the EABI kind based on the ISA before the user gets
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to change the ISA with directives. This isn't really
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the best, but then neither is basing the abi on the isa. */
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if (ISA_HAS_64BIT_REGS (mips_opts.isa)
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&& mips_opts.abi == EABI_ABI)
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mips_eabi64 = 1;
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/* If they asked for mips1 or mips2 and a cpu that is
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mips3 or greater, then mark the object file 32BITMODE. */
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if (mips_isa_from_cpu != ISA_UNKNOWN
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@ -10627,10 +10615,12 @@ mips_after_parse_args ()
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/* If the selected architecture includes support for ASEs, enable
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generation of code for them. */
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if (mips_opts.mips16 == -1)
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mips_opts.mips16 = (CPU_HAS_MIPS16 (mips_arch)) ? 1 : 0;
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if (mips_opts.ase_mips3d == -1)
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mips_opts.ase_mips3d = CPU_HAS_MIPS3D (mips_arch);
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mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (mips_arch)) ? 1 : 0;
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if (mips_opts.ase_mdmx == -1)
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mips_opts.ase_mdmx = CPU_HAS_MDMX (mips_arch);
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mips_opts.ase_mdmx = (CPU_HAS_MDMX (mips_arch)) ? 1 : 0;
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if (file_mips_gp32 < 0)
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file_mips_gp32 = 0;
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@ -10639,6 +10629,7 @@ mips_after_parse_args ()
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file_mips_isa = mips_opts.isa;
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file_mips_abi = mips_opts.abi;
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file_ase_mips16 = mips_opts.mips16;
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file_ase_mips3d = mips_opts.ase_mips3d;
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file_ase_mdmx = mips_opts.ase_mdmx;
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mips_opts.gp32 = file_mips_gp32;
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@ -11677,10 +11668,6 @@ s_mipsset (x)
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{
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mips_opts.nobopt = 1;
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}
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else if (strcmp (name, "mdmx") == 0)
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mips_opts.ase_mdmx = 1;
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else if (strcmp (name, "nomdmx") == 0)
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mips_opts.ase_mdmx = 0;
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else if (strcmp (name, "mips16") == 0
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|| strcmp (name, "MIPS-16") == 0)
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mips_opts.mips16 = 1;
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@ -11691,6 +11678,10 @@ s_mipsset (x)
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mips_opts.ase_mips3d = 1;
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else if (strcmp (name, "nomips3d") == 0)
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mips_opts.ase_mips3d = 0;
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else if (strcmp (name, "mdmx") == 0)
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mips_opts.ase_mdmx = 1;
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else if (strcmp (name, "nomdmx") == 0)
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mips_opts.ase_mdmx = 0;
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else if (strncmp (name, "mips", 4) == 0)
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{
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int isa;
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@ -13206,6 +13197,8 @@ mips_elf_final_processing ()
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elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
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/* Set MIPS ELF flags for ASEs. */
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if (file_ase_mips16)
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elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
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#if 0 /* XXX FIXME */
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if (file_ase_mips3d)
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elf_elfheader (stdoutput)->e_flags |= ???;
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@ -13222,7 +13215,9 @@ mips_elf_final_processing ()
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elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
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else if (file_mips_abi == EABI_ABI)
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{
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if (mips_eabi64)
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/* Set the EABI kind based on the ISA. This isn't really
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the best, but then neither is basing the abi on the isa. */
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if (ISA_HAS_64BIT_REGS (file_mips_isa))
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elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
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else
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elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
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