gas/
* config/tc-mips.c (append_method): New enum. (can_swap_branch_p, get_append_method): New functions. (append_insn): Use get_append_method to decide how the instruction should be added.
This commit is contained in:
Richard Sandiford
parent
0d1b033387
commit
a4e064680b
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@ -1,3 +1,10 @@
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2011-06-29 Richard Sandiford <rdsandiford@googlemail.com>
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* config/tc-mips.c (append_method): New enum.
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(can_swap_branch_p, get_append_method): New functions.
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(append_insn): Use get_append_method to decide how the instruction
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should be added.
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2011-06-29 Richard Sandiford <rdsandiford@googlemail.com>
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* config/tc-mips.c (append_insn): Remove bogus goto.
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@ -121,6 +121,21 @@ extern int target_big_endian;
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? ".rodata" \
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: (abort (), ""))
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/* Ways in which an instruction can be "appended" to the output. */
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enum append_method {
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/* Just add it normally. */
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APPEND_ADD,
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/* Add it normally and then add a nop. */
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APPEND_ADD_WITH_NOP,
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/* Turn an instruction with a delay slot into a "compact" version. */
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APPEND_ADD_COMPACT,
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/* Insert the instruction before the last one. */
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APPEND_SWAP
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};
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/* Information about an instruction, including its format, operands
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and fixups. */
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struct mips_cl_insn
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@ -3073,6 +3088,168 @@ fix_loongson2f (struct mips_cl_insn * ip)
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fix_loongson2f_jump (ip);
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}
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/* IP is a branch that has a delay slot, and we need to fill it
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automatically. Return true if we can do that by swapping IP
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with the previous instruction. */
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static bfd_boolean
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can_swap_branch_p (struct mips_cl_insn *ip)
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{
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unsigned long pinfo, prev_pinfo;
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unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
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/* -O2 and above is required for this optimization. */
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if (mips_optimize < 2)
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return FALSE;
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/* If we have seen .set volatile or .set nomove, don't optimize. */
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if (mips_opts.nomove)
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return FALSE;
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/* We can't swap if the previous instruction's position is fixed. */
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if (history[0].fixed_p)
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return FALSE;
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/* If the previous previous insn was in a .set noreorder, we can't
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swap. Actually, the MIPS assembler will swap in this situation.
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However, gcc configured -with-gnu-as will generate code like
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.set noreorder
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lw $4,XXX
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.set reorder
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INSN
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bne $4,$0,foo
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in which we can not swap the bne and INSN. If gcc is not configured
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-with-gnu-as, it does not output the .set pseudo-ops. */
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if (history[1].noreorder_p)
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return FALSE;
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/* If the previous instruction had a fixup in mips16 mode, we can not
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swap. This normally means that the previous instruction was a 4
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byte branch anyhow. */
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if (mips_opts.mips16 && history[0].fixp[0])
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return FALSE;
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/* If the branch is itself the target of a branch, we can not swap.
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We cheat on this; all we check for is whether there is a label on
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this instruction. If there are any branches to anything other than
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a label, users must use .set noreorder. */
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if (seg_info (now_seg)->label_list)
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return FALSE;
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/* If the previous instruction is in a variant frag other than this
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branch's one, we cannot do the swap. This does not apply to the
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mips16, which uses variant frags for different purposes. */
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if (!mips_opts.mips16
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&& history[0].frag
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&& history[0].frag->fr_type == rs_machine_dependent)
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return FALSE;
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/* We do not swap with a trap instruction, since it complicates trap
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handlers to have the trap instruction be in a delay slot. */
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prev_pinfo = history[0].insn_mo->pinfo;
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if (prev_pinfo & INSN_TRAP)
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return FALSE;
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/* If the previous instruction is a sync, sync.l, or sync.p, we can
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not swap. */
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if (prev_pinfo & INSN_SYNC)
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return FALSE;
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/* If the previous instruction is an ERET or DERET, avoid the swap. */
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if (history[0].insn_opcode == INSN_ERET)
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return FALSE;
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if (history[0].insn_opcode == INSN_DERET)
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return FALSE;
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/* Check for conflicts between the branch and the instructions
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before the candidate delay slot. */
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if (nops_for_insn (0, history + 1, ip) > 0)
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return FALSE;
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/* Check for conflicts between the swapped sequence and the
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target of the branch. */
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if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
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return FALSE;
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/* If the branch reads a register that the previous
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instruction sets, we can not swap. */
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gpr_read = gpr_read_mask (ip);
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prev_gpr_write = gpr_write_mask (&history[0]);
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if (gpr_read & prev_gpr_write)
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return FALSE;
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/* If the branch writes a register that the previous
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instruction sets, we can not swap. */
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gpr_write = gpr_write_mask (ip);
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if (gpr_write & prev_gpr_write)
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return FALSE;
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/* If the branch writes a register that the previous
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instruction reads, we can not swap. */
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prev_gpr_read = gpr_read_mask (&history[0]);
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if (gpr_write & prev_gpr_read)
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return FALSE;
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/* If one instruction sets a condition code and the
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other one uses a condition code, we can not swap. */
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pinfo = ip->insn_mo->pinfo;
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if ((pinfo & INSN_READ_COND_CODE)
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&& (prev_pinfo & INSN_WRITE_COND_CODE))
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return FALSE;
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if ((pinfo & INSN_WRITE_COND_CODE)
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&& (prev_pinfo & INSN_READ_COND_CODE))
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return FALSE;
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/* If the previous instruction uses the PC, we can not swap. */
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if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC))
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return FALSE;
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return TRUE;
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}
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/* Decide how we should add IP to the instruction stream. */
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static enum append_method
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get_append_method (struct mips_cl_insn *ip)
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{
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unsigned long pinfo;
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/* The relaxed version of a macro sequence must be inherently
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hazard-free. */
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if (mips_relax.sequence == 2)
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return APPEND_ADD;
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/* We must not dabble with instructions in a ".set norerorder" block. */
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if (mips_opts.noreorder)
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return APPEND_ADD;
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/* Otherwise, it's our responsibility to fill branch delay slots. */
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pinfo = ip->insn_mo->pinfo;
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if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
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|| (pinfo & INSN_COND_BRANCH_DELAY))
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{
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if (can_swap_branch_p (ip))
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return APPEND_SWAP;
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if (mips_opts.mips16
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&& ISA_SUPPORTS_MIPS16E
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&& (pinfo & INSN_UNCOND_BRANCH_DELAY)
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&& (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)))
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return APPEND_ADD_COMPACT;
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return APPEND_ADD_WITH_NOP;
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}
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/* We don't bother trying to track the target of branches, so there's
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nothing we can use to fill a branch-likely slot. */
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if (pinfo & INSN_COND_BRANCH_LIKELY)
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return APPEND_ADD_WITH_NOP;
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return APPEND_ADD;
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}
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/* IP is a MIPS16 instruction whose opcode we have just changed.
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Point IP->insn_mo to the new opcode's definition. */
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@ -3101,9 +3278,8 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
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{
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unsigned long prev_pinfo, pinfo;
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unsigned long prev_pinfo2, pinfo2;
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relax_stateT prev_insn_frag_type = 0;
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bfd_boolean relaxed_branch = FALSE;
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segment_info_type *si = seg_info (now_seg);
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enum append_method method;
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if (mips_fix_loongson2f)
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fix_loongson2f (ip);
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@ -3273,6 +3449,8 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
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}
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}
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method = get_append_method (ip);
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#ifdef OBJ_ELF
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/* The value passed to dwarf2_emit_insn is the distance between
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the beginning of the current instruction and the address that
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@ -3282,10 +3460,6 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
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dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0);
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#endif
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/* Record the frag type before frag_var. */
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if (history[0].frag)
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prev_insn_frag_type = history[0].frag->fr_type;
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if (address_expr
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&& *reloc_type == BFD_RELOC_16_PCREL_S2
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&& (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
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@ -3469,158 +3643,59 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
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mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
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mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
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if (mips_relax.sequence != 2 && !mips_opts.noreorder)
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switch (method)
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{
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/* Filling the branch delay slot is more complex. We try to
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switch the branch with the previous instruction, which we can
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do if the previous instruction does not set up a condition
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that the branch tests and if the branch is not itself the
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target of any branch. */
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if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
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|| (pinfo & INSN_COND_BRANCH_DELAY))
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{
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if (mips_optimize < 2
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/* If we have seen .set volatile or .set nomove, don't
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optimize. */
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|| mips_opts.nomove != 0
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/* We can't swap if the previous instruction's position
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is fixed. */
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|| history[0].fixed_p
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/* If the previous previous insn was in a .set
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noreorder, we can't swap. Actually, the MIPS
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assembler will swap in this situation. However, gcc
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configured -with-gnu-as will generate code like
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.set noreorder
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lw $4,XXX
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.set reorder
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INSN
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bne $4,$0,foo
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in which we can not swap the bne and INSN. If gcc is
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not configured -with-gnu-as, it does not output the
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.set pseudo-ops. */
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|| history[1].noreorder_p
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/* If the branch is itself the target of a branch, we
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can not swap. We cheat on this; all we check for is
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whether there is a label on this instruction. If
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there are any branches to anything other than a
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label, users must use .set noreorder. */
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|| si->label_list != NULL
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/* If the previous instruction is in a variant frag
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other than this branch's one, we cannot do the swap.
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This does not apply to the mips16, which uses variant
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frags for different purposes. */
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|| (! mips_opts.mips16
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&& prev_insn_frag_type == rs_machine_dependent)
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/* Check for conflicts between the branch and the instructions
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before the candidate delay slot. */
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|| nops_for_insn (0, history + 1, ip) > 0
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/* Check for conflicts between the swapped sequence and the
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target of the branch. */
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|| nops_for_sequence (2, 0, history + 1, ip, history) > 0
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/* We do not swap with a trap instruction, since it
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complicates trap handlers to have the trap
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instruction be in a delay slot. */
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|| (prev_pinfo & INSN_TRAP)
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/* If the branch reads a register that the previous
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instruction sets, we can not swap. */
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|| (gpr_read_mask (ip) & gpr_write_mask (&history[0])) != 0
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/* If the branch writes a register that the previous
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instruction sets, we can not swap. */
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|| (gpr_write_mask (ip) & gpr_write_mask (&history[0])) != 0
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/* If the branch writes a register that the previous
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instruction reads, we can not swap. */
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|| (gpr_write_mask (ip) & gpr_read_mask (&history[0])) != 0
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/* If one instruction sets a condition code and the
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other one uses a condition code, we can not swap. */
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|| ((pinfo & INSN_READ_COND_CODE)
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&& (prev_pinfo & INSN_WRITE_COND_CODE))
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|| ((pinfo & INSN_WRITE_COND_CODE)
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&& (prev_pinfo & INSN_READ_COND_CODE))
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/* If the previous instruction uses the PC, we can not
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swap. */
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|| (mips_opts.mips16
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&& (prev_pinfo & MIPS16_INSN_READ_PC))
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/* If the previous instruction had a fixup in mips16
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mode, we can not swap. This normally means that the
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previous instruction was a 4 byte branch anyhow. */
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|| (mips_opts.mips16 && history[0].fixp[0])
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/* If the previous instruction is a sync, sync.l, or
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sync.p, we can not swap. */
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|| (prev_pinfo & INSN_SYNC)
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/* If the previous instruction is an ERET or
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DERET, avoid the swap. */
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|| (history[0].insn_opcode == INSN_ERET)
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|| (history[0].insn_opcode == INSN_DERET))
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{
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if (mips_opts.mips16
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&& (pinfo & INSN_UNCOND_BRANCH_DELAY)
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&& (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))
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&& ISA_SUPPORTS_MIPS16E)
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{
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/* Convert MIPS16 jr/jalr into a "compact" jump. */
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ip->insn_opcode |= 0x0080;
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find_altered_mips16_opcode (ip);
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install_insn (ip);
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insert_into_history (0, 1, ip);
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}
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else
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{
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/* We could do even better for unconditional branches to
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portions of this object file; we could pick up the
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instruction at the destination, put it in the delay
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slot, and bump the destination address. */
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insert_into_history (0, 1, ip);
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emit_nop ();
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}
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if (mips_relax.sequence)
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mips_relax.sizes[mips_relax.sequence - 1] += 4;
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}
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else
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{
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/* It looks like we can actually do the swap. */
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struct mips_cl_insn delay = history[0];
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if (mips_opts.mips16)
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{
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know (delay.frag == ip->frag);
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move_insn (ip, delay.frag, delay.where);
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move_insn (&delay, ip->frag, ip->where + insn_length (ip));
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}
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else if (relaxed_branch)
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{
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/* Add the delay slot instruction to the end of the
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current frag and shrink the fixed part of the
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original frag. If the branch occupies the tail of
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the latter, move it backwards to cover the gap. */
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delay.frag->fr_fix -= 4;
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if (delay.frag == ip->frag)
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move_insn (ip, ip->frag, ip->where - 4);
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add_fixed_insn (&delay);
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}
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else
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{
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move_insn (&delay, ip->frag, ip->where);
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move_insn (ip, history[0].frag, history[0].where);
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}
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history[0] = *ip;
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delay.fixed_p = 1;
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insert_into_history (0, 1, &delay);
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}
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}
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else if (pinfo & INSN_COND_BRANCH_LIKELY)
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{
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/* We don't yet optimize a branch likely. What we should do
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is look at the target, copy the instruction found there
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into the delay slot, and increment the branch to jump to
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the next instruction. */
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insert_into_history (0, 1, ip);
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emit_nop ();
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}
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else
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insert_into_history (0, 1, ip);
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case APPEND_ADD:
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insert_into_history (0, 1, ip);
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break;
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case APPEND_ADD_WITH_NOP:
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insert_into_history (0, 1, ip);
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emit_nop ();
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if (mips_relax.sequence)
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mips_relax.sizes[mips_relax.sequence - 1] += 4;
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break;
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case APPEND_ADD_COMPACT:
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/* Convert MIPS16 jr/jalr into a "compact" jump. */
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gas_assert (mips_opts.mips16);
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ip->insn_opcode |= 0x0080;
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find_altered_mips16_opcode (ip);
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install_insn (ip);
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insert_into_history (0, 1, ip);
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break;
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case APPEND_SWAP:
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{
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struct mips_cl_insn delay = history[0];
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if (mips_opts.mips16)
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{
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know (delay.frag == ip->frag);
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move_insn (ip, delay.frag, delay.where);
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move_insn (&delay, ip->frag, ip->where + insn_length (ip));
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}
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else if (relaxed_branch)
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{
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/* Add the delay slot instruction to the end of the
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current frag and shrink the fixed part of the
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original frag. If the branch occupies the tail of
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the latter, move it backwards to cover the gap. */
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delay.frag->fr_fix -= 4;
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if (delay.frag == ip->frag)
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move_insn (ip, ip->frag, ip->where - 4);
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add_fixed_insn (&delay);
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}
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else
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{
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move_insn (&delay, ip->frag, ip->where);
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move_insn (ip, history[0].frag, history[0].where);
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}
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history[0] = *ip;
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delay.fixed_p = 1;
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insert_into_history (0, 1, &delay);
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}
|
||||
break;
|
||||
}
|
||||
else
|
||||
insert_into_history (0, 1, ip);
|
||||
|
||||
/* If we have just completed an unconditional branch, clear the history. */
|
||||
if ((history[1].insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY)
|
||||
|
|
|
|||
Loading…
Reference in New Issue