x86: Add Intel ENCLV to assembler and disassembler
gas/ * testsuite/gas/i386/se1.s: Add enclv. * testsuite/gas/i386/x86-64-se1.s: Likewise. * testsuite/gas/i386/se1.d: Updated. * testsuite/gas/i386/x86-64-se1.d: Likewise. opcodes/ * i386-dis.c (rm_table): Add enclv. * i386-opc.tbl: Add enclv. * i386-tbl.h: Regenerated.
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H.J. Lu
parent
f8740dc531
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a4e78aa5fe
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@ -1,3 +1,10 @@
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2018-10-05 H.J. Lu <hongjiu.lu@intel.com>
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* testsuite/gas/i386/se1.s: Add enclv.
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* testsuite/gas/i386/x86-64-se1.s: Likewise.
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* testsuite/gas/i386/se1.d: Updated.
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* testsuite/gas/i386/x86-64-se1.d: Likewise.
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2018-10-05 Sudakshina Das <sudi.das@arm.com>
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* config/tc-arm.c (arm_ext_predres): New.
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@ -10,4 +10,5 @@ Disassembly of section .text:
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0+ <_start>:
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[ ]*[a-f0-9]+: 0f 01 cf encls
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[ ]*[a-f0-9]+: 0f 01 d7 enclu
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[ ]*[a-f0-9]+: 0f 01 c0 enclv
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#pass
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@ -5,3 +5,4 @@ _start:
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encls
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enclu
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enclv
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@ -10,4 +10,5 @@ Disassembly of section .text:
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0+ <_start>:
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[ ]*[a-f0-9]+: 0f 01 cf encls
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[ ]*[a-f0-9]+: 0f 01 d7 enclu
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[ ]*[a-f0-9]+: 0f 01 c0 enclv
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#pass
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@ -5,3 +5,4 @@ _start:
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encls
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enclu
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enclv
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@ -1,3 +1,9 @@
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2018-10-05 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (rm_table): Add enclv.
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* i386-opc.tbl: Add enclv.
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* i386-tbl.h: Regenerated.
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2018-10-05 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (arm_opcodes): Add sb.
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@ -11027,7 +11027,7 @@ static const struct dis386 rm_table[][8] = {
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},
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{
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/* RM_0F01_REG_0 */
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{ Bad_Opcode },
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{ "enclv", { Skip_MODRM }, 0 },
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{ "vmcall", { Skip_MODRM }, 0 },
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{ "vmlaunch", { Skip_MODRM }, 0 },
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{ "vmresume", { Skip_MODRM }, 0 },
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@ -3992,6 +3992,7 @@ xsavec64, 1, 0xfc7, 0x4, 2, CpuXSAVEC|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sS
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encls, 0, 0xf01cf, None, 3, CpuSE1, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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enclu, 0, 0xf01d7, None, 3, CpuSE1, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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enclv, 0, 0xf01c0, None, 3, CpuSE1, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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// SGX instructions end.
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@ -66539,6 +66539,20 @@ const insn_template i386_optab[] =
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{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0 } } } },
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{ "enclv", 0, 0xf01c0, None, 3,
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0 } },
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
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1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0 },
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{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0 } } } },
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{ "vcvtpd2udqx", 2, 0x79, None, 1,
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0,
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