MIPS16/opcodes: Make the handling of BREAK and SDBBP consistent
Disassemble the MIPS16 BREAK and SDBBP instruction's immediate operand in the hexadecimal rather than decimal numeral system and add respective operandless variants with an implicit 0 operand, making our handling of these instructions consistent with how we have processed their regular MIPS and microMIPS counterparts since forever. opcodes/ * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand type to hexadecimal. (mips16_opcodes): Add operandless "break" and "sdbbp" entries. binutils/ * testsuite/binutils-all/mips/mips16-extend-insn.d: Adjust BREAK and SDBBP disassembly. gas/ * testsuite/gas/mips/mips16.d: Adjust BREAK disassembly. * testsuite/gas/mips/mips16-64@mips16.d: Likewise. * testsuite/gas/mips/mips16-64.d: Likewise. * testsuite/gas/mips/mips16-64@mips16-64.d: Likewise. * testsuite/gas/mips/mips16-macro.d: Likewise. * testsuite/gas/mips/mips16-64@mips16-macro.d: Likewise. * testsuite/gas/mips/mips16-sub.d: Likewise. * testsuite/gas/mips/mips16-32@mips16-sub.d: Likewise.
This commit is contained in:
Maciej W. Rozycki
parent
de428bc533
commit
a4f8991513
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@ -1,3 +1,8 @@
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2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
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* testsuite/binutils-all/mips/mips16-extend-insn.d: Adjust BREAK
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and SDBBP disassembly.
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2017-05-10 Maciej W. Rozycki <macro@imgtec.com>
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* testsuite/binutils-all/mips/mips.exp: Define `tempfile' and
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@ -215,7 +215,7 @@ Disassembly of section \.text:
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[0-9a-f]+ <[^>]*> f123 extend 0x123
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[0-9a-f]+ <[^>]*> e8c0 jalrc s0
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[0-9a-f]+ <[^>]*> f123 extend 0x123
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[0-9a-f]+ <[^>]*> e801 sdbbp 0
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[0-9a-f]+ <[^>]*> e801 sdbbp
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[0-9a-f]+ <[^>]*> f123 extend 0x123
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[0-9a-f]+ <[^>]*> e802 slt s0,s0
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[0-9a-f]+ <[^>]*> f123 extend 0x123
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@ -223,7 +223,7 @@ Disassembly of section \.text:
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[0-9a-f]+ <[^>]*> f123 extend 0x123
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[0-9a-f]+ <[^>]*> e804 sllv s0,s0
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[0-9a-f]+ <[^>]*> f123 extend 0x123
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[0-9a-f]+ <[^>]*> e805 break 0
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[0-9a-f]+ <[^>]*> e805 break
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[0-9a-f]+ <[^>]*> f123 extend 0x123
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[0-9a-f]+ <[^>]*> e806 srlv s0,s0
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[0-9a-f]+ <[^>]*> f123 extend 0x123
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@ -1,3 +1,14 @@
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2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
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* testsuite/gas/mips/mips16.d: Adjust BREAK disassembly.
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* testsuite/gas/mips/mips16-64@mips16.d: Likewise.
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* testsuite/gas/mips/mips16-64.d: Likewise.
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* testsuite/gas/mips/mips16-64@mips16-64.d: Likewise.
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* testsuite/gas/mips/mips16-macro.d: Likewise.
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* testsuite/gas/mips/mips16-64@mips16-macro.d: Likewise.
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* testsuite/gas/mips/mips16-sub.d: Likewise.
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* testsuite/gas/mips/mips16-32@mips16-sub.d: Likewise.
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2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
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* testsuite/gas/mips/mips32r2-sync-1.d: New test.
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@ -757,13 +757,13 @@ Disassembly of section \.text:
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[0-9a-f]+ <[^>]*> ea7d 0xea7d
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[0-9a-f]+ <[^>]*> ea7e 0xea7e
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[0-9a-f]+ <[^>]*> 2b01 bnez v1,000007d4 <insns2\+0xb4>
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[0-9a-f]+ <[^>]*> e8e5 break 7
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[0-9a-f]+ <[^>]*> e8e5 break 0x7
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[0-9a-f]+ <[^>]*> ea12 mflo v0
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[0-9a-f]+ <[^>]*> 6500 nop
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[0-9a-f]+ <[^>]*> 6500 nop
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[0-9a-f]+ <[^>]*> ea7f 0xea7f
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[0-9a-f]+ <[^>]*> 2b01 bnez v1,000007e0 <insns2\+0xc0>
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[0-9a-f]+ <[^>]*> e8e5 break 7
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[0-9a-f]+ <[^>]*> e8e5 break 0x7
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[0-9a-f]+ <[^>]*> ea12 mflo v0
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[0-9a-f]+ <[^>]*> 6500 nop
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[0-9a-f]+ <[^>]*> 6500 nop
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@ -771,13 +771,13 @@ Disassembly of section \.text:
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[0-9a-f]+ <[^>]*> ea79 multu v0,v1
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[0-9a-f]+ <[^>]*> ea7a div zero,v0,v1
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[0-9a-f]+ <[^>]*> 2b01 bnez v1,000007f0 <insns2\+0xd0>
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[0-9a-f]+ <[^>]*> e8e5 break 7
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[0-9a-f]+ <[^>]*> e8e5 break 0x7
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[0-9a-f]+ <[^>]*> ea12 mflo v0
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[0-9a-f]+ <[^>]*> 6500 nop
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[0-9a-f]+ <[^>]*> 6500 nop
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[0-9a-f]+ <[^>]*> ea7b divu zero,v0,v1
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[0-9a-f]+ <[^>]*> 2b01 bnez v1,000007fc <insns2\+0xdc>
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[0-9a-f]+ <[^>]*> e8e5 break 7
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[0-9a-f]+ <[^>]*> e8e5 break 0x7
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[0-9a-f]+ <[^>]*> ea12 mflo v0
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[0-9a-f]+ <[^>]*> ea00 jr v0
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[0-9a-f]+ <[^>]*> 6500 nop
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@ -805,9 +805,9 @@ Disassembly of section \.text:
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[0-9a-f]+ <[^>]*> 176f b 00000720 <insns2>
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[0-9a-f]+ <[^>]*> 1012 b 00000868 <bar>
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[0-9a-f]+ <[^>]*> 1075 b 00000930 <iuux>
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[0-9a-f]+ <[^>]*> e805 break 0
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[0-9a-f]+ <[^>]*> e825 break 1
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[0-9a-f]+ <[^>]*> efe5 break 63
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[0-9a-f]+ <[^>]*> e805 break
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[0-9a-f]+ <[^>]*> e825 break 0x1
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[0-9a-f]+ <[^>]*> efe5 break 0x3f
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[0-9a-f]+ <[^>]*> 1800 0000 jal 00000000 <data1>
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[ ]*[0-9a-f]+: R_MIPS16_26 extern
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[0-9a-f]+ <[^>]*> 6500 nop
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@ -614,21 +614,21 @@ Disassembly of section .text:
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7cc: ea7d dmultu v0,v1
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7ce: ea7e ddiv zero,v0,v1
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7d0: 2b01 bnez v1,7d4 <insns2\+(0x|)b4>
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7d2: e8e5 break 7
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7d2: e8e5 break 0x7
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7d4: ea12 mflo v0
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7d6: ea7f ddivu zero,v0,v1
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7d8: 2b01 bnez v1,7dc <insns2\+(0x|)bc>
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7da: e8e5 break 7
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7da: e8e5 break 0x7
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7dc: ea12 mflo v0
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7de: ea78 mult v0,v1
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7e0: ea79 multu v0,v1
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7e2: ea7a div zero,v0,v1
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7e4: 2b01 bnez v1,7e8 <insns2\+(0x|)c8>
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7e6: e8e5 break 7
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7e6: e8e5 break 0x7
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7e8: ea12 mflo v0
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7ea: ea7b divu zero,v0,v1
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7ec: 2b01 bnez v1,7f0 <insns2\+(0x|)d0>
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7ee: e8e5 break 7
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7ee: e8e5 break 0x7
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7f0: ea12 mflo v0
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7f2: ea80 jrc v0
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7f4: e8a0 jrc ra
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@ -653,9 +653,9 @@ Disassembly of section .text:
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828: 177b b 720 <insns2>
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82a: 1012 b 850 <bar>
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82c: 1075 b 918 <iuux>
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82e: e805 break 0
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830: e825 break 1
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832: efe5 break 63
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82e: e805 break
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830: e825 break 0x1
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832: efe5 break 0x3f
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834: 1800 0000 jal 0 <data1>
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834: R_MIPS16_26 extern
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834: R_MIPS_NONE \*ABS\*
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@ -614,13 +614,13 @@ Disassembly of section .text:
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7cc: ea7d dmultu v0,v1
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7ce: ea7e ddiv zero,v0,v1
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7d0: 2b01 bnez v1,7d4 <insns2\+(0x|)b4>
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7d2: e8e5 break 7
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7d2: e8e5 break 0x7
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7d4: ea12 mflo v0
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7d6: 6500 nop
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7d8: 6500 nop
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7da: ea7f ddivu zero,v0,v1
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7dc: 2b01 bnez v1,7e0 <insns2\+(0x|)c0>
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7de: e8e5 break 7
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7de: e8e5 break 0x7
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7e0: ea12 mflo v0
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7e2: 6500 nop
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7e4: 6500 nop
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@ -628,13 +628,13 @@ Disassembly of section .text:
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7e8: ea79 multu v0,v1
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7ea: ea7a div zero,v0,v1
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7ec: 2b01 bnez v1,7f0 <insns2\+(0x|)d0>
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7ee: e8e5 break 7
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7ee: e8e5 break 0x7
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7f0: ea12 mflo v0
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7f2: 6500 nop
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7f4: 6500 nop
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7f6: ea7b divu zero,v0,v1
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7f8: 2b01 bnez v1,7fc <insns2\+(0x|)dc>
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7fa: e8e5 break 7
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7fa: e8e5 break 0x7
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7fc: ea12 mflo v0
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7fe: ea00 jr v0
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800: 6500 nop
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@ -662,9 +662,9 @@ Disassembly of section .text:
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840: 176f b 720 <insns2>
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842: 1012 b 868 <bar>
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844: 1075 b 930 <iuux>
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846: e805 break 0
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848: e825 break 1
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84a: efe5 break 63
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846: e805 break
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848: e825 break 0x1
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84a: efe5 break 0x3f
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84c: 1800 0000 jal 0 <data1>
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84c: R_MIPS16_26 extern
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84c: R_MIPS_NONE \*ABS\*
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@ -11,49 +11,49 @@ Disassembly of section \.text:
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[ 0-9a-f]+ <foo>:
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[ 0-9a-f]+: eb9a div \$0,\$3,\$4
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[ 0-9a-f]+: 2c01 bnez \$4,[0-9a-f]+ <[^>]*>
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[ 0-9a-f]+: e8e5 break 7
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[ 0-9a-f]+: e8e5 break 0x7
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[ 0-9a-f]+: ea12 mflo \$2
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[ 0-9a-f]+: 6500 nop
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[ 0-9a-f]+: 6500 nop
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[ 0-9a-f]+: ecbb divu \$0,\$4,\$5
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[ 0-9a-f]+: 2d01 bnez \$5,[0-9a-f]+ <[^>]*>
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[ 0-9a-f]+: e8e5 break 7
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[ 0-9a-f]+: e8e5 break 0x7
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[ 0-9a-f]+: eb12 mflo \$3
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[ 0-9a-f]+: 6500 nop
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[ 0-9a-f]+: 6500 nop
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[ 0-9a-f]+: edde ddiv \$0,\$5,\$6
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[ 0-9a-f]+: 2e01 bnez \$6,[0-9a-f]+ <[^>]*>
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[ 0-9a-f]+: e8e5 break 7
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[ 0-9a-f]+: e8e5 break 0x7
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[ 0-9a-f]+: ec12 mflo \$4
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[ 0-9a-f]+: 6500 nop
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[ 0-9a-f]+: 6500 nop
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[ 0-9a-f]+: eeff ddivu \$0,\$6,\$7
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[ 0-9a-f]+: 2f01 bnez \$7,[0-9a-f]+ <[^>]*>
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[ 0-9a-f]+: e8e5 break 7
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[ 0-9a-f]+: e8e5 break 0x7
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[ 0-9a-f]+: ed12 mflo \$5
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[ 0-9a-f]+: 6500 nop
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[ 0-9a-f]+: 6500 nop
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[ 0-9a-f]+: ef1a div \$0,\$7,\$16
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[ 0-9a-f]+: 2801 bnez \$16,[0-9a-f]+ <[^>]*>
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[ 0-9a-f]+: e8e5 break 7
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[ 0-9a-f]+: e8e5 break 0x7
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[ 0-9a-f]+: ee10 mfhi \$6
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[ 0-9a-f]+: 6500 nop
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[ 0-9a-f]+: 6500 nop
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[ 0-9a-f]+: ef3b divu \$0,\$7,\$17
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[ 0-9a-f]+: 2901 bnez \$17,[0-9a-f]+ <[^>]*>
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[ 0-9a-f]+: e8e5 break 7
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[ 0-9a-f]+: e8e5 break 0x7
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[ 0-9a-f]+: ee10 mfhi \$6
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[ 0-9a-f]+: 6500 nop
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[ 0-9a-f]+: 6500 nop
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[ 0-9a-f]+: eb9e ddiv \$0,\$3,\$4
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[ 0-9a-f]+: 2c01 bnez \$4,[0-9a-f]+ <[^>]*>
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[ 0-9a-f]+: e8e5 break 7
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[ 0-9a-f]+: e8e5 break 0x7
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[ 0-9a-f]+: ea10 mfhi \$2
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[ 0-9a-f]+: 6500 nop
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[ 0-9a-f]+: 6500 nop
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[ 0-9a-f]+: ecbf ddivu \$0,\$4,\$5
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[ 0-9a-f]+: 2d01 bnez \$5,[0-9a-f]+ <[^>]*>
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[ 0-9a-f]+: e8e5 break 7
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[ 0-9a-f]+: e8e5 break 0x7
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[ 0-9a-f]+: eb10 mfhi \$3
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[ 0-9a-f]+: 6500 nop
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[ 0-9a-f]+: 6500 nop
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@ -614,13 +614,13 @@ Disassembly of section .text:
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7cc: ea7d dmultu v0,v1
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7ce: ea7e ddiv zero,v0,v1
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7d0: 2b01 bnez v1,7d4 <insns2\+(0x|)b4>
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7d2: e8e5 break 7
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7d2: e8e5 break 0x7
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7d4: ea12 mflo v0
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7d6: 6500 nop
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7d8: 6500 nop
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7da: ea7f ddivu zero,v0,v1
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7dc: 2b01 bnez v1,7e0 <insns2\+(0x|)c0>
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7de: e8e5 break 7
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7de: e8e5 break 0x7
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7e0: ea12 mflo v0
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7e2: 6500 nop
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7e4: 6500 nop
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@ -628,13 +628,13 @@ Disassembly of section .text:
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7e8: ea79 multu v0,v1
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7ea: ea7a div zero,v0,v1
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7ec: 2b01 bnez v1,7f0 <insns2\+(0x|)d0>
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7ee: e8e5 break 7
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7ee: e8e5 break 0x7
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7f0: ea12 mflo v0
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7f2: 6500 nop
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7f4: 6500 nop
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7f6: ea7b divu zero,v0,v1
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7f8: 2b01 bnez v1,7fc <insns2\+(0x|)dc>
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7fa: e8e5 break 7
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7fa: e8e5 break 0x7
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7fc: ea12 mflo v0
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7fe: ea00 jr v0
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800: 6500 nop
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@ -662,9 +662,9 @@ Disassembly of section .text:
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840: 176f b 720 <insns2>
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842: 1012 b 868 <bar>
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844: 1075 b 930 <iuux>
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846: e805 break 0
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848: e825 break 1
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84a: efe5 break 63
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846: e805 break
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848: e825 break 0x1
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84a: efe5 break 0x3f
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84c: 1800 0000 jal 0 <data1>
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84c: R_MIPS16_26 extern
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850: 6500 nop
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@ -10,35 +10,35 @@ Disassembly of section \.text:
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[ 0-9a-f]+ <foo>:
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[ 0-9a-f]+: eb9a div \$0,\$3,\$4
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[ 0-9a-f]+: 2c01 bnez \$4,[0-9a-f]+ <[^>]*>
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[ 0-9a-f]+: e8e5 break 7
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[ 0-9a-f]+: e8e5 break 0x7
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[ 0-9a-f]+: ea12 mflo \$2
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[ 0-9a-f]+: ecbb divu \$0,\$4,\$5
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[ 0-9a-f]+: 2d01 bnez \$5,[0-9a-f]+ <[^>]*>
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[ 0-9a-f]+: e8e5 break 7
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[ 0-9a-f]+: e8e5 break 0x7
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[ 0-9a-f]+: eb12 mflo \$3
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[ 0-9a-f]+: edde ddiv \$0,\$5,\$6
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[ 0-9a-f]+: 2e01 bnez \$6,[0-9a-f]+ <[^>]*>
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[ 0-9a-f]+: e8e5 break 7
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[ 0-9a-f]+: e8e5 break 0x7
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[ 0-9a-f]+: ec12 mflo \$4
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[ 0-9a-f]+: eeff ddivu \$0,\$6,\$7
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[ 0-9a-f]+: 2f01 bnez \$7,[0-9a-f]+ <[^>]*>
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[ 0-9a-f]+: e8e5 break 7
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[ 0-9a-f]+: e8e5 break 0x7
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[ 0-9a-f]+: ed12 mflo \$5
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[ 0-9a-f]+: ef1a div \$0,\$7,\$16
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[ 0-9a-f]+: 2801 bnez \$16,[0-9a-f]+ <[^>]*>
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[ 0-9a-f]+: e8e5 break 7
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[ 0-9a-f]+: e8e5 break 0x7
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[ 0-9a-f]+: ee10 mfhi \$6
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[ 0-9a-f]+: ef3b divu \$0,\$7,\$17
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[ 0-9a-f]+: 2901 bnez \$17,[0-9a-f]+ <[^>]*>
|
||||
[ 0-9a-f]+: e8e5 break 7
|
||||
[ 0-9a-f]+: e8e5 break 0x7
|
||||
[ 0-9a-f]+: ee10 mfhi \$6
|
||||
[ 0-9a-f]+: eb9e ddiv \$0,\$3,\$4
|
||||
[ 0-9a-f]+: 2c01 bnez \$4,[0-9a-f]+ <[^>]*>
|
||||
[ 0-9a-f]+: e8e5 break 7
|
||||
[ 0-9a-f]+: e8e5 break 0x7
|
||||
[ 0-9a-f]+: ea10 mfhi \$2
|
||||
[ 0-9a-f]+: ecbf ddivu \$0,\$4,\$5
|
||||
[ 0-9a-f]+: 2d01 bnez \$5,[0-9a-f]+ <[^>]*>
|
||||
[ 0-9a-f]+: e8e5 break 7
|
||||
[ 0-9a-f]+: e8e5 break 0x7
|
||||
[ 0-9a-f]+: eb10 mfhi \$3
|
||||
[ 0-9a-f]+: edd9 multu \$5,\$6
|
||||
[ 0-9a-f]+: ec12 mflo \$4
|
||||
|
|
|
|||
|
|
@ -603,13 +603,13 @@ Disassembly of section \.text:
|
|||
[0-9a-f]+ <[^>]*> ea7d dmultu v0,v1
|
||||
[0-9a-f]+ <[^>]*> ea7e ddiv zero,v0,v1
|
||||
[0-9a-f]+ <[^>]*> 2b01 bnez v1,000007d4 <insns2\+0xb4>
|
||||
[0-9a-f]+ <[^>]*> e8e5 break 7
|
||||
[0-9a-f]+ <[^>]*> e8e5 break 0x7
|
||||
[0-9a-f]+ <[^>]*> ea12 mflo v0
|
||||
[0-9a-f]+ <[^>]*> 6500 nop
|
||||
[0-9a-f]+ <[^>]*> 6500 nop
|
||||
[0-9a-f]+ <[^>]*> ea7f ddivu zero,v0,v1
|
||||
[0-9a-f]+ <[^>]*> 2b01 bnez v1,000007e0 <insns2\+0xc0>
|
||||
[0-9a-f]+ <[^>]*> e8e5 break 7
|
||||
[0-9a-f]+ <[^>]*> e8e5 break 0x7
|
||||
[0-9a-f]+ <[^>]*> ea12 mflo v0
|
||||
[0-9a-f]+ <[^>]*> 6500 nop
|
||||
[0-9a-f]+ <[^>]*> 6500 nop
|
||||
|
|
@ -617,13 +617,13 @@ Disassembly of section \.text:
|
|||
[0-9a-f]+ <[^>]*> ea79 multu v0,v1
|
||||
[0-9a-f]+ <[^>]*> ea7a div zero,v0,v1
|
||||
[0-9a-f]+ <[^>]*> 2b01 bnez v1,000007f0 <insns2\+0xd0>
|
||||
[0-9a-f]+ <[^>]*> e8e5 break 7
|
||||
[0-9a-f]+ <[^>]*> e8e5 break 0x7
|
||||
[0-9a-f]+ <[^>]*> ea12 mflo v0
|
||||
[0-9a-f]+ <[^>]*> 6500 nop
|
||||
[0-9a-f]+ <[^>]*> 6500 nop
|
||||
[0-9a-f]+ <[^>]*> ea7b divu zero,v0,v1
|
||||
[0-9a-f]+ <[^>]*> 2b01 bnez v1,000007fc <insns2\+0xdc>
|
||||
[0-9a-f]+ <[^>]*> e8e5 break 7
|
||||
[0-9a-f]+ <[^>]*> e8e5 break 0x7
|
||||
[0-9a-f]+ <[^>]*> ea12 mflo v0
|
||||
[0-9a-f]+ <[^>]*> ea00 jr v0
|
||||
[0-9a-f]+ <[^>]*> 6500 nop
|
||||
|
|
@ -651,9 +651,9 @@ Disassembly of section \.text:
|
|||
[0-9a-f]+ <[^>]*> 176f b 00000720 <insns2>
|
||||
[0-9a-f]+ <[^>]*> 1012 b 00000868 <bar>
|
||||
[0-9a-f]+ <[^>]*> 1075 b 00000930 <iuux>
|
||||
[0-9a-f]+ <[^>]*> e805 break 0
|
||||
[0-9a-f]+ <[^>]*> e825 break 1
|
||||
[0-9a-f]+ <[^>]*> efe5 break 63
|
||||
[0-9a-f]+ <[^>]*> e805 break
|
||||
[0-9a-f]+ <[^>]*> e825 break 0x1
|
||||
[0-9a-f]+ <[^>]*> efe5 break 0x3f
|
||||
[0-9a-f]+ <[^>]*> 1800 0000 jal 00000000 <data1>
|
||||
[ ]*[0-9a-f]+: R_MIPS16_26 extern
|
||||
[0-9a-f]+ <[^>]*> 6500 nop
|
||||
|
|
|
|||
|
|
@ -613,21 +613,21 @@ Disassembly of section .text:
|
|||
7cc: ea7d dmultu v0,v1
|
||||
7ce: ea7e ddiv zero,v0,v1
|
||||
7d0: 2b01 bnez v1,7d4 <insns2\+(0x|)b4>
|
||||
7d2: e8e5 break 7
|
||||
7d2: e8e5 break 0x7
|
||||
7d4: ea12 mflo v0
|
||||
7d6: ea7f ddivu zero,v0,v1
|
||||
7d8: 2b01 bnez v1,7dc <insns2\+(0x|)bc>
|
||||
7da: e8e5 break 7
|
||||
7da: e8e5 break 0x7
|
||||
7dc: ea12 mflo v0
|
||||
7de: ea78 mult v0,v1
|
||||
7e0: ea79 multu v0,v1
|
||||
7e2: ea7a div zero,v0,v1
|
||||
7e4: 2b01 bnez v1,7e8 <insns2\+(0x|)c8>
|
||||
7e6: e8e5 break 7
|
||||
7e6: e8e5 break 0x7
|
||||
7e8: ea12 mflo v0
|
||||
7ea: ea7b divu zero,v0,v1
|
||||
7ec: 2b01 bnez v1,7f0 <insns2\+(0x|)d0>
|
||||
7ee: e8e5 break 7
|
||||
7ee: e8e5 break 0x7
|
||||
7f0: ea12 mflo v0
|
||||
7f2: ea80 jrc v0
|
||||
7f4: e8a0 jrc ra
|
||||
|
|
@ -652,9 +652,9 @@ Disassembly of section .text:
|
|||
828: 177b b 720 <insns2>
|
||||
82a: 1012 b 850 <bar>
|
||||
82c: 1075 b 918 <iuux>
|
||||
82e: e805 break 0
|
||||
830: e825 break 1
|
||||
832: efe5 break 63
|
||||
82e: e805 break
|
||||
830: e825 break 0x1
|
||||
832: efe5 break 0x3f
|
||||
834: 1800 0000 jal 0 <data1>
|
||||
834: R_MIPS16_26 extern
|
||||
838: 6500 nop
|
||||
|
|
|
|||
|
|
@ -1,3 +1,9 @@
|
|||
2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
|
||||
|
||||
* mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
|
||||
type to hexadecimal.
|
||||
(mips16_opcodes): Add operandless "break" and "sdbbp" entries.
|
||||
|
||||
2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
|
||||
|
||||
* mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
|
||||
|
|
|
|||
|
|
@ -56,7 +56,7 @@ decode_mips16_operand (char type, bfd_boolean extended_p)
|
|||
case '2': HINT (3, 8);
|
||||
case '3': HINT (5, 16);
|
||||
case '4': HINT (3, 21);
|
||||
case '6': UINT (6, 5);
|
||||
case '6': HINT (6, 5);
|
||||
|
||||
case 'L': SPECIAL (6, 5, ENTRY_EXIT_LIST);
|
||||
case 'M': SPECIAL (7, 0, SAVE_RESTORE_LIST);
|
||||
|
|
@ -230,6 +230,7 @@ const struct mips_opcode mips16_opcodes[] =
|
|||
{"bne", "x,y,p", 0, (int) M_BNE, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{"bne", "x,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{"bnez", "x,p", 0x2800, 0xf800, RD_1, CBR, I1, 0, 0 },
|
||||
{"break", "", 0xe805, 0xffff, TRAP, SH, I1, 0, 0 },
|
||||
{"break", "6", 0xe805, 0xf81f, TRAP, SH, I1, 0, 0 },
|
||||
{"bteqz", "p", 0x6000, 0xff00, RD_T, CBR, I1, 0, 0 },
|
||||
{"btnez", "p", 0x6100, 0xff00, RD_T, CBR, I1, 0, 0 },
|
||||
|
|
@ -358,6 +359,7 @@ const struct mips_opcode mips16_opcodes[] =
|
|||
/* MIPS16e additions; see above for compact jumps. */
|
||||
{"restore", "M", 0x6400, 0xff80, WR_31|NODS, MOD_SP, I32, 0, 0 },
|
||||
{"save", "m", 0x6480, 0xff80, NODS, RD_31|MOD_SP, I32, 0, 0 },
|
||||
{"sdbbp", "", 0xe801, 0xffff, TRAP, SH, I32, 0, 0 },
|
||||
{"sdbbp", "6", 0xe801, 0xf81f, TRAP, SH, I32, 0, 0 },
|
||||
{"seb", "x", 0xe891, 0xf8ff, MOD_1, SH, I32, 0, 0 },
|
||||
{"seh", "x", 0xe8b1, 0xf8ff, MOD_1, SH, I32, 0, 0 },
|
||||
|
|
|
|||
Loading…
Reference in New Issue