OpenE2K/binutils-gdb
12
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

opcodes/

Browse Source 
* aarch64-opc.c (print_register_offset_address): Call
	get_int_reg_name to prepare the register name.

gas/testsuite/

	* gas/aarch64/ldst-reg-reg-offset.s: Add tests.
	* gas/aarch64/ldst-reg-reg-offset.d: Update.
This commit is contained in:
Yufeng Zhang 2014-02-27 14:55:46 +00:00
parent 2fa0369e51
commit a58549dda5
5 changed files with 25 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
gas/testsuite/ChangeLog
View File

@ -1,3 +1,8 @@
2014-02-27 Yufeng Zhang <yufeng.zhang@arm.com>
* gas/aarch64/ldst-reg-reg-offset.s: Add tests.
* gas/aarch64/ldst-reg-reg-offset.d: Update.
2014-02-21 Ilya Tocar <ilya.tocar@intel.com>
* gas/i386/avx512pf-intel.d: Remove prefetchwt1.

4
gas/testsuite/gas/aarch64/ldst-reg-reg-offset.d
View File

@ -85,3 +85,7 @@ Disassembly of section \.text:
134: fc67fbe7 ldr d7, \[sp,x7,sxtx #3\]
138: 3ce7ebe7 ldr q7, \[sp,x7,sxtx\]
13c: 3ce7fbe7 ldr q7, \[sp,x7,sxtx #4\]
140: f87ffbe1 ldr x1, \[sp,xzr,sxtx #3\]
144: f83ffbe1 str x1, \[sp,xzr,sxtx #3\]
148: b87fdbe1 ldr w1, \[sp,wzr,sxtw #2\]
14c: b83fdbe1 str w1, \[sp,wzr,sxtw #2\]

6
gas/testsuite/gas/aarch64/ldst-reg-reg-offset.s
View File

@ -86,3 +86,9 @@
func:
ld_or_st str
ld_or_st ldr
/* When the index register is of register 31, it should be ZR. */
ldr x1, [sp, xzr, sxtx #3]
str x1, [sp, xzr, sxtx #3]
ldr w1, [sp, wzr, sxtw #2]
str w1, [sp, wzr, sxtw #2]

5
opcodes/ChangeLog
View File

@ -1,3 +1,8 @@
2014-02-27 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64-opc.c (print_register_offset_address): Call
get_int_reg_name to prepare the register name.
2014-02-25 Ilya Tocar <ilya.tocar@intel.com>
* i386-opc.tbl: Remove wrong variant of vcvtps2ph

7
opcodes/aarch64-opc.c
View File

@ -2282,9 +2282,12 @@ print_register_offset_address (char *buf, size_t size,
else
tb[0] = '\0';
snprintf (buf, size, "[%s,%c%d%s]",
snprintf (buf, size, "[%s,%s%s]",
get_64bit_int_reg_name (opnd->addr.base_regno, 1),
wm_p ? 'w' : 'x', opnd->addr.offset.regno, tb);
get_int_reg_name (opnd->addr.offset.regno,
wm_p ? AARCH64_OPND_QLF_W : AARCH64_OPND_QLF_X,
0 /* sp_reg_p */),
tb);
}
/* Generate the string representation of the operand OPNDS[IDX] for OPCODE