AArch64: Add SVE constraints verifier.
This patch adds the verification rules for move prefix constraints. The Arm SVE instruction MOVPRFX introduces[1] constraints on the instruction at PC+4. Particularly the following constraints are handled by this patch * MOVPRFX must be followed by an instruction. * MOVPRFX can only be followed by non-layout altering directives. * MOVPRFX destination register MUST be used as the destination register in the instruction at PC+4, and is not allowed to be used in any other position other than destructive input. This includes registers that architecturally overlap. e.g. x1 should be treated as z1. * MOVPRFX must be followed by a restricted set of SVE instructions. * The size of the destination register of MOVPRFX must be equal to that of the operation at PC+4. * The predicate register and operation of MOVPRFX must match that of the instruction at PC+4 * The predicated instruction at PC+4 must use the merging predicate. * Architectural aliases and pseudo-instructions need to be supported as well. * MOVPRFX cannot be the last instruction in a sequence Any failure to adhere to any of these constrains will emit an assembly warning and a disassembly note. [1] https://developer.arm.com/docs/ddi0584/latest/arm-architecture-reference-manual-supplement-the-scalable-vector-extension-sve-for-armv8-a include/ * opcode/aarch64.h (aarch64_inst): Remove. (enum err_type): Add ERR_VFI. (aarch64_is_destructive_by_operands): New. (init_insn_sequence): New. (aarch64_decode_insn): Remove param name. opcodes/ * aarch64-opc.c (init_insn_block): New. (verify_constraints, aarch64_is_destructive_by_operands): New. * aarch64-opc.h (verify_constraints): New. gas/ * config/tc-aarch64.c (output_operand_error_report): Order warnings.
This commit is contained in:
Tamar Christina
parent
755b748fd9
commit
a68f4cd235
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@ -1,3 +1,7 @@
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2018-10-03 Tamar Christina <tamar.christina@arm.com>
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* config/tc-aarch64.c (output_operand_error_report): Order warnings.
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2018-10-03 Tamar Christina <tamar.christina@arm.com>
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* config/tc-aarch64.c (now_instr_sequence):
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@ -4807,10 +4807,12 @@ output_operand_error_report (char *str, bfd_boolean non_fatal_only)
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{
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gas_assert (curr->detail.kind != AARCH64_OPDE_NIL);
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DEBUG_TRACE ("\t%s", operand_mismatch_kind_names[curr->detail.kind]);
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if (operand_error_higher_severity_p (curr->detail.kind, kind))
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if (operand_error_higher_severity_p (curr->detail.kind, kind)
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&& (!non_fatal_only || (non_fatal_only && curr->detail.non_fatal)))
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kind = curr->detail.kind;
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}
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gas_assert (kind != AARCH64_OPDE_NIL);
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gas_assert (kind != AARCH64_OPDE_NIL || non_fatal_only);
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/* Pick up one of errors of KIND to report. */
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largest_error_pos = -2; /* Index can be -1 which means unknown index. */
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@ -1,3 +1,11 @@
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2018-10-03 Tamar Christina <tamar.christina@arm.com>
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* opcode/aarch64.h (aarch64_inst): Remove.
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(enum err_type): Add ERR_VFI.
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(aarch64_is_destructive_by_operands): New.
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(init_insn_sequence): New.
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(aarch64_decode_insn): Remove param name.
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2018-10-03 Tamar Christina <tamar.christina@arm.com>
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* opcode/aarch64.h (struct aarch64_opcode): Expand verifiers to take
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@ -648,6 +648,7 @@ enum err_type
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ERR_UND,
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ERR_UNP,
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ERR_NYI,
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ERR_VFI,
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ERR_NR_ENTRIES
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};
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@ -1065,7 +1066,6 @@ struct aarch64_inst
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aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
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};
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typedef struct aarch64_inst aarch64_inst;
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/* Diagnosis related declaration and interface. */
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@ -1190,6 +1190,9 @@ extern aarch64_opnd_qualifier_t
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aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
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const aarch64_opnd_qualifier_t, int);
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extern bfd_boolean
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aarch64_is_destructive_by_operands (const aarch64_opcode *);
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extern int
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aarch64_num_of_operands (const aarch64_opcode *);
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@ -1201,7 +1204,10 @@ aarch64_zero_register_p (const aarch64_opnd_info *);
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extern enum err_type
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aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
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aarch64_operand_error *errors);
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aarch64_operand_error *);
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extern void
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init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *);
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/* Given an operand qualifier, return the expected data element size
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of a qualified operand. */
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@ -1,3 +1,9 @@
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2018-10-03 Tamar Christina <tamar.christina@arm.com>
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* aarch64-opc.c (init_insn_block): New.
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(verify_constraints, aarch64_is_destructive_by_operands): New.
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* aarch64-opc.h (verify_constraints): New.
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2018-10-03 Tamar Christina <tamar.christina@arm.com>
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* aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
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@ -832,6 +832,25 @@ dump_match_qualifiers (const struct aarch64_opnd_info *opnd,
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}
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#endif /* DEBUG_AARCH64 */
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/* This function checks if the given instruction INSN is a destructive
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instruction based on the usage of the registers. It does not recognize
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unary destructive instructions. */
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bfd_boolean
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aarch64_is_destructive_by_operands (const aarch64_opcode *opcode)
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{
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int i = 0;
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const enum aarch64_opnd *opnds = opcode->operands;
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if (opnds[0] == AARCH64_OPND_NIL)
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return FALSE;
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while (opnds[++i] != AARCH64_OPND_NIL)
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if (opnds[i] == opnds[0])
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return TRUE;
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return FALSE;
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}
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/* TODO improve this, we can have an extra field at the runtime to
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store the number of operands rather than calculating it every time. */
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@ -4491,7 +4510,7 @@ verify_ldpsw (const struct aarch64_inst *inst ATTRIBUTE_UNUSED,
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const aarch64_insn insn, bfd_vma pc ATTRIBUTE_UNUSED,
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bfd_boolean encoding ATTRIBUTE_UNUSED,
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aarch64_operand_error *mismatch_detail ATTRIBUTE_UNUSED,
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aarch64_instr_sequence *insn_block ATTRIBUTE_UNUSED)
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aarch64_instr_sequence *insn_sequence ATTRIBUTE_UNUSED)
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{
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int t = BITS (insn, 4, 0);
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int n = BITS (insn, 9, 5);
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@ -4514,6 +4533,334 @@ verify_ldpsw (const struct aarch64_inst *inst ATTRIBUTE_UNUSED,
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return ERR_OK;
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}
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/* Initialize an instruction sequence insn_sequence with the instruction INST.
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If INST is NULL the given insn_sequence is cleared and the sequence is left
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uninitialized. */
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void
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init_insn_sequence (const struct aarch64_inst *inst,
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aarch64_instr_sequence *insn_sequence)
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{
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int num_req_entries = 0;
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insn_sequence->next_insn = 0;
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insn_sequence->num_insns = num_req_entries;
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if (insn_sequence->instr)
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XDELETE (insn_sequence->instr);
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insn_sequence->instr = NULL;
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if (inst)
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{
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insn_sequence->instr = XNEW (aarch64_inst);
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memcpy (insn_sequence->instr, inst, sizeof (aarch64_inst));
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}
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/* Handle all the cases here. May need to think of something smarter than
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a giant if/else chain if this grows. At that time, a lookup table may be
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best. */
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if (inst && inst->opcode->constraints & C_SCAN_MOVPRFX)
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num_req_entries = 1;
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if (insn_sequence->current_insns)
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XDELETEVEC (insn_sequence->current_insns);
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insn_sequence->current_insns = NULL;
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if (num_req_entries != 0)
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{
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size_t size = num_req_entries * sizeof (aarch64_inst);
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insn_sequence->current_insns
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= (aarch64_inst**) XNEWVEC (aarch64_inst, num_req_entries);
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memset (insn_sequence->current_insns, 0, size);
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}
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}
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/* This function verifies that the instruction INST adheres to its specified
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constraints. If it does then ERR_OK is returned, if not then ERR_VFI is
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returned and MISMATCH_DETAIL contains the reason why verification failed.
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The function is called both during assembly and disassembly. If assembling
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then ENCODING will be TRUE, else FALSE. If dissassembling PC will be set
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and will contain the PC of the current instruction w.r.t to the section.
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If ENCODING and PC=0 then you are at a start of a section. The constraints
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are verified against the given state insn_sequence which is updated as it
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transitions through the verification. */
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enum err_type
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verify_constraints (const struct aarch64_inst *inst,
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const aarch64_insn insn ATTRIBUTE_UNUSED,
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bfd_vma pc,
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bfd_boolean encoding,
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aarch64_operand_error *mismatch_detail,
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aarch64_instr_sequence *insn_sequence)
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{
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assert (inst);
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assert (inst->opcode);
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const struct aarch64_opcode *opcode = inst->opcode;
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if (!opcode->constraints && !insn_sequence->instr)
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return ERR_OK;
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assert (insn_sequence);
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enum err_type res = ERR_OK;
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/* This instruction puts a constraint on the insn_sequence. */
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if (opcode->flags & F_SCAN)
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{
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if (insn_sequence->instr)
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{
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mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
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mismatch_detail->error = _("instruction opens new dependency "
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"sequence without ending previous one");
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mismatch_detail->index = -1;
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mismatch_detail->non_fatal = TRUE;
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res = ERR_VFI;
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}
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init_insn_sequence (inst, insn_sequence);
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return res;
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}
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/* Verify constraints on an existing sequence. */
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if (insn_sequence->instr)
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{
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const struct aarch64_opcode* inst_opcode = insn_sequence->instr->opcode;
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/* If we're decoding and we hit PC=0 with an open sequence then we haven't
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closed a previous one that we should have. */
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if (!encoding && pc == 0)
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{
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mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
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mismatch_detail->error = _("previous `movprfx' sequence not closed");
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mismatch_detail->index = -1;
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mismatch_detail->non_fatal = TRUE;
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res = ERR_VFI;
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/* Reset the sequence. */
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init_insn_sequence (NULL, insn_sequence);
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return res;
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}
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/* Validate C_SCAN_MOVPRFX constraints. Move this to a lookup table. */
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if (inst_opcode->constraints & C_SCAN_MOVPRFX)
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{
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/* Check to see if the MOVPRFX SVE instruction is followed by an SVE
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instruction for better error messages. */
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if (!opcode->avariant || !(*opcode->avariant & AARCH64_FEATURE_SVE))
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{
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mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
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mismatch_detail->error = _("SVE instruction expected after "
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"`movprfx'");
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mismatch_detail->index = -1;
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mismatch_detail->non_fatal = TRUE;
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res = ERR_VFI;
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goto done;
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}
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/* Check to see if the MOVPRFX SVE instruction is followed by an SVE
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instruction that is allowed to be used with a MOVPRFX. */
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if (!(opcode->constraints & C_SCAN_MOVPRFX))
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{
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mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
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mismatch_detail->error = _("SVE `movprfx' compatible instruction "
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"expected");
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mismatch_detail->index = -1;
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mismatch_detail->non_fatal = TRUE;
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res = ERR_VFI;
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goto done;
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}
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/* Next check for usage of the predicate register. */
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aarch64_opnd_info blk_dest = insn_sequence->instr->operands[0];
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aarch64_opnd_info blk_pred = {0}, inst_pred = {0};
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bfd_boolean predicated = FALSE;
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assert (blk_dest.type == AARCH64_OPND_SVE_Zd);
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/* Determine if the movprfx instruction used is predicated or not. */
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if (insn_sequence->instr->operands[1].type == AARCH64_OPND_SVE_Pg3)
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{
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predicated = TRUE;
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blk_pred = insn_sequence->instr->operands[1];
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}
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unsigned char max_elem_size = 0;
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unsigned char current_elem_size;
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int num_op_used = 0, last_op_usage = 0;
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int i, inst_pred_idx = -1;
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int num_ops = aarch64_num_of_operands (opcode);
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for (i = 0; i < num_ops; i++)
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{
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aarch64_opnd_info inst_op = inst->operands[i];
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switch (inst_op.type)
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{
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case AARCH64_OPND_SVE_Zd:
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case AARCH64_OPND_SVE_Zm_5:
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case AARCH64_OPND_SVE_Zm_16:
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case AARCH64_OPND_SVE_Zn:
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case AARCH64_OPND_SVE_Zt:
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case AARCH64_OPND_SVE_Vm:
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case AARCH64_OPND_SVE_Vn:
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case AARCH64_OPND_Va:
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case AARCH64_OPND_Vn:
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case AARCH64_OPND_Vm:
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case AARCH64_OPND_Sn:
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case AARCH64_OPND_Sm:
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case AARCH64_OPND_Rn:
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case AARCH64_OPND_Rm:
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case AARCH64_OPND_Rn_SP:
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case AARCH64_OPND_Rm_SP:
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if (inst_op.reg.regno == blk_dest.reg.regno)
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{
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num_op_used++;
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last_op_usage = i;
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}
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current_elem_size
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= aarch64_get_qualifier_esize (inst_op.qualifier);
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if (current_elem_size > max_elem_size)
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max_elem_size = current_elem_size;
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break;
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case AARCH64_OPND_SVE_Pd:
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case AARCH64_OPND_SVE_Pg3:
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case AARCH64_OPND_SVE_Pg4_5:
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case AARCH64_OPND_SVE_Pg4_10:
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case AARCH64_OPND_SVE_Pg4_16:
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case AARCH64_OPND_SVE_Pm:
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case AARCH64_OPND_SVE_Pn:
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case AARCH64_OPND_SVE_Pt:
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inst_pred = inst_op;
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inst_pred_idx = i;
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break;
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default:
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break;
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}
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}
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assert (max_elem_size != 0);
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aarch64_opnd_info inst_dest = inst->operands[0];
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/* Determine the size that should be used to compare against the
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movprfx size. */
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current_elem_size
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= opcode->constraints & C_MAX_ELEM
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? max_elem_size
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: aarch64_get_qualifier_esize (inst_dest.qualifier);
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/* If movprfx is predicated do some extra checks. */
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if (predicated)
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{
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/* The instruction must be predicated. */
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if (inst_pred_idx < 0)
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{
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mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
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mismatch_detail->error = _("predicated instruction expected "
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"after `movprfx'");
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mismatch_detail->index = -1;
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mismatch_detail->non_fatal = TRUE;
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res = ERR_VFI;
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goto done;
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}
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/* The instruction must have a merging predicate. */
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if (inst_pred.qualifier != AARCH64_OPND_QLF_P_M)
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{
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mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
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mismatch_detail->error = _("merging predicate expected due "
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"to preceding `movprfx'");
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mismatch_detail->index = inst_pred_idx;
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mismatch_detail->non_fatal = TRUE;
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res = ERR_VFI;
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goto done;
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}
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/* The same register must be used in instruction. */
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if (blk_pred.reg.regno != inst_pred.reg.regno)
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{
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mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
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mismatch_detail->error = _("predicate register differs "
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"from that in preceding "
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"`movprfx'");
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mismatch_detail->index = inst_pred_idx;
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mismatch_detail->non_fatal = TRUE;
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res = ERR_VFI;
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goto done;
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}
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}
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/* Destructive operations by definition must allow one usage of the
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same register. */
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int allowed_usage
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= aarch64_is_destructive_by_operands (opcode) ? 2 : 1;
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/* Operand is not used at all. */
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if (num_op_used == 0)
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{
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mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
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mismatch_detail->error = _("output register of preceding "
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"`movprfx' not used in current "
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"instruction");
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mismatch_detail->index = 0;
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mismatch_detail->non_fatal = TRUE;
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res = ERR_VFI;
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goto done;
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}
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/* We now know it's used, now determine exactly where it's used. */
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if (blk_dest.reg.regno != inst_dest.reg.regno)
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{
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mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
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mismatch_detail->error = _("output register of preceding "
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"`movprfx' expected as output");
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mismatch_detail->index = 0;
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mismatch_detail->non_fatal = TRUE;
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res = ERR_VFI;
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goto done;
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}
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|
||||
/* Operand used more than allowed for the specific opcode type. */
|
||||
if (num_op_used > allowed_usage)
|
||||
{
|
||||
mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
|
||||
mismatch_detail->error = _("output register of preceding "
|
||||
"`movprfx' used as input");
|
||||
mismatch_detail->index = last_op_usage;
|
||||
mismatch_detail->non_fatal = TRUE;
|
||||
res = ERR_VFI;
|
||||
goto done;
|
||||
}
|
||||
|
||||
/* Now the only thing left is the qualifiers checks. The register
|
||||
must have the same maximum element size. */
|
||||
if (inst_dest.qualifier
|
||||
&& blk_dest.qualifier
|
||||
&& current_elem_size
|
||||
!= aarch64_get_qualifier_esize (blk_dest.qualifier))
|
||||
{
|
||||
mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
|
||||
mismatch_detail->error = _("register size not compatible with "
|
||||
"previous `movprfx'");
|
||||
mismatch_detail->index = 0;
|
||||
mismatch_detail->non_fatal = TRUE;
|
||||
res = ERR_VFI;
|
||||
goto done;
|
||||
}
|
||||
}
|
||||
|
||||
done:
|
||||
/* Add the new instruction to the sequence. */
|
||||
memcpy (insn_sequence->current_insns + insn_sequence->next_insn++,
|
||||
inst, sizeof (aarch64_inst));
|
||||
|
||||
/* Check if sequence is now full. */
|
||||
if (insn_sequence->next_insn >= insn_sequence->num_insns)
|
||||
{
|
||||
/* Sequence is full, but we don't have anything special to do for now,
|
||||
so clear and reset it. */
|
||||
init_insn_sequence (NULL, insn_sequence);
|
||||
}
|
||||
}
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
|
||||
/* Return true if VALUE cannot be moved into an SVE register using DUP
|
||||
(with any element size, not just ESIZE) and if using DUPM would
|
||||
therefore be OK. ESIZE is the number of bytes in the immediate. */
|
||||
|
|
|
|||
|
|
@ -183,6 +183,10 @@ typedef struct aarch64_operand aarch64_operand;
|
|||
|
||||
extern const aarch64_operand aarch64_operands[];
|
||||
|
||||
enum err_type
|
||||
verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
|
||||
bfd_boolean, aarch64_operand_error *, aarch64_instr_sequence*);
|
||||
|
||||
/* Operand flags. */
|
||||
|
||||
#define OPD_F_HAS_INSERTER 0x00000001
|
||||
|
|
|
|||
Loading…
Reference in New Issue