More 1 << 31 signed overflows
* config/tc-csky.c (get_operand_value): Rewrite 1 << 31 expressions to avoid signed overflow. * config/tc-mcore.c (md_assemble): Likewise. * config/tc-mips.c (gpr_read_mask, gpr_write_mask): Likewise. * config/tc-nds32.c (SET_ADDEND): Likewise. * config/tc-nios2.c (nios2_assemble_arg_R): Likewise.
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@ -1,3 +1,12 @@
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2020-03-10 Alan Modra <amodra@gmail.com>
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* config/tc-csky.c (get_operand_value): Rewrite 1 << 31 expressions
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to avoid signed overflow.
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* config/tc-mcore.c (md_assemble): Likewise.
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* config/tc-mips.c (gpr_read_mask, gpr_write_mask): Likewise.
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* config/tc-nds32.c (SET_ADDEND): Likewise.
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* config/tc-nios2.c (nios2_assemble_arg_R): Likewise.
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2020-03-09 Jan Beulich <jbeulich@suse.com>
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* testsuite/gas/i386/avx.s: Add long-form VCMP[PS][SD] pseudos.
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@ -3166,7 +3166,7 @@ get_operand_value (struct csky_opcode_info *op,
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case OPRND_TYPE_IMM5b_1_31:
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return is_imm_over_range (oper, 1, 31, -1);
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case OPRND_TYPE_IMM5b_POWER:
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if (is_imm_over_range (oper, 1, ~(1 << 31), 1 << 31))
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if (is_imm_over_range (oper, 1, (1u << 31) - 1, 1u << 31))
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{
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int log;
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int val = csky_insn.val[csky_insn.idx - 1];
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@ -3179,7 +3179,7 @@ get_operand_value (struct csky_opcode_info *op,
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/* This type for "mgeni" in csky v1 ISA. */
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case OPRND_TYPE_IMM5b_7_31_POWER:
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if (is_imm_over_range (oper, 1, ~(1 << 31), 1 << 31))
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if (is_imm_over_range (oper, 1, (1u << 31) - 1, 1u << 31))
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{
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int log;
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int val = csky_insn.val[csky_insn.idx - 1];
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@ -1088,7 +1088,7 @@ md_assemble (char * str)
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if (* op_end == ',')
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{
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op_end = parse_imm (op_end + 1, & reg, 1, 1 << 31);
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op_end = parse_imm (op_end + 1, & reg, 1, 1u << 31);
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/* Further restrict the immediate to a power of two. */
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if ((reg & (reg - 1)) == 0)
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reg = mylog2 (reg);
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@ -1144,7 +1144,7 @@ md_assemble (char * str)
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if (* op_end == ',')
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{
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op_end = parse_imm (op_end + 1, & reg, 1, 1 << 31);
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op_end = parse_imm (op_end + 1, & reg, 1, 1u << 31);
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/* Further restrict the immediate to a power of two. */
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if ((reg & (reg - 1)) == 0)
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@ -4778,7 +4778,7 @@ gpr_read_mask (const struct mips_cl_insn *ip)
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if (pinfo2 & INSN2_READ_SP)
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mask |= 1 << SP;
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if (pinfo2 & INSN2_READ_GPR_31)
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mask |= 1 << 31;
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mask |= 1u << 31;
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/* Don't include register 0. */
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return mask & ~1;
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}
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@ -4797,7 +4797,7 @@ gpr_write_mask (const struct mips_cl_insn *ip)
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if (pinfo & INSN_WRITE_GPR_24)
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mask |= 1 << 24;
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if (pinfo & INSN_WRITE_GPR_31)
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mask |= 1 << 31;
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mask |= 1u << 31;
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if (pinfo & INSN_UDI)
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/* UDI instructions have traditionally been assumed to write to RD. */
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mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
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@ -5278,7 +5278,7 @@ nds32_elf_sethi_range (struct nds32_relocs_pattern *pattern)
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not, optimize option, 16 bit instruction is enable. */
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#define SET_ADDEND(size, convertible, optimize, insn16_on) \
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(((size) & 0xff) | ((convertible) ? 1 << 31 : 0) \
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(((size) & 0xff) | ((convertible) ? 1u << 31 : 0) \
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| ((optimize) ? 1 << 30 : 0) | (insn16_on ? 1 << 29 : 0))
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#define MAC_COMBO (E_NDS32_HAS_FPU_MAC_INST|E_NDS32_HAS_MAC_DX_INST)
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@ -2710,7 +2710,7 @@ nios2_assemble_arg_R (const char *token, nios2_insn_infoS *insn)
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mask = (reglist & 0x00ffc000) >> 14;
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if (reglist & (1 << 28))
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mask |= 1 << 10;
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if (reglist & (1 << 31))
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if (reglist & (1u << 31))
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mask |= 1 << 11;
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}
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insn->insn_code |= SET_IW_F1X4L17_REGMASK (mask);
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