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Fix tests for PR 18500 so that they will pass for big-endian ARM toolchains.

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PR gas/18500
	* gas/arm/vfpv3xd-ldr_immediate.d: Update test for big-endian ARM
	toolchains.
	* gas/arm/vfpv3-ldr_immediate.d: Likewise.
	* gas/arm/vfpv2-ldr_immediate.d: Likewise.
This commit is contained in:
Nick Clifton 2015-10-21 17:25:28 +01:00
parent abeead094e
commit a846e9c187
4 changed files with 42 additions and 34 deletions
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8
gas/testsuite/ChangeLog
View File

@ -1,3 +1,11 @@
2015-10-21 Nick Clifton <nickc@redhat.com>
PR gas/18500
* gas/arm/vfpv3xd-ldr_immediate.d: Update test for big-endian ARM
toolchains.
* gas/arm/vfpv3-ldr_immediate.d: Likewise.
* gas/arm/vfpv2-ldr_immediate.d: Likewise.
2015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* gas/s390/esa-g5.d: Use odd GPR for the second operand.

28
gas/testsuite/gas/arm/vfpv2-ldr_immediate.d
View File

@ -8,43 +8,43 @@ Disassembly of section \.text:
0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
0[0-9a-fx]+ .*00000000 .*
0[0-9a-fx]+ .*3fbe0000 .*
0[0-9a-fx]+ .*[00000000|3fbe0000] .*
0[0-9a-fx]+ .*[3fbe0000|00000000] .*
0[0-9a-fx]+ .*3df00000 .*
.*
0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
0[0-9a-fx]+ .*00000000 .*
0[0-9a-fx]+ .*bfc00000 .*
0[0-9a-fx]+ .*[00000000|bfc00000] .*
0[0-9a-fx]+ .*[bfc00000|00000000] .*
0[0-9a-fx]+ .*be000000 .*
.*
0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
0[0-9a-fx]+ .*00000000 .*
0[0-9a-fx]+ .*3fc00000 .*
0[0-9a-fx]+ .*[00000000|3fc00000] .*
0[0-9a-fx]+ .*[3fc00000|00000000] .*
0[0-9a-fx]+ .*3e000000 .*
.*
0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
0[0-9a-fx]+ .*00000000 .*
0[0-9a-fx]+ .*3fe08000 .*
0[0-9a-fx]+ .*[00000000|3fe08000] .*
0[0-9a-fx]+ .*[3fe08000|00000000] .*
0[0-9a-fx]+ .*3f040000 .*
.*
0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
0[0-9a-fx]+ .*00000000 .*
0[0-9a-fx]+ .*3fef0000 .*
0[0-9a-fx]+ .*[00000000|3fef0000] .*
0[0-9a-fx]+ .*[3fef0000|00000000] .*
0[0-9a-fx]+ .*3f780000 .*
.*
0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
0[0-9a-fx]+ .*00000000 .*
0[0-9a-fx]+ .*403f0000 .*
0[0-9a-fx]+ .*[00000000|403f0000] .*
0[0-9a-fx]+ .*[403f0000|00000000] .*
0[0-9a-fx]+ .*41f80000 .*
.*
0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
0[0-9a-fx]+ .*00000000 .*
0[0-9a-fx]+ .*40400000 .*
0[0-9a-fx]+ .*[00000000|40400000] .*
0[0-9a-fx]+ .*[40400000|00000000] .*
0[0-9a-fx]+ .*42000000 .*
#pass

12
gas/testsuite/gas/arm/vfpv3-ldr_immediate.d
View File

@ -8,8 +8,8 @@ Disassembly of section \.text:
0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
0[0-9a-fx]+ .*00000000 .*
0[0-9a-fx]+ .*3fbe0000 .*
0[0-9a-fx]+ .*[00000000|3fbe0000] .*
0[0-9a-fx]+ .*[3fbe0000|00000000] .*
0[0-9a-fx]+ .*3df00000 .*
.*
@ -19,8 +19,8 @@ Disassembly of section \.text:
0[0-9a-fx]+ .*eeb40a00 (vmov\.f32|fconsts) s0, #64.*
0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
0[0-9a-fx]+ .*00000000 .*
0[0-9a-fx]+ .*3fe08000 .*
0[0-9a-fx]+ .*[00000000|3fe08000] .*
0[0-9a-fx]+ .*[3fe08000|00000000] .*
0[0-9a-fx]+ .*3f040000 .*
.*
0[0-9a-fx]+ .*eeb60b0f (vmov\.f64|fconstd) d0, #111.*
@ -29,7 +29,7 @@ Disassembly of section \.text:
0[0-9a-fx]+ .*eeb30a0f (vmov\.f32|fconsts) s0, #63.*
0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
0[0-9a-fx]+ .*00000000 .*
0[0-9a-fx]+ .*40400000 .*
0[0-9a-fx]+ .*[00000000|40400000] .*
0[0-9a-fx]+ .*[40400000|00000000] .*
0[0-9a-fx]+ .*42000000 .*
#pass

28
gas/testsuite/gas/arm/vfpv3xd-ldr_immediate.d
View File

@ -8,35 +8,35 @@ Disassembly of section \.text:
0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
0[0-9a-fx]+ .*00000000 .*
0[0-9a-fx]+ .*3fbe0000 .*
0[0-9a-fx]+ .*[00000000|3fbe0000] .*
0[0-9a-fx]+ .*[3fbe0000|00000000] .*
0[0-9a-fx]+ .*3df00000 .*
.*
0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
0[0-9a-fx]+ .*eebc0a00 (vmov\.f32|fconsts) s0, #192.*
0[0-9a-fx]+ .*00000000 .*
0[0-9a-fx]+ .*bfc00000 .*
0[0-9a-fx]+ .*[00000000|bfc00000] .*
0[0-9a-fx]+ .*[bfc00000|00000000] .*
0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
0[0-9a-fx]+ .*eeb40a00 (vmov\.f32|fconsts) s0, #64.*
0[0-9a-fx]+ .*00000000 .*
0[0-9a-fx]+ .*3fc00000 .*
0[0-9a-fx]+ .*[00000000|3fc00000] .*
0[0-9a-fx]+ .*[3fc00000|00000000] .*
0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
0[0-9a-fx]+ .*00000000 .*
0[0-9a-fx]+ .*3fe08000 .*
0[0-9a-fx]+ .*[00000000|3fe08000] .*
0[0-9a-fx]+ .*[3fe08000|00000000] .*
0[0-9a-fx]+ .*3f040000 .*
.*
0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
0[0-9a-fx]+ .*eeb60a0f (vmov\.f32|fconsts) s0, #111.*
0[0-9a-fx]+ .*00000000 .*
0[0-9a-fx]+ .*3fef0000 .*
0[0-9a-fx]+ .*[00000000|3fef0000] .*
0[0-9a-fx]+ .*[3fef0000|00000000] .*
0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
0[0-9a-fx]+ .*eeb30a0f (vmov\.f32|fconsts) s0, #63.*
0[0-9a-fx]+ .*00000000 .*
0[0-9a-fx]+ .*403f0000 .*
0[0-9a-fx]+ .*[00000000|403f0000] .*
0[0-9a-fx]+ .*[403f0000|00000000] .*
0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
0[0-9a-fx]+ .*00000000 .*
0[0-9a-fx]+ .*40400000 .*
0[0-9a-fx]+ .*[00000000|40400000] .*
0[0-9a-fx]+ .*[40400000|00000000] .*
0[0-9a-fx]+ .*42000000 .*
#pass