* config/tc-i386.h (md_end): Define.
(i386_elf_emit_arch_note): Declare. (CpuUnknown): Delete. * config/tc-i386.c (default_arch): Constify. (smallest_imm_type): Remove CpuUnknown test. (md_assemble): Don't bother checking cpu_arch_flags non-zero. (i386_elf_emit_arch_note): New function.
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@ -1,5 +1,13 @@
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2001-11-15 Alan Modra <amodra@bigpond.net.au>
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* config/tc-i386.h (md_end): Define.
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(i386_elf_emit_arch_note): Declare.
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(CpuUnknown): Delete.
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* config/tc-i386.c (default_arch): Constify.
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(smallest_imm_type): Remove CpuUnknown test.
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(md_assemble): Don't bother checking cpu_arch_flags non-zero.
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(i386_elf_emit_arch_note): New function.
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* po/POTFILES.in: Regenerate.
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2001-11-15 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
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@ -77,7 +77,7 @@ static bfd_reloc_code_real_type reloc
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#ifndef DEFAULT_ARCH
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#define DEFAULT_ARCH "i386"
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#endif
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static char *default_arch = DEFAULT_ARCH;
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static const char *default_arch = DEFAULT_ARCH;
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/* 'md_assemble ()' gathers together information and puts it into a
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i386_insn. */
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@ -539,8 +539,7 @@ static int
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smallest_imm_type (num)
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offsetT num;
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{
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if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64)
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&& !(cpu_arch_flags & (CpuUnknown)))
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if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
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{
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/* This code is disabled on the 486 because all the Imm1 forms
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in the opcode table are slower on the i486. They're the
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@ -1393,18 +1392,15 @@ md_assemble (line)
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}
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/* Check if instruction is supported on specified architecture. */
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if (cpu_arch_flags != 0)
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if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64))
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& ~(cpu_arch_flags & ~(Cpu64 | CpuNo64)))
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{
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if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64))
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& ~(cpu_arch_flags & ~(Cpu64 | CpuNo64)))
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{
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as_warn (_("`%s' is not supported on `%s'"),
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current_templates->start->name, cpu_arch_name);
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}
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else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
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{
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as_warn (_("use .code16 to ensure correct addressing mode"));
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}
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as_warn (_("`%s' is not supported on `%s'"),
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current_templates->start->name, cpu_arch_name);
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}
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else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
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{
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as_warn (_("use .code16 to ensure correct addressing mode"));
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}
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/* Check for rep/repne without a string instruction. */
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@ -4661,6 +4657,48 @@ i386_target_format ()
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}
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#endif /* OBJ_MAYBE_ more than one */
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#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
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void i386_elf_emit_arch_note ()
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{
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if (OUTPUT_FLAVOR == bfd_target_elf_flavour
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&& cpu_arch_name != NULL)
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{
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char *p;
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asection *seg = now_seg;
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subsegT subseg = now_subseg;
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Elf_Internal_Note i_note;
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Elf_External_Note e_note;
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asection *note_secp;
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int len;
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/* Create the .note section. */
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note_secp = subseg_new (".note", 0);
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bfd_set_section_flags (stdoutput,
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note_secp,
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SEC_HAS_CONTENTS | SEC_READONLY);
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/* Process the arch string. */
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len = strlen (cpu_arch_name);
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i_note.namesz = len + 1;
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i_note.descsz = 0;
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i_note.type = NT_ARCH;
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p = frag_more (sizeof (e_note.namesz));
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md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
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p = frag_more (sizeof (e_note.descsz));
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md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
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p = frag_more (sizeof (e_note.type));
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md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
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p = frag_more (len + 1);
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strcpy (p, cpu_arch_name);
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frag_align (2, 0, 0);
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subseg_set (seg, subseg);
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}
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}
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#endif
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#endif /* BFD_ASSEMBLER */
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symbolS *
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@ -111,6 +111,11 @@ extern const char *i386_target_format PARAMS ((void));
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#endif
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#endif
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#if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF))
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#define md_end i386_elf_emit_arch_note
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extern void i386_elf_emit_arch_note PARAMS ((void));
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#endif
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#else /* ! BFD_ASSEMBLER */
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/* COFF STUFF */
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@ -293,7 +298,6 @@ typedef struct
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#define CpuSSE 0x1000 /* Streaming SIMD extensions required */
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#define CpuSSE2 0x2000 /* Streaming SIMD extensions 2 required */
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#define Cpu3dnow 0x4000 /* 3dnow! support required */
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#define CpuUnknown 0x8000 /* The CPU is unknown, be on the safe side. */
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/* These flags are set by gas depending on the flag_code. */
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#define Cpu64 0x4000000 /* 64bit support required */
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