PowerPC VLE insn set additions
opcodes/ * ppc-opc.c (ELEV): Define. (vle_opcodes): Add se_rfgi and e_sc. (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx for E200Z4. gas/ * testsuite/gas/ppc/vle.s: Format. Add se_rfgi and e_sc. * testsuite/gas/ppc/vle.d: Update.
This commit is contained in:
Alan Modra
parent
ebe553db6c
commit
a8cc8a548e
@ -1,3 +1,8 @@
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2017-04-22 Alan Modra <amodra@gmail.com>
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* testsuite/gas/ppc/vle.s: Format. Add se_rfgi and e_sc.
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* testsuite/gas/ppc/vle.d: Update.
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2017-04-21 Nick Clifton <nickc@redhat.com>
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PR binutils/21380
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@ -148,3 +148,7 @@ Disassembly of section \.text:
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194: e9 c2 se_bl 118 <middle_label>
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196: 79 ff ff 82 e_b 118 <middle_label>
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19a: 79 ff fe 67 e_bl 0 <start_label>
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19e: 00 0c se_rfgi
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1a0: 7c 00 00 48 e_sc
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1a4: 7c 00 00 48 e_sc
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1a8: 7c 00 08 48 e_sc 1
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@ -41,144 +41,148 @@
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.equ r31,31
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.equ r32,32
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.equ rsp,r1
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start_label:
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start_label:
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e_add16i r4,r3,27
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e_add2i. r0,0x3456
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e_add2is r1,0x4321
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e_addi. r2,r6,SCI0
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e_addi r3,r5,SCI1
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e_addic. r4,r4,SCI2
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e_addic r7,r8,SCI3
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e_and2i. r9,0xfeed
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e_and2is. r10,5
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e_andi. r11,r13,0x39
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e_andi r12,r15,SCI2
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e_b middle_label
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e_bl extern_subr
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e_bc 0,3,start_label
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e_bcl 1,15,extern_subr
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e_add2i. r0,0x3456
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e_add2is r1,0x4321
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e_addi. r2,r6,SCI0
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e_addi r3,r5,SCI1
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e_addic. r4,r4,SCI2
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e_addic r7,r8,SCI3
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e_and2i. r9,0xfeed
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e_and2is. r10,5
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e_andi. r11,r13,0x39
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e_andi r12,r15,SCI2
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e_b middle_label
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e_bl extern_subr
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e_bc 0,3,start_label
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e_bcl 1,15,extern_subr
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e_cmp16i r2,0x3333
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e_cmpi 2,r6,SCI1
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e_cmph 1,r7,r11
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e_cmph16i r12,0xfdef
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e_cmphl 0,r6,r8
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e_cmphl16i r13,0x1234
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e_cmpl16i r1, 0xfee0
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e_cmpli 1,r3,SCI3
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e_crand 0x1d,3,0
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e_crandc 0,2,0x1d
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e_creqv 15,16,17
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e_crnand 0xf,0,3
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e_crnor 0xf,0,3
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e_cror 12,13,14
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e_crorc 19,18,17
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e_crxor 0,0,0
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e_lbz r7,0xffffcc0d(r3)
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e_lbzu r7,-52(r5)
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e_lha r8,0x1ff(r10)
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e_lhau r8,-1(r1)
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e_cmpl16i r1, 0xfee0
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e_cmpli 1,r3,SCI3
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e_crand 0x1d,3,0
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e_crandc 0,2,0x1d
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e_creqv 15,16,17
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e_crnand 0xf,0,3
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e_crnor 0xf,0,3
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e_cror 12,13,14
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e_crorc 19,18,17
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e_crxor 0,0,0
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e_lbz r7,0xffffcc0d(r3)
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e_lbzu r7,-52(r5)
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e_lha r8,0x1ff(r10)
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e_lhau r8,-1(r1)
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e_lhz r7,6200(r0)
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e_lhzu r7,62(r0)
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e_li r0,0x33333
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e_lis r1,0x3333
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e_lmw r5,24(r3)
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e_lwz r5,10024(r3)
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e_lwzu r6,0x72(r2)
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e_mcrf 1,6
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e_mulli r9,r10,SCI0
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e_mull2i r1,0x668
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e_or2i r5,0x2345
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e_or2is r5,0xa345
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e_ori. r7,r9,SCI0
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e_ori r7,r8,SCI1
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e_rlw r18, r22,r0
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e_rlw. r8, r2,r0
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e_rlwi r20,r3,21
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e_rlwi. r2,r3,21
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e_rlwimi r4,r19,13,8,15
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e_rlwinm r4,r1,13,1,17
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e_slwi r12,r19,6
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e_slwi. r12,r10,20
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e_srwi r0,r1,16
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e_srwi. r0,r1,11
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e_stb r3,22000(r1)
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e_stbu r19,-4(r22)
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e_sth r0,666(r21)
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e_sthu r1,-1(r23)
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e_stmw r0,4(r3)
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e_stw r3,16161(r0)
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e_stwu r22,0xffffffee(r4)
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e_subfic r0,r21,SCI2
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e_subfic. r22,r0,SCI3
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e_xori r21,r3,SCI1
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e_xori. r0,r20,SCI0
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middle_label:
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se_add r31,r7
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se_addi r28,0x1f
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se_and r0,r1
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se_and. r1,r0
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se_andc r2, r3
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se_andi r4,0x11
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se_b middle_label
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se_bl extern_subr
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se_bc 1,3,not_end_label
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se_bclri r27,0x12
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se_bctr
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se_bctrl
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se_bgeni r7,17
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se_blr
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se_blrl
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se_bmaski r6,0
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se_bseti r0,1
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se_btsti r4,7
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se_cmp r0,r1
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se_cmph r31,r28
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se_cmphl r1,r25
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se_cmpi r3,22
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se_cmpl r6,r7
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se_cmpli r28,0xc
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se_extsb r1
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se_extsh r2
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se_extzb r30
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se_extzh r24
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e_li r0,0x33333
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e_lis r1,0x3333
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e_lmw r5,24(r3)
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e_lwz r5,10024(r3)
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e_lwzu r6,0x72(r2)
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e_mcrf 1,6
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e_mulli r9,r10,SCI0
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e_mull2i r1,0x668
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e_or2i r5,0x2345
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e_or2is r5,0xa345
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e_ori. r7,r9,SCI0
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e_ori r7,r8,SCI1
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e_rlw r18, r22,r0
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e_rlw. r8, r2,r0
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e_rlwi r20,r3,21
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e_rlwi. r2,r3,21
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e_rlwimi r4,r19,13,8,15
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e_rlwinm r4,r1,13,1,17
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e_slwi r12,r19,6
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e_slwi. r12,r10,20
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e_srwi r0,r1,16
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e_srwi. r0,r1,11
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e_stb r3,22000(r1)
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e_stbu r19,-4(r22)
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e_sth r0,666(r21)
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e_sthu r1,-1(r23)
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e_stmw r0,4(r3)
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e_stw r3,16161(r0)
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e_stwu r22,0xffffffee(r4)
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e_subfic r0,r21,SCI2
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e_subfic. r22,r0,SCI3
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e_xori r21,r3,SCI1
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e_xori. r0,r20,SCI0
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middle_label:
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se_add r31,r7
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se_addi r28,0x1f
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se_and r0,r1
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se_and. r1,r0
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se_andc r2, r3
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se_andi r4,0x11
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se_b middle_label
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se_bl extern_subr
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se_bc 1,3,not_end_label
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se_bclri r27,0x12
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se_bctr
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se_bctrl
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se_bgeni r7,17
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se_blr
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se_blrl
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se_bmaski r6,0
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se_bseti r0,1
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se_btsti r4,7
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se_cmp r0,r1
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se_cmph r31,r28
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se_cmphl r1,r25
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se_cmpi r3,22
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se_cmpl r6,r7
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se_cmpli r28,0xc
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se_extsb r1
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se_extsh r2
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se_extzb r30
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se_extzh r24
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not_end_label:
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se_illegal
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se_isync
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se_lbz r1,8(r24)
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se_lhz r24,18(r4)
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se_illegal
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se_isync
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se_lbz r1,8(r24)
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se_lhz r24,18(r4)
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se_li r4,0x4f
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se_lwz r6,60(r0)
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se_mfar r7,r8
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se_mfctr r3
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se_mflr r4
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se_mr r31,r0
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se_mtar r23,r2
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se_mtctr r6
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se_mtlr r31
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se_lwz r6,60(r0)
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se_mfar r7,r8
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se_mfctr r3
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se_mflr r4
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se_mr r31,r0
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se_mtar r23,r2
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se_mtctr r6
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se_mtlr r31
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se_mullw r3,r4
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se_neg r24
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se_not r25
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se_or r0,r1
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se_rfci
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se_rfdi
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se_rfi
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se_sc
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se_slw r5,r6
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se_slwi r7,7
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se_sraw r6,r30
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se_srawi r25,8
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se_srw r30,r0
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se_srwi r29,25
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se_stb r0,10(r2)
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se_sth r1,12(r30)
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se_stw r7,0(r29)
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se_sub r1,r2
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se_subf r29,r26
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se_subi r7,24
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se_neg r24
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se_not r25
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se_or r0,r1
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se_rfci
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se_rfdi
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se_rfi
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se_sc
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se_slw r5,r6
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se_slwi r7,7
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se_sraw r6,r30
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se_srawi r25,8
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se_srw r30,r0
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se_srwi r29,25
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se_stb r0,10(r2)
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se_sth r1,12(r30)
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se_stw r7,0(r29)
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se_sub r1,r2
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se_subf r29,r26
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se_subi r7,24
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end_label:
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se_subi. r25,19
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se_bl middle_label
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e_b middle_label
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e_bl start_label
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se_subi. r25,19
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se_bl middle_label
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e_b middle_label
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e_bl start_label
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se_rfgi
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e_sc
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e_sc 0
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e_sc 1
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@ -1,3 +1,11 @@
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2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
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Alan Modra <amodra@gmail.com>
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* ppc-opc.c (ELEV): Define.
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(vle_opcodes): Add se_rfgi and e_sc.
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(powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
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for E200Z4.
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2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
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* sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
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@ -652,8 +652,10 @@ const struct powerpc_operand powerpc_operands[] =
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#define SH6_MASK ((0x1f << 11) | (1 << 1))
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{ 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 },
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/* The SH field of the tlbwe instruction, which is optional. */
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/* The SH field of some variants of the tlbre and tlbwe
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instructions, and the ELEV field of the e_sc instruction. */
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#define SHO SH6 + 1
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#define ELEV SHO
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{ 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
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/* The SI field in a D form instruction. */
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@ -5874,7 +5876,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"mcrxr", X(31,512), XBFRARB_MASK, COM, POWER7, {BF}},
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{"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}},
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{"lbdx", X(31,515), X_MASK, E500MC, 0, {RT, RA, RB}},
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{"lbdx", X(31,515), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}},
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{"bblels", X(31,518), X_MASK, PPCBRLK, 0, {0}},
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@ -5925,7 +5927,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}},
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{"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}},
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{"lhdx", X(31,547), X_MASK, E500MC, 0, {RT, RA, RB}},
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{"lhdx", X(31,547), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}},
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{"lvtrx", X(31,549), X_MASK, E6500, 0, {VD, RA0, RB}},
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@ -5949,7 +5951,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, 0, {BF}},
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{"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}},
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{"lwdx", X(31,579), X_MASK, E500MC, 0, {RT, RA, RB}},
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{"lwdx", X(31,579), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}},
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{"lvtlx", X(31,581), X_MASK, E6500, 0, {VD, RA0, RB}},
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@ -6000,7 +6002,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
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{"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}},
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{"stbdx", X(31,643), X_MASK, E500MC, 0, {RS, RA, RB}},
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{"stbdx", X(31,643), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}},
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{"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}},
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{"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
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@ -6038,7 +6040,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}},
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{"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}},
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{"sthdx", X(31,675), X_MASK, E500MC, 0, {RS, RA, RB}},
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{"sthdx", X(31,675), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}},
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{"stvfrx", X(31,677), X_MASK, E6500, 0, {VS, RA0, RB}},
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@ -6056,7 +6058,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}},
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{"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}},
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{"stwdx", X(31,707), X_MASK, E500MC, 0, {RS, RA, RB}},
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{"stwdx", X(31,707), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}},
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{"stvflx", X(31,709), X_MASK, E6500, 0, {VS, RA0, RB}},
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@ -7109,6 +7111,7 @@ const struct powerpc_opcode vle_opcodes[] = {
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{"se_rfci", C(9), C_MASK, PPCVLE, 0, {}},
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{"se_rfdi", C(10), C_MASK, PPCVLE, 0, {}},
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{"se_rfmci", C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}},
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{"se_rfgi", C(12), C_MASK, PPCVLE, 0, {}},
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{"se_not", SE_R(0,2), SE_R_MASK, PPCVLE, 0, {RX}},
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{"se_neg", SE_R(0,3), SE_R_MASK, PPCVLE, 0, {RX}},
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{"se_mflr", SE_R(0,8), SE_R_MASK, PPCVLE, 0, {RX}},
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@ -7266,6 +7269,7 @@ const struct powerpc_opcode vle_opcodes[] = {
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{"e_btl", EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
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{"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
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{"e_sc", X(31,36), XRTRA_MASK, PPCVLE, 0, {ELEV}},
|
||||
{"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
|
||||
{"e_crandc", XL(31,129), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
|
||||
{"e_crnand", XL(31,225), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
|
||||
|
||||
Loading…
Reference in New Issue
Block a user