* config/m68k-parse.h (m68k_register): Add ROMBAR0, ASID.
* config/tc-m68k.c (mcfv4e_ctrl): Add ColdFire specific names. (mcf5475_ctrl, mcf5485_ctrl): New. (m68k_cpus): Use mcf5485_ctrl and mcf5485_ctrl for those families. (m68k_ip): Add ASID, MMUBAR, ROMBAR0 handling. (init_table): Add asid, mmubar, adjust rombar0.
This commit is contained in:
Nathan Sidwell
parent
1306df90a9
commit
a8e24a5610
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@ -1,3 +1,12 @@
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2007-02-15 Nathan Sidwell <nathan@codesourcery.com>
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* config/m68k-parse.h (m68k_register): Add ROMBAR0, ASID.
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* config/tc-m68k.c (mcfv4e_ctrl): Add ColdFire specific names.
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(mcf5475_ctrl, mcf5485_ctrl): New.
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(m68k_cpus): Use mcf5485_ctrl and mcf5485_ctrl for those families.
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(m68k_ip): Add ASID, MMUBAR, ROMBAR0 handling.
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(init_table): Add asid, mmubar, adjust rombar0.
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2007-02-14 Alan Modra <amodra@bigpond.net.au>
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* config/tc-i386.h (Seg2ShortForm, Seg3ShortForm): Delete.
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@ -116,6 +116,7 @@ enum m68k_register
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RAMBAR0,
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RAMBAR1,
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MMUBAR, /* mcfv4e added these. */
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ROMBAR0, /* mcfv4e added these. */
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ROMBAR1, /* mcfv4e added these. */
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MPCR, EDRAMBAR, SECMBAR, /* mcfv4e added these. */
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PCR1U0, PCR1L0, PCR1U1, PCR1L1,/* mcfv4e added these. */
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@ -126,6 +127,7 @@ enum m68k_register
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FLASHBAR, RAMBAR, /* mcf528x added these. */
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MBAR2, /* mcf5249 added this. */
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MBAR,
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ASID, /* m5475. */
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CAC, /* fido added this. */
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MBB,
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#define last_movec_reg MBB
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@ -225,10 +225,37 @@ static const enum m68k_register mcf5373_ctrl[] = {
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0
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};
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static const enum m68k_register mcfv4e_ctrl[] = {
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CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, VBR, PC, ROMBAR,
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ROMBAR1, RAMBAR0, RAMBAR1, MPCR, EDRAMBAR, SECMBAR, MBAR, MBAR0, MBAR1,
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CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
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VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
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MBAR, SECMBAR,
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MPCR /* Multiprocessor Control register */,
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EDRAMBAR /* Embedded DRAM Base Address Register */,
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/* Permutation control registers. */
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PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
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PCR3U0, PCR3L0, PCR3U1, PCR3L1,
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/* Legacy names */
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TC /* ASID */, BUSCR /* MMUBAR */,
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ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
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MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
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ROMBAR /* ROMBAR0 */,
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0
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};
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static const enum m68k_register mcf5475_ctrl[] = {
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CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
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VBR, PC, RAMBAR0, RAMBAR1, MBAR,
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/* Legacy names */
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TC /* ASID */, BUSCR /* MMUBAR */,
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ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
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MBAR1 /* MBAR */, ROMBAR /* ROMBAR0 */,
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0
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};
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static const enum m68k_register mcf5485_ctrl[] = {
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CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
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VBR, PC, RAMBAR0, RAMBAR1, MBAR,
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/* Legacy names */
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TC /* ASID */, BUSCR /* MMUBAR */,
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ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
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MBAR1 /* MBAR */, ROMBAR /* ROMBAR0 */,
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0
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};
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static const enum m68k_register fido_ctrl[] = {
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@ -541,21 +568,21 @@ static const struct m68k_cpu m68k_cpus[] =
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{mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf_ctrl, "5407",0},
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{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5470", -1},
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{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5471", -1},
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{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5472", -1},
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{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5473", -1},
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{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5474", -1},
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{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5475", -1},
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{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "547x", 0},
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{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
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{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
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{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
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{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
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{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
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{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
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{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
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{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5480", -1},
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{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5481", -1},
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{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5482", -1},
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{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5483", -1},
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{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5484", -1},
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{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5485", -1},
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{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "548x", 0},
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{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
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{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
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{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
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{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
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{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
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{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
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{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
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{fido_a, fido_ctrl, "fido", 1},
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@ -2964,6 +2991,7 @@ m68k_ip (char *instring)
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tmpreg = 0x002;
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break;
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case TC:
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case ASID:
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tmpreg = 0x003;
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break;
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case ACR0:
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@ -2983,6 +3011,7 @@ m68k_ip (char *instring)
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tmpreg = 0x007;
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break;
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case BUSCR:
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case MMUBAR:
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tmpreg = 0x008;
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break;
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@ -3014,6 +3043,7 @@ m68k_ip (char *instring)
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tmpreg = 0x808;
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break;
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case ROMBAR:
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case ROMBAR0:
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tmpreg = 0xC00;
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break;
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case ROMBAR1:
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@ -3759,7 +3789,7 @@ static const struct init_entry init_table[] =
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{ "dacr0", DTT0 }, /* Data Access Control Register 0. */
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{ "dacr1", DTT1 }, /* Data Access Control Register 0. */
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/* mcf5200 versions of same. The ColdFire programmer's reference
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/* Coldfire versions of same. The ColdFire programmer's reference
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manual indicated that the order is 2,3,0,1, but Ken Rose
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<rose@netcom.com> says that 0,1,2,3 is the correct order. */
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{ "acr0", ACR0 }, /* Access Control Unit 0. */
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@ -3769,12 +3799,14 @@ static const struct init_entry init_table[] =
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{ "tc", TC }, /* MMU Translation Control Register. */
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{ "tcr", TC },
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{ "asid", ASID },
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{ "mmusr", MMUSR }, /* MMU Status Register. */
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{ "srp", SRP }, /* User Root Pointer. */
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{ "urp", URP }, /* Supervisor Root Pointer. */
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{ "buscr", BUSCR },
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{ "mmubar", MMUBAR },
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{ "pcr", PCR },
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{ "rombar", ROMBAR }, /* ROM Base Address Register. */
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@ -3784,7 +3816,7 @@ static const struct init_entry init_table[] =
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{ "mbar0", MBAR0 }, /* mcfv4e registers. */
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{ "mbar1", MBAR1 }, /* mcfv4e registers. */
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{ "rombar0", ROMBAR }, /* mcfv4e registers. */
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{ "rombar0", ROMBAR0 }, /* mcfv4e registers. */
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{ "rombar1", ROMBAR1 }, /* mcfv4e registers. */
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{ "mpcr", MPCR }, /* mcfv4e registers. */
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{ "edrambar", EDRAMBAR }, /* mcfv4e registers. */
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