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Remove i860, i960, bout and aout-adobe targets 

Plus remove a few leftovers from the 29k support.

include/
	* aout/adobe.h: Delete.
	* aout/reloc.h: Delete.
	* coff/i860.h: Delete.
	* coff/i960.h: Delete.
	* elf/i860.h: Delete.
	* elf/i960.h: Delete.
	* opcode/i860.h: Delete.
	* opcode/i960.h: Delete.
	* aout/aout64.h (enum reloc_type): Trim off 29k and other unused values.
	* aout/ar.h (ARMAGB): Remove.
	* coff/internal.h (struct internal_aouthdr, struct internal_scnhdr,
	union internal_auxent): Remove i960 support.
bfd/
	* aout-adobe.c: Delete.
	* bout.c: Delete.
	* coff-i860.c: Delete.
	* coff-i960.c: Delete.
	* cpu-i860.c: Delete.
	* cpu-i960.c: Delete.
	* elf32-i860.c: Delete.
	* elf32-i960.c: Delete.
	* hosts/i860mach3.h: Delete.
	* Makefile.am: Remove i860, i960, bout, and adobe support.
	* archures.c: Remove i860 and i960 support.
	* coffcode.h: Likewise.
	* reloc.c: Likewise.
	* aoutx.h: Comment updates.
	* archive.c: Remove BOUT and i960 support.
	* bfd.c: Remove BOUT support.
	* coffswap.h: Remove i960 support.
	* config.bfd: Remove i860, i960 and adobe targets.
	* configure.ac: Remove adode, bout, i860, i960, icoff targets.
	* targets.c: Likewise.
	* ieee.c: Remove i960 support.
	* mach-o.c: Remove i860 support.
	* Makefile.in: Regenerate.
	* bfd-in2.h: Regenerate.
	* configure: Regenerate.
	* libbfd.h: Regenerate.
	* po/SRC-POTFILES.in: Regenerate.
opcodes/
	* opcodes/i860-dis.c: Delete.
	* opcodes/i960-dis.c: Delete.
	* Makefile.am: Remove i860 and i960 support.
	* configure.ac: Likewise.
	* disassemble.c: Likewise.
	* disassemble.h: Likewise.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* po/POTFILES.in: Regenerate.
binutils/
	* ieee.c: Remove i960 support.
	* od-macho.c: Remove i860 support.
	* readelf.c: Remove i860 and i960 support.
	* testsuite/binutils-all/objcopy.exp: Likewise.
	* testsuite/binutils-all/objdump.exp: Likewise.
	* testsuite/lib/binutils-common.exp: Likewise.
gas/
	* config/aout_gnu.h: Delete.
	* config/tc-i860.c: Delete.
	* config/tc-i860.h: Delete.
	* config/tc-i960.c: Delete.
	* config/tc-i960.h: Delete.
	* doc/c-i860.texi: Delete.
	* doc/c-i960.texi: Delete.
	* testsuite/gas/i860/README.i860: Delete.
	* testsuite/gas/i860/bitwise.d: Delete.
	* testsuite/gas/i860/bitwise.s: Delete.
	* testsuite/gas/i860/branch.d: Delete.
	* testsuite/gas/i860/branch.s: Delete.
	* testsuite/gas/i860/bte.d: Delete.
	* testsuite/gas/i860/bte.s: Delete.
	* testsuite/gas/i860/dir-align01.d: Delete.
	* testsuite/gas/i860/dir-align01.s: Delete.
	* testsuite/gas/i860/dir-intel01.d: Delete.
	* testsuite/gas/i860/dir-intel01.s: Delete.
	* testsuite/gas/i860/dir-intel02.d: Delete.
	* testsuite/gas/i860/dir-intel02.s: Delete.
	* testsuite/gas/i860/dir-intel03-err.l: Delete.
	* testsuite/gas/i860/dir-intel03-err.s: Delete.
	* testsuite/gas/i860/dual01.d: Delete.
	* testsuite/gas/i860/dual01.s: Delete.
	* testsuite/gas/i860/dual02-err.l: Delete.
	* testsuite/gas/i860/dual02-err.s: Delete.
	* testsuite/gas/i860/dual03.d: Delete.
	* testsuite/gas/i860/dual03.s: Delete.
	* testsuite/gas/i860/fldst01.d: Delete.
	* testsuite/gas/i860/fldst01.s: Delete.
	* testsuite/gas/i860/fldst02.d: Delete.
	* testsuite/gas/i860/fldst02.s: Delete.
	* testsuite/gas/i860/fldst03.d: Delete.
	* testsuite/gas/i860/fldst03.s: Delete.
	* testsuite/gas/i860/fldst04.d: Delete.
	* testsuite/gas/i860/fldst04.s: Delete.
	* testsuite/gas/i860/fldst05.d: Delete.
	* testsuite/gas/i860/fldst05.s: Delete.
	* testsuite/gas/i860/fldst06.d: Delete.
	* testsuite/gas/i860/fldst06.s: Delete.
	* testsuite/gas/i860/fldst07.d: Delete.
	* testsuite/gas/i860/fldst07.s: Delete.
	* testsuite/gas/i860/fldst08.d: Delete.
	* testsuite/gas/i860/fldst08.s: Delete.
	* testsuite/gas/i860/float01.d: Delete.
	* testsuite/gas/i860/float01.s: Delete.
	* testsuite/gas/i860/float02.d: Delete.
	* testsuite/gas/i860/float02.s: Delete.
	* testsuite/gas/i860/float03.d: Delete.
	* testsuite/gas/i860/float03.s: Delete.
	* testsuite/gas/i860/float04.d: Delete.
	* testsuite/gas/i860/float04.s: Delete.
	* testsuite/gas/i860/form.d: Delete.
	* testsuite/gas/i860/form.s: Delete.
	* testsuite/gas/i860/i860.exp: Delete.
	* testsuite/gas/i860/iarith.d: Delete.
	* testsuite/gas/i860/iarith.s: Delete.
	* testsuite/gas/i860/ldst01.d: Delete.
	* testsuite/gas/i860/ldst01.s: Delete.
	* testsuite/gas/i860/ldst02.d: Delete.
	* testsuite/gas/i860/ldst02.s: Delete.
	* testsuite/gas/i860/ldst03.d: Delete.
	* testsuite/gas/i860/ldst03.s: Delete.
	* testsuite/gas/i860/ldst04.d: Delete.
	* testsuite/gas/i860/ldst04.s: Delete.
	* testsuite/gas/i860/ldst05.d: Delete.
	* testsuite/gas/i860/ldst05.s: Delete.
	* testsuite/gas/i860/ldst06.d: Delete.
	* testsuite/gas/i860/ldst06.s: Delete.
	* testsuite/gas/i860/pfam.d: Delete.
	* testsuite/gas/i860/pfam.s: Delete.
	* testsuite/gas/i860/pfmam.d: Delete.
	* testsuite/gas/i860/pfmam.s: Delete.
	* testsuite/gas/i860/pfmsm.d: Delete.
	* testsuite/gas/i860/pfmsm.s: Delete.
	* testsuite/gas/i860/pfsm.d: Delete.
	* testsuite/gas/i860/pfsm.s: Delete.
	* testsuite/gas/i860/pseudo-ops01.d: Delete.
	* testsuite/gas/i860/pseudo-ops01.s: Delete.
	* testsuite/gas/i860/regress01.d: Delete.
	* testsuite/gas/i860/regress01.s: Delete.
	* testsuite/gas/i860/shift.d: Delete.
	* testsuite/gas/i860/shift.s: Delete.
	* testsuite/gas/i860/simd.d: Delete.
	* testsuite/gas/i860/simd.s: Delete.
	* testsuite/gas/i860/system.d: Delete.
	* testsuite/gas/i860/system.s: Delete.
	* testsuite/gas/i860/xp.d: Delete.
	* testsuite/gas/i860/xp.s: Delete.
	* Makefile.am: Remove i860 and i960 support.
	* configure.tgt: Likewise.
	* doc/Makefile.am: Likewise.
	* doc/all.texi: Likewise.
	* testsuite/gas/all/gas.exp
	* config/obj-coff.h: Remove i960 support.
	* doc/internals.texi: Likewise.
	* expr.c: Likewise.
	* read.c: Likewise.
	* write.c: Likewise.
	* write.h: Likewise.
	* testsuite/gas/lns/lns.exp: Likewise.
	* testsuite/gas/symver/symver.exp: Likewise.
	* config/tc-m68k.c: Remove BOUT support.
	* config/tc-score.c: Likewise.
	* config/tc-score7.c: Likewise.
	* config/tc-sparc.c: Likewise.
	* symbols.c: Likewise.
	* doc/h8.texi: Likewise.
	* configure.ac: Remove BOUT and i860 support.
	* doc/as.texinfo: Remove BOUT, i860 and i960 support
	* Makefile.in: Regenerate.
	* config.in: Regenerate.
	* configure: Regenerate.
	* doc/Makefile.in: Regenerate.
	* po/POTFILES.in: Regenerate.
ld/
	* emulparams/coff_i860.sh: Delete.
	* emulparams/elf32_i860.sh: Delete.
	* emulparams/elf32_i960.sh: Delete.
	* emulparams/gld960.sh: Delete.
	* emulparams/gld960coff.sh: Delete.
	* emulparams/lnk960.sh: Delete.
	* emultempl/gld960.em: Delete.
	* emultempl/gld960c.em: Delete.
	* emultempl/lnk960.em: Delete.
	* scripttempl/i860coff.sc: Delete.
	* scripttempl/i960.sc: Delete.
	* ld.texinfo: Remove i960 support.
	* Makefile.am: Remove i860 and i960 support.
	* configure.tgt: Likewise.
	* testsuite/ld-discard/extern.d: Likewise.
	* testsuite/ld-discard/start.d: Likewise.
	* testsuite/ld-discard/static.d: Likewise.
	* testsuite/ld-elf/compressed1d.d: Likewise.
	* testsuite/ld-elf/group1.d: Likewise.
	* testsuite/ld-elf/group3b.d: Likewise.
	* testsuite/ld-elf/group8a.d: Likewise.
	* testsuite/ld-elf/group8b.d: Likewise.
	* testsuite/ld-elf/group9a.d: Likewise.
	* testsuite/ld-elf/group9b.d: Likewise.
	* testsuite/ld-elf/linkonce2.d: Likewise.
	* testsuite/ld-elf/merge.d: Likewise.
	* testsuite/ld-elf/merge2.d: Likewise.
	* testsuite/ld-elf/merge3.d: Likewise.
	* testsuite/ld-elf/orphan-10.d: Likewise.
	* testsuite/ld-elf/orphan-11.d: Likewise.
	* testsuite/ld-elf/orphan-12.d: Likewise.
	* testsuite/ld-elf/orphan-9.d: Likewise.
	* testsuite/ld-elf/orphan-region.d: Likewise.
	* testsuite/ld-elf/orphan.d: Likewise.
	* testsuite/ld-elf/orphan3.d: Likewise.
	* testsuite/ld-elf/pr12851.d: Likewise.
	* testsuite/ld-elf/pr12975.d: Likewise.
	* testsuite/ld-elf/pr13177.d: Likewise.
	* testsuite/ld-elf/pr13195.d: Likewise.
	* testsuite/ld-elf/pr17550a.d: Likewise.
	* testsuite/ld-elf/pr17550b.d: Likewise.
	* testsuite/ld-elf/pr17550c.d: Likewise.
	* testsuite/ld-elf/pr17550d.d: Likewise.
	* testsuite/ld-elf/pr17615.d: Likewise.
	* testsuite/ld-elf/pr20528a.d: Likewise.
	* testsuite/ld-elf/pr20528b.d: Likewise.
	* testsuite/ld-elf/pr21562a.d: Likewise.
	* testsuite/ld-elf/pr21562b.d: Likewise.
	* testsuite/ld-elf/pr21562c.d: Likewise.
	* testsuite/ld-elf/pr21562d.d: Likewise.
	* testsuite/ld-elf/pr21562i.d: Likewise.
	* testsuite/ld-elf/pr21562j.d: Likewise.
	* testsuite/ld-elf/pr21562k.d: Likewise.
	* testsuite/ld-elf/pr21562l.d: Likewise.
	* testsuite/ld-elf/pr21562m.d: Likewise.
	* testsuite/ld-elf/pr21562n.d: Likewise.
	* testsuite/ld-elf/pr22677.d: Likewise.
	* testsuite/ld-elf/pr22836-1a.d: Likewise.
	* testsuite/ld-elf/pr22836-1b.d: Likewise.
	* testsuite/ld-elf/pr349.d: Likewise.
	* testsuite/ld-elf/sec-to-seg.exp: Likewise.
	* testsuite/ld-elf/sec64k.exp: Likewise.
	* testsuite/ld-elf/warn1.d: Likewise.
	* testsuite/ld-elf/warn2.d: Likewise.
	* testsuite/ld-elf/warn3.d: Likewise.
	* testsuite/lib/ld-lib.exp: Likewise.
	* Makefile.in: Regenerate.
	* po/BLD-POTFILES.in: Regenerate.
This commit is contained in:
Alan Modra 2018-04-11 18:46:05 +09:30
parent c43b2c546b
commit a8eb42a8b7
242 changed files with 380 additions and 21807 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
bfd/ChangeLog
View File

@ -1,3 +1,33 @@
2018-04-11 Alan Modra <amodra@gmail.com>
* aout-adobe.c: Delete.
* bout.c: Delete.
* coff-i860.c: Delete.
* coff-i960.c: Delete.
* cpu-i860.c: Delete.
* cpu-i960.c: Delete.
* elf32-i860.c: Delete.
* elf32-i960.c: Delete.
* hosts/i860mach3.h: Delete.
* Makefile.am: Remove i860, i960, bout, and adobe support.
* archures.c: Remove i860 and i960 support.
* coffcode.h: Likewise.
* reloc.c: Likewise.
* aoutx.h: Comment updates.
* archive.c: Remove BOUT and i960 support.
* bfd.c: Remove BOUT support.
* coffswap.h: Remove i960 support.
* config.bfd: Remove i860, i960 and adobe targets.
* configure.ac: Remove adode, bout, i860, i960, icoff targets.
* targets.c: Likewise.
* ieee.c: Remove i960 support.
* mach-o.c: Remove i860 support.
* Makefile.in: Regenerate.
* bfd-in2.h: Regenerate.
* configure: Regenerate.
* libbfd.h: Regenerate.
* po/SRC-POTFILES.in: Regenerate.
2018-04-09 Maciej W. Rozycki <macro@mips.com>
* elf64-mips.c (mips_elf64_write_rel): Handle a NULL BFD pointer

16
bfd/Makefile.am
View File

@ -114,8 +114,6 @@ ALL_MACHINES = \
cpu-iamcu.lo \
cpu-l1om.lo \
cpu-k1om.lo \
cpu-i860.lo \
cpu-i960.lo \
cpu-ia64.lo \
cpu-ip2k.lo \
cpu-iq2000.lo \
@ -204,8 +202,6 @@ ALL_MACHINES_CFILES = \
cpu-iamcu.c \
cpu-l1om.c \
cpu-k1om.c \
cpu-i860.c \
cpu-i960.c \
cpu-ia64.c \
cpu-ip2k.c \
cpu-iq2000.c \
@ -271,7 +267,6 @@ ALL_MACHINES_CFILES = \
# The .o files needed by all of the 32 bit vectors that are configured into
# target_vector in targets.c if configured with --enable-targets=all.
BFD32_BACKENDS = \
aout-adobe.lo \
aout-arm.lo \
aout-cris.lo \
aout-ns32k.lo \
@ -280,7 +275,6 @@ BFD32_BACKENDS = \
aout0.lo \
aout32.lo \
armnetbsd.lo \
bout.lo \
cf-i386lynx.lo \
cf-sparclynx.lo \
coff-apollo.lo \
@ -290,8 +284,6 @@ BFD32_BACKENDS = \
coff-h8300.lo \
coff-h8500.lo \
coff-i386.lo \
coff-i860.lo \
coff-i960.lo \
coff-m68k.lo \
coff-m88k.lo \
coff-mips.lo \
@ -347,8 +339,6 @@ BFD32_BACKENDS = \
elf32-i370.lo \
elf32-i386.lo \
elfxx-x86.lo \
elf32-i860.lo \
elf32-i960.lo \
elf32-ip2k.lo \
elf32-iq2000.lo \
elf32-lm32.lo \
@ -468,7 +458,6 @@ BFD32_BACKENDS = \
xtensa-modules.lo
BFD32_BACKENDS_CFILES = \
aout-adobe.c \
aout-arm.c \
aout-cris.c \
aout-ns32k.c \
@ -477,7 +466,6 @@ BFD32_BACKENDS_CFILES = \
aout0.c \
aout32.c \
armnetbsd.c \
bout.c \
cf-i386lynx.c \
cf-sparclynx.c \
coff-apollo.c \
@ -487,8 +475,6 @@ BFD32_BACKENDS_CFILES = \
coff-h8300.c \
coff-h8500.c \
coff-i386.c \
coff-i860.c \
coff-i960.c \
coff-m68k.c \
coff-m88k.c \
coff-mips.c \
@ -544,8 +530,6 @@ BFD32_BACKENDS_CFILES = \
elf32-i370.c \
elf32-i386.c \
elfxx-x86.c \
elf32-i860.c \
elf32-i960.c \
elf32-ip2k.c \
elf32-iq2000.c \
elf32-lm32.c \

24
bfd/Makefile.in
View File

@ -447,8 +447,6 @@ ALL_MACHINES = \
cpu-iamcu.lo \
cpu-l1om.lo \
cpu-k1om.lo \
cpu-i860.lo \
cpu-i960.lo \
cpu-ia64.lo \
cpu-ip2k.lo \
cpu-iq2000.lo \
@ -537,8 +535,6 @@ ALL_MACHINES_CFILES = \
cpu-iamcu.c \
cpu-l1om.c \
cpu-k1om.c \
cpu-i860.c \
cpu-i960.c \
cpu-ia64.c \
cpu-ip2k.c \
cpu-iq2000.c \
@ -605,7 +601,6 @@ ALL_MACHINES_CFILES = \
# The .o files needed by all of the 32 bit vectors that are configured into
# target_vector in targets.c if configured with --enable-targets=all.
BFD32_BACKENDS = \
aout-adobe.lo \
aout-arm.lo \
aout-cris.lo \
aout-ns32k.lo \
@ -614,7 +609,6 @@ BFD32_BACKENDS = \
aout0.lo \
aout32.lo \
armnetbsd.lo \
bout.lo \
cf-i386lynx.lo \
cf-sparclynx.lo \
coff-apollo.lo \
@ -624,8 +618,6 @@ BFD32_BACKENDS = \
coff-h8300.lo \
coff-h8500.lo \
coff-i386.lo \
coff-i860.lo \
coff-i960.lo \
coff-m68k.lo \
coff-m88k.lo \
coff-mips.lo \
@ -681,8 +673,6 @@ BFD32_BACKENDS = \
elf32-i370.lo \
elf32-i386.lo \
elfxx-x86.lo \
elf32-i860.lo \
elf32-i960.lo \
elf32-ip2k.lo \
elf32-iq2000.lo \
elf32-lm32.lo \
@ -802,7 +792,6 @@ BFD32_BACKENDS = \
xtensa-modules.lo
BFD32_BACKENDS_CFILES = \
aout-adobe.c \
aout-arm.c \
aout-cris.c \
aout-ns32k.c \
@ -811,7 +800,6 @@ BFD32_BACKENDS_CFILES = \
aout0.c \
aout32.c \
armnetbsd.c \
bout.c \
cf-i386lynx.c \
cf-sparclynx.c \
coff-apollo.c \
@ -821,8 +809,6 @@ BFD32_BACKENDS_CFILES = \
coff-h8300.c \
coff-h8500.c \
coff-i386.c \
coff-i860.c \
coff-i960.c \
coff-m68k.c \
coff-m88k.c \
coff-mips.c \
@ -878,8 +864,6 @@ BFD32_BACKENDS_CFILES = \
elf32-i370.c \
elf32-i386.c \
elfxx-x86.c \
elf32-i860.c \
elf32-i960.c \
elf32-ip2k.c \
elf32-iq2000.c \
elf32-lm32.c \
@ -1322,7 +1306,6 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aix386-core.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aix5ppc-core.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aout-adobe.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aout-arm.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aout-cris.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aout-ns32k.Plo@am__quote@
@ -1339,7 +1322,6 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bfdio.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bfdwin.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/binary.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bout.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cache.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cf-i386lynx.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cf-sparclynx.Plo@am__quote@
@ -1353,8 +1335,6 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-h8300.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-h8500.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-i386.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-i860.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-i960.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-m68k.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-m88k.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-mips.Plo@am__quote@
@ -1400,8 +1380,6 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-hppa.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-i370.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-i386.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-i860.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-i960.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-ia64.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-iamcu.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-ip2k.Plo@am__quote@
@ -1503,8 +1481,6 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-hppa.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-i370.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-i386.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-i860.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-i960.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-ia64.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-ip2k.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-iq2000.Plo@am__quote@

535
bfd/aout-adobe.c
View File

@ -1,535 +0,0 @@
/* BFD back-end for a.out.adobe binaries.
Copyright (C) 1990-2018 Free Software Foundation, Inc.
Written by Cygnus Support. Based on bout.c.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
#include "sysdep.h"
#include "bfd.h"
#include "libbfd.h"
#include "aout/adobe.h"
#include "aout/stab_gnu.h"
#include "libaout.h" /* BFD a.out internal data structures. */
/* Forward decl. */
extern const bfd_target aout_adobe_vec;
/* Swaps the information in an executable header taken from a raw byte
stream memory image, into the internal exec_header structure. */
static void
aout_adobe_swap_exec_header_in (bfd *abfd,
struct external_exec *bytes,
struct internal_exec *execp)
{
/* Now fill in fields in the execp, from the bytes in the raw data. */
execp->a_info = H_GET_32 (abfd, bytes->e_info);
execp->a_text = GET_WORD (abfd, bytes->e_text);
execp->a_data = GET_WORD (abfd, bytes->e_data);
execp->a_bss = GET_WORD (abfd, bytes->e_bss);
execp->a_syms = GET_WORD (abfd, bytes->e_syms);
execp->a_entry = GET_WORD (abfd, bytes->e_entry);
execp->a_trsize = GET_WORD (abfd, bytes->e_trsize);
execp->a_drsize = GET_WORD (abfd, bytes->e_drsize);
}
/* Swaps the information in an internal exec header structure into the
supplied buffer ready for writing to disk. */
static void
aout_adobe_swap_exec_header_out (bfd *abfd,
struct internal_exec *execp,
struct external_exec *bytes)
{
/* Now fill in fields in the raw data, from the fields in the exec
struct. */
H_PUT_32 (abfd, execp->a_info , bytes->e_info);
PUT_WORD (abfd, execp->a_text , bytes->e_text);
PUT_WORD (abfd, execp->a_data , bytes->e_data);
PUT_WORD (abfd, execp->a_bss , bytes->e_bss);
PUT_WORD (abfd, execp->a_syms , bytes->e_syms);
PUT_WORD (abfd, execp->a_entry , bytes->e_entry);
PUT_WORD (abfd, execp->a_trsize, bytes->e_trsize);
PUT_WORD (abfd, execp->a_drsize, bytes->e_drsize);
}
/* Finish up the opening of a b.out file for reading. Fill in all the
fields that are not handled by common code. */
static const bfd_target *
aout_adobe_callback (bfd *abfd)
{
struct internal_exec *execp = exec_hdr (abfd);
asection *sect;
struct external_segdesc ext[1];
char *section_name;
char try_again[30]; /* Name and number. */
char *newname;
int trynum;
flagword flags;
/* Architecture and machine type -- unknown in this format. */
bfd_set_arch_mach (abfd, bfd_arch_unknown, 0L);
/* The positions of the string table and symbol table. */
obj_str_filepos (abfd) = N_STROFF (execp);
obj_sym_filepos (abfd) = N_SYMOFF (execp);
/* Suck up the section information from the file, one section at a time. */
for (;;)
{
bfd_size_type amt = sizeof (*ext);
if (bfd_bread ( ext, amt, abfd) != amt)
{
if (bfd_get_error () != bfd_error_system_call)
bfd_set_error (bfd_error_wrong_format);
return NULL;
}
switch (ext->e_type[0])
{
case N_TEXT:
section_name = ".text";
flags = SEC_CODE | SEC_LOAD | SEC_ALLOC | SEC_HAS_CONTENTS;
break;
case N_DATA:
section_name = ".data";
flags = SEC_DATA | SEC_LOAD | SEC_ALLOC | SEC_HAS_CONTENTS;
break;
case N_BSS:
section_name = ".bss";
flags = SEC_DATA | SEC_HAS_CONTENTS;
break;
case 0:
goto no_more_sections;
default:
_bfd_error_handler
/* xgettext:c-format */
(_("%pB: unknown section type in a.out.adobe file: %x"),
abfd, ext->e_type[0]);
goto no_more_sections;
}
/* First one is called ".text" or whatever; subsequent ones are
".text1", ".text2", ... */
bfd_set_error (bfd_error_no_error);
sect = bfd_make_section_with_flags (abfd, section_name, flags);
trynum = 0;
while (!sect)
{
if (bfd_get_error () != bfd_error_no_error)
/* Some other error -- slide into the sunset. */
return NULL;
sprintf (try_again, "%s%d", section_name, ++trynum);
sect = bfd_make_section_with_flags (abfd, try_again, flags);
}
/* Fix the name, if it is a sprintf'd name. */
if (sect->name == try_again)
{
amt = strlen (sect->name);
newname = bfd_zalloc (abfd, amt);
if (newname == NULL)
return NULL;
strcpy (newname, sect->name);
sect->name = newname;
}
/* Assumed big-endian. */
sect->size = ((ext->e_size[0] << 8)
| ext->e_size[1] << 8
| ext->e_size[2]);
sect->vma = H_GET_32 (abfd, ext->e_virtbase);
sect->filepos = H_GET_32 (abfd, ext->e_filebase);
/* FIXME XXX alignment? */
/* Set relocation information for first section of each type. */
if (trynum == 0)
switch (ext->e_type[0])
{
case N_TEXT:
sect->rel_filepos = N_TRELOFF (execp);
sect->reloc_count = execp->a_trsize;
break;
case N_DATA:
sect->rel_filepos = N_DRELOFF (execp);
sect->reloc_count = execp->a_drsize;
break;
default:
break;
}
}
no_more_sections:
adata (abfd).reloc_entry_size = sizeof (struct reloc_std_external);
adata (abfd).symbol_entry_size = sizeof (struct external_nlist);
adata (abfd).page_size = 1; /* Not applicable. */
adata (abfd).segment_size = 1; /* Not applicable. */
adata (abfd).exec_bytes_size = EXEC_BYTES_SIZE;
return abfd->xvec;
}
static const bfd_target *
aout_adobe_object_p (bfd *abfd)
{
struct internal_exec anexec;
struct external_exec exec_bytes;
char *targ;
bfd_size_type amt = EXEC_BYTES_SIZE;
if (bfd_bread (& exec_bytes, amt, abfd) != amt)
{
if (bfd_get_error () != bfd_error_system_call)
bfd_set_error (bfd_error_wrong_format);
return NULL;
}
anexec.a_info = H_GET_32 (abfd, exec_bytes.e_info);
/* Normally we just compare for the magic number.
However, a bunch of Adobe tools aren't fixed up yet; they generate
files using ZMAGIC(!).
If the environment variable GNUTARGET is set to "a.out.adobe", we will
take just about any a.out file as an Adobe a.out file. FIXME! */
if (N_BADMAG (&anexec))
{
targ = getenv ("GNUTARGET");
if (targ && !strcmp (targ, aout_adobe_vec.name))
/* Just continue anyway, if specifically set to this format. */
;
else
{
bfd_set_error (bfd_error_wrong_format);
return NULL;
}
}
aout_adobe_swap_exec_header_in (abfd, &exec_bytes, &anexec);
return aout_32_some_aout_object_p (abfd, &anexec, aout_adobe_callback);
}
struct bout_data_struct
{
struct aoutdata a;
struct internal_exec e;
};
static bfd_boolean
aout_adobe_mkobject (bfd *abfd)
{
struct bout_data_struct *rawptr;
bfd_size_type amt = sizeof (struct bout_data_struct);
rawptr = bfd_zalloc (abfd, amt);
if (rawptr == NULL)
return FALSE;
abfd->tdata.bout_data = rawptr;
exec_hdr (abfd) = &rawptr->e;
adata (abfd).reloc_entry_size = sizeof (struct reloc_std_external);
adata (abfd).symbol_entry_size = sizeof (struct external_nlist);
adata (abfd).page_size = 1; /* Not applicable. */
adata (abfd).segment_size = 1; /* Not applicable. */
adata (abfd).exec_bytes_size = EXEC_BYTES_SIZE;
return TRUE;
}
static void
aout_adobe_write_section (bfd *abfd ATTRIBUTE_UNUSED,
sec_ptr sect ATTRIBUTE_UNUSED)
{
/* FIXME XXX. */
}
static bfd_boolean
aout_adobe_write_object_contents (bfd *abfd)
{
struct external_exec swapped_hdr;
static struct external_segdesc sentinel[1]; /* Initialized to zero. */
asection *sect;
bfd_size_type amt;
exec_hdr (abfd)->a_info = ZMAGIC;
/* Calculate text size as total of text sections, etc. */
exec_hdr (abfd)->a_text = 0;
exec_hdr (abfd)->a_data = 0;
exec_hdr (abfd)->a_bss = 0;
exec_hdr (abfd)->a_trsize = 0;
exec_hdr (abfd)->a_drsize = 0;
for (sect = abfd->sections; sect; sect = sect->next)
{
if (sect->flags & SEC_CODE)
{
exec_hdr (abfd)->a_text += sect->size;
exec_hdr (abfd)->a_trsize += sect->reloc_count *
sizeof (struct reloc_std_external);
}
else if (sect->flags & SEC_DATA)
{
exec_hdr (abfd)->a_data += sect->size;
exec_hdr (abfd)->a_drsize += sect->reloc_count *
sizeof (struct reloc_std_external);
}
else if (sect->flags & SEC_ALLOC && !(sect->flags & SEC_LOAD))
exec_hdr (abfd)->a_bss += sect->size;
}
exec_hdr (abfd)->a_syms = bfd_get_symcount (abfd)
* sizeof (struct external_nlist);
exec_hdr (abfd)->a_entry = bfd_get_start_address (abfd);
aout_adobe_swap_exec_header_out (abfd, exec_hdr (abfd), &swapped_hdr);
amt = EXEC_BYTES_SIZE;
if (bfd_seek (abfd, (file_ptr) 0, SEEK_SET) != 0
|| bfd_bwrite (& swapped_hdr, amt, abfd) != amt)
return FALSE;
/* Now write out the section information. Text first, data next, rest
afterward. */
for (sect = abfd->sections; sect; sect = sect->next)
if (sect->flags & SEC_CODE)
aout_adobe_write_section (abfd, sect);
for (sect = abfd->sections; sect; sect = sect->next)
if (sect->flags & SEC_DATA)
aout_adobe_write_section (abfd, sect);
for (sect = abfd->sections; sect; sect = sect->next)
if (!(sect->flags & (SEC_CODE | SEC_DATA)))
aout_adobe_write_section (abfd, sect);
/* Write final `sentinel` section header (with type of 0). */
amt = sizeof (*sentinel);
if (bfd_bwrite (sentinel, amt, abfd) != amt)
return FALSE;
/* Now write out reloc info, followed by syms and strings. */
if (bfd_get_symcount (abfd) != 0)
{
if (bfd_seek (abfd, (file_ptr) (N_SYMOFF (exec_hdr (abfd))), SEEK_SET)
!= 0)
return FALSE;
if (! aout_32_write_syms (abfd))
return FALSE;
if (bfd_seek (abfd, (file_ptr) (N_TRELOFF (exec_hdr (abfd))), SEEK_SET)
!= 0)
return FALSE;
for (sect = abfd->sections; sect; sect = sect->next)
if (sect->flags & SEC_CODE)
if (!aout_32_squirt_out_relocs (abfd, sect))
return FALSE;
if (bfd_seek (abfd, (file_ptr) (N_DRELOFF (exec_hdr (abfd))), SEEK_SET)
!= 0)
return FALSE;
for (sect = abfd->sections; sect; sect = sect->next)
if (sect->flags & SEC_DATA)
if (!aout_32_squirt_out_relocs (abfd, sect))
return FALSE;
}
return TRUE;
}
static bfd_boolean
aout_adobe_set_section_contents (bfd *abfd,
asection *section,
const void * location,
file_ptr offset,
bfd_size_type count)
{
file_ptr section_start;
sec_ptr sect;
/* Set by bfd.c handler. */
if (! abfd->output_has_begun)
{
/* Assign file offsets to sections. Text sections are first, and
are contiguous. Then data sections. Everything else at the end. */
section_start = N_TXTOFF (0);
for (sect = abfd->sections; sect; sect = sect->next)
{
if (sect->flags & SEC_CODE)
{
sect->filepos = section_start;
/* FIXME: Round to alignment. */
section_start += sect->size;
}
}
for (sect = abfd->sections; sect; sect = sect->next)
{
if (sect->flags & SEC_DATA)
{
sect->filepos = section_start;
/* FIXME: Round to alignment. */
section_start += sect->size;
}
}
for (sect = abfd->sections; sect; sect = sect->next)
{
if (sect->flags & SEC_HAS_CONTENTS &&
!(sect->flags & (SEC_CODE | SEC_DATA)))
{
sect->filepos = section_start;
/* FIXME: Round to alignment. */
section_start += sect->size;
}
}
}
/* Regardless, once we know what we're doing, we might as well get
going. */
if (bfd_seek (abfd, section->filepos + offset, SEEK_SET) != 0)
return FALSE;
if (count == 0)
return TRUE;
return bfd_bwrite (location, count, abfd) == count;
}
static bfd_boolean
aout_adobe_set_arch_mach (bfd *abfd,
enum bfd_architecture arch,
unsigned long machine)
{
if (! bfd_default_set_arch_mach (abfd, arch, machine))
return FALSE;
if (arch == bfd_arch_unknown
|| arch == bfd_arch_m68k)
return TRUE;
return FALSE;
}
static int
aout_adobe_sizeof_headers (bfd *ignore_abfd ATTRIBUTE_UNUSED,
struct bfd_link_info *info ATTRIBUTE_UNUSED)
{
return sizeof (struct internal_exec);
}
/* Build the transfer vector for Adobe A.Out files. */
#define aout_32_find_line _bfd_nosymbols_find_line
#define aout_32_get_symbol_version_string _bfd_nosymbols_get_symbol_version_string
#define aout_32_bfd_make_debug_symbol _bfd_nosymbols_bfd_make_debug_symbol
#define aout_32_bfd_reloc_type_lookup _bfd_norelocs_bfd_reloc_type_lookup
#define aout_32_bfd_reloc_name_lookup _bfd_norelocs_bfd_reloc_name_lookup
#define aout_32_close_and_cleanup aout_32_bfd_free_cached_info
#define aout_32_set_arch_mach aout_adobe_set_arch_mach
#define aout_32_set_section_contents aout_adobe_set_section_contents
#define aout_32_sizeof_headers aout_adobe_sizeof_headers
#define aout_32_bfd_get_relocated_section_contents bfd_generic_get_relocated_section_contents
#define aout_32_get_section_contents_in_window _bfd_generic_get_section_contents_in_window
#define aout_32_bfd_relax_section bfd_generic_relax_section
#define aout_32_bfd_gc_sections bfd_generic_gc_sections
#define aout_32_bfd_lookup_section_flags bfd_generic_lookup_section_flags
#define aout_32_bfd_merge_sections bfd_generic_merge_sections
#define aout_32_bfd_is_group_section bfd_generic_is_group_section
#define aout_32_bfd_discard_group bfd_generic_discard_group
#define aout_32_section_already_linked _bfd_generic_section_already_linked
#define aout_32_bfd_define_common_symbol bfd_generic_define_common_symbol
#define aout_32_bfd_define_start_stop bfd_generic_define_start_stop
#define aout_32_bfd_link_hash_table_create _bfd_generic_link_hash_table_create
#define aout_32_bfd_link_add_symbols _bfd_generic_link_add_symbols
#define aout_32_bfd_link_just_syms _bfd_generic_link_just_syms
#define aout_32_bfd_copy_link_hash_symbol_type \
_bfd_generic_copy_link_hash_symbol_type
#define aout_32_bfd_final_link _bfd_generic_final_link
#define aout_32_bfd_link_split_section _bfd_generic_link_split_section
#define aout_32_bfd_link_check_relocs _bfd_generic_link_check_relocs
#define aout_32_set_reloc _bfd_generic_set_reloc
const bfd_target aout_adobe_vec =
{
"a.out.adobe", /* Name. */
bfd_target_aout_flavour,
BFD_ENDIAN_BIG, /* Data byte order is unknown (big assumed). */
BFD_ENDIAN_BIG, /* Header byte order is big. */
(HAS_RELOC | EXEC_P | /* Object flags. */
HAS_LINENO | HAS_DEBUG |
HAS_SYMS | HAS_LOCALS | WP_TEXT ),
/* section flags */
(SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_CODE | SEC_DATA | SEC_RELOC),
'_', /* Symbol leading char. */
' ', /* AR_pad_char. */
16, /* AR_max_namelen. */
0, /* match priority. */
bfd_getb64, bfd_getb_signed_64, bfd_putb64,
bfd_getb32, bfd_getb_signed_32, bfd_putb32,
bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* Data. */
bfd_getb64, bfd_getb_signed_64, bfd_putb64,
bfd_getb32, bfd_getb_signed_32, bfd_putb32,
bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* Headers. */
{ /* bfd_check_format. */
_bfd_dummy_target,
aout_adobe_object_p,
bfd_generic_archive_p,
_bfd_dummy_target
},
{ /* bfd_set_format. */
_bfd_bool_bfd_false_error,
aout_adobe_mkobject,
_bfd_generic_mkarchive,
_bfd_bool_bfd_false_error
},
{ /* bfd_write_contents. */
_bfd_bool_bfd_false_error,
aout_adobe_write_object_contents,
_bfd_write_archive_contents,
_bfd_bool_bfd_false_error
},
BFD_JUMP_TABLE_GENERIC (aout_32),
BFD_JUMP_TABLE_COPY (_bfd_generic),
BFD_JUMP_TABLE_CORE (_bfd_nocore),
BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_bsd),
BFD_JUMP_TABLE_SYMBOLS (aout_32),
BFD_JUMP_TABLE_RELOCS (aout_32),
BFD_JUMP_TABLE_WRITE (aout_32),
BFD_JUMP_TABLE_LINK (aout_32),
BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
NULL,
NULL
};

13
bfd/aoutx.h
View File

@ -33,9 +33,9 @@ DESCRIPTION
The support is split into a basic support file @file{aoutx.h}
and other files which derive functions from the base. One
derivation file is @file{aoutf1.h} (for a.out flavour 1), and
adds to the basic a.out functions support for sun3, sun4, 386
and 29k a.out files, to create a target jump vector for a
specific target.
adds to the basic a.out functions support for sun3, sun4, and
386 a.out files, to create a target jump vector for a specific
target.
This information is further split out into more specific files
for each machine, including @file{sunos.c} for sun3 and sun4,
@ -136,10 +136,9 @@ DESCRIPTION
The file @file{aoutx.h} provides for both the @emph{standard}
and @emph{extended} forms of a.out relocation records.
The standard records contain only an
address, a symbol index, and a type field. The extended records
(used on 29ks and sparcs) also have a full integer for an
addend. */
The standard records contain only an address, a symbol index,
and a type field. The extended records also have a full
integer for an addend. */
#ifndef CTOR_TABLE_RELOC_HOWTO
#define CTOR_TABLE_RELOC_IDX 2

16
bfd/archive.c
View File

@ -847,7 +847,6 @@ bfd_generic_archive_p (bfd *abfd)
bfd_is_thin_archive (abfd) = (strncmp (armag, ARMAGT, SARMAG) == 0);
if (strncmp (armag, ARMAG, SARMAG) != 0
&& strncmp (armag, ARMAGB, SARMAG) != 0
&& ! bfd_is_thin_archive (abfd))
{
bfd_set_error (bfd_error_wrong_format);
@ -1042,21 +1041,6 @@ do_slurp_coff_armap (bfd *abfd)
nsymz = bfd_getb32 (int_buf);
stringsize = parsed_size - (4 * nsymz) - 4;
/* ... except that some archive formats are broken, and it may be our
fault - the i960 little endian coff sometimes has big and sometimes
little, because our tools changed. Here's a horrible hack to clean
up the crap. */
if (stringsize > 0xfffff
&& bfd_get_arch (abfd) == bfd_arch_i960
&& bfd_get_flavour (abfd) == bfd_target_coff_flavour)
{
/* This looks dangerous, let's do it the other way around. */
nsymz = bfd_getl32 (int_buf);
stringsize = parsed_size - (4 * nsymz) - 4;
swap = bfd_getl32;
}
/* The coff armap must be read sequentially. So we construct a
bsd-style one in core all at once, for simplicity. */

25
bfd/archures.c
View File

@ -63,8 +63,7 @@ DESCRIPTION
Another field indicates which processor within
the family is in use. The machine gives a number which
distinguishes different versions of the architecture,
containing, for example, 2 and 3 for Intel i960 KA and i960 KB,
and 68020 and 68030 for Motorola 68020 and 68030.
containing, for example, 68020 for Motorola 68020.
.enum bfd_architecture
.{
@ -103,23 +102,6 @@ DESCRIPTION
.#define bfd_mach_mcf_isa_c_nodiv_mac 30
.#define bfd_mach_mcf_isa_c_nodiv_emac 31
. bfd_arch_vax, {* DEC Vax. *}
. bfd_arch_i960, {* Intel 960. *}
. {* The order of the following is important.
. lower number indicates a machine type that
. only accepts a subset of the instructions
. available to machines with higher numbers.
. The exception is the "ca", which is
. incompatible with all other machines except
. "core". *}
.
.#define bfd_mach_i960_core 1
.#define bfd_mach_i960_ka_sa 2
.#define bfd_mach_i960_kb_sb 3
.#define bfd_mach_i960_mc 4
.#define bfd_mach_i960_xa 5
.#define bfd_mach_i960_ca 6
.#define bfd_mach_i960_jx 7
.#define bfd_mach_i960_hx 8
.
. bfd_arch_or1k, {* OpenRISC 1000. *}
.#define bfd_mach_or1k 1
@ -237,7 +219,6 @@ DESCRIPTION
.#define bfd_mach_i386_iamcu_intel_syntax (bfd_mach_i386_iamcu | bfd_mach_i386_intel_syntax)
. bfd_arch_we32k, {* AT&T WE32xxx. *}
. bfd_arch_tahoe, {* CCI/Harris Tahoe. *}
. bfd_arch_i860, {* Intel 860. *}
. bfd_arch_i370, {* IBM 360/370 Mainframes. *}
. bfd_arch_romp, {* IBM ROMP PC/RT. *}
. bfd_arch_convex, {* Convex. *}
@ -603,8 +584,6 @@ extern const bfd_arch_info_type bfd_hppa_arch;
extern const bfd_arch_info_type bfd_i370_arch;
extern const bfd_arch_info_type bfd_i386_arch;
extern const bfd_arch_info_type bfd_iamcu_arch;
extern const bfd_arch_info_type bfd_i860_arch;
extern const bfd_arch_info_type bfd_i960_arch;
extern const bfd_arch_info_type bfd_ia64_arch;
extern const bfd_arch_info_type bfd_ip2k_arch;
extern const bfd_arch_info_type bfd_iq2000_arch;
@ -698,8 +677,6 @@ static const bfd_arch_info_type * const bfd_archures_list[] =
&bfd_i370_arch,
&bfd_i386_arch,
&bfd_iamcu_arch,
&bfd_i860_arch,
&bfd_i960_arch,
&bfd_ia64_arch,
&bfd_ip2k_arch,
&bfd_iq2000_arch,

70
bfd/bfd-in2.h
View File

@ -1979,23 +1979,6 @@ enum bfd_architecture
#define bfd_mach_mcf_isa_c_nodiv_mac 30
#define bfd_mach_mcf_isa_c_nodiv_emac 31
bfd_arch_vax, /* DEC Vax. */
bfd_arch_i960, /* Intel 960. */
/* The order of the following is important.
lower number indicates a machine type that
only accepts a subset of the instructions
available to machines with higher numbers.
The exception is the "ca", which is
incompatible with all other machines except
"core". */
#define bfd_mach_i960_core 1
#define bfd_mach_i960_ka_sa 2
#define bfd_mach_i960_kb_sb 3
#define bfd_mach_i960_mc 4
#define bfd_mach_i960_xa 5
#define bfd_mach_i960_ca 6
#define bfd_mach_i960_jx 7
#define bfd_mach_i960_hx 8
bfd_arch_or1k, /* OpenRISC 1000. */
#define bfd_mach_or1k 1
@ -2113,7 +2096,6 @@ enum bfd_architecture
#define bfd_mach_i386_iamcu_intel_syntax (bfd_mach_i386_iamcu | bfd_mach_i386_intel_syntax)
bfd_arch_we32k, /* AT&T WE32xxx. */
bfd_arch_tahoe, /* CCI/Harris Tahoe. */
bfd_arch_i860, /* Intel 860. */
bfd_arch_i370, /* IBM 360/370 Mainframes. */
bfd_arch_romp, /* IBM ROMP PC/RT. */
bfd_arch_convex, /* Convex. */
@ -2506,10 +2488,9 @@ typedef enum bfd_reloc_status
/* The symbol to relocate against was undefined. */
bfd_reloc_undefined,
/* The relocation was performed, but may not be ok - presently
generated only when linking i960 coff files with i960 b.out
symbols. If this type is returned, the error_message argument
to bfd_perform_relocation will be set. */
/* The relocation was performed, but may not be ok. If this type is
returned, the error_message argument to bfd_perform_relocation
will be set. */
bfd_reloc_dangerous
}
bfd_reloc_status_type;
@ -2589,8 +2570,7 @@ struct reloc_howto_struct
/* If this field is non null, then the supplied function is
called rather than the normal function. This allows really
strange relocation methods to be accommodated (e.g., i960 callj
instructions). */
strange relocation methods to be accommodated. */
bfd_reloc_status_type (*special_function)
(bfd *, arelent *, struct bfd_symbol *, void *, asection *,
bfd *, char **);
@ -2715,9 +2695,7 @@ enum bfd_reloc_code_real {
/* PC-relative relocations. Sometimes these are relative to the address
of the relocation itself; sometimes they are relative to the start of
the section containing the relocation. It depends on the specific target.
The 24-bit relocation is used in some Intel 960 configurations. */
the section containing the relocation. It depends on the specific target. */
BFD_RELOC_64_PCREL,
BFD_RELOC_32_PCREL,
BFD_RELOC_24_PCREL,
@ -2809,9 +2787,6 @@ decided relatively late. */
BFD_RELOC_GPREL16,
BFD_RELOC_GPREL32,
/* Reloc types used for i960/b.out. */
BFD_RELOC_I960_CALLJ,
/* SPARC ELF relocations. There is probably some overlap with other
relocation types already defined. */
BFD_RELOC_NONE,
@ -5435,40 +5410,6 @@ a matching LO8XG part. */
BFD_RELOC_CRIS_DTPMOD,
BFD_RELOC_CRIS_32_IE,
/* Intel i860 Relocations. */
BFD_RELOC_860_COPY,
BFD_RELOC_860_GLOB_DAT,
BFD_RELOC_860_JUMP_SLOT,
BFD_RELOC_860_RELATIVE,
BFD_RELOC_860_PC26,
BFD_RELOC_860_PLT26,
BFD_RELOC_860_PC16,
BFD_RELOC_860_LOW0,
BFD_RELOC_860_SPLIT0,
BFD_RELOC_860_LOW1,
BFD_RELOC_860_SPLIT1,
BFD_RELOC_860_LOW2,
BFD_RELOC_860_SPLIT2,
BFD_RELOC_860_LOW3,
BFD_RELOC_860_LOGOT0,
BFD_RELOC_860_SPGOT0,
BFD_RELOC_860_LOGOT1,
BFD_RELOC_860_SPGOT1,
BFD_RELOC_860_LOGOTOFF0,
BFD_RELOC_860_SPGOTOFF0,
BFD_RELOC_860_LOGOTOFF1,
BFD_RELOC_860_SPGOTOFF1,
BFD_RELOC_860_LOGOTOFF2,
BFD_RELOC_860_LOGOTOFF3,
BFD_RELOC_860_LOPC,
BFD_RELOC_860_HIGHADJ,
BFD_RELOC_860_HAGOT,
BFD_RELOC_860_HAGOTOFF,
BFD_RELOC_860_HAPC,
BFD_RELOC_860_HIGH,
BFD_RELOC_860_HIGOT,
BFD_RELOC_860_HIGOTOFF,
/* OpenRISC 1000 Relocations. */
BFD_RELOC_OR1K_REL_26,
BFD_RELOC_OR1K_GOTPC_HI16,
@ -7076,7 +7017,6 @@ struct bfd
struct tekhex_data_struct *tekhex_data;
struct elf_obj_tdata *elf_obj_data;
struct nlm_obj_tdata *nlm_obj_data;
struct bout_data_struct *bout_data;
struct mmo_data_struct *mmo_data;
struct sun_core_struct *sun_core_data;
struct sco5_core_struct *sco5_core_data;

1
bfd/bfd.c
View File

@ -318,7 +318,6 @@ CODE_FRAGMENT
. struct tekhex_data_struct *tekhex_data;
. struct elf_obj_tdata *elf_obj_data;
. struct nlm_obj_tdata *nlm_obj_data;
. struct bout_data_struct *bout_data;
. struct mmo_data_struct *mmo_data;
. struct sun_core_struct *sun_core_data;
. struct sco5_core_struct *sco5_core_data;

1508
bfd/bout.c
View File

File diff suppressed because it is too large Load Diff

730
bfd/coff-i860.c
View File

@ -1,730 +0,0 @@
/* BFD back-end for Intel i860 COFF files.
Copyright (C) 1990-2018 Free Software Foundation, Inc.
Created mostly by substituting "860" for "386" in coff-i386.c
Harry Dolan <dolan@ssd.intel.com>, October 1995
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "sysdep.h"
#include "bfd.h"
#include "libbfd.h"
#include "coff/i860.h"
#include "coff/internal.h"
#ifndef bfd_pe_print_pdata
#define bfd_pe_print_pdata NULL
#endif
#include "libcoff.h"
#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER (2)
/* The page size is a guess based on ELF. */
#define COFF_PAGE_SIZE 0x1000
/* For some reason when using i860 COFF the value stored in the .text
section for a reference to a common symbol is the value itself plus
any desired offset. Ian Taylor, Cygnus Support. */
/* If we are producing relocatable output, we need to do some
adjustments to the object file that are not done by the
bfd_perform_relocation function. This function is called by every
reloc type to make any required adjustments. */
static bfd_reloc_status_type
coff_i860_reloc (bfd *abfd,
arelent *reloc_entry,
asymbol *symbol,
void *data,
asection *input_section ATTRIBUTE_UNUSED,
bfd *output_bfd,
char **error_message ATTRIBUTE_UNUSED)
{
symvalue diff;
if (output_bfd == (bfd *) NULL)
return bfd_reloc_continue;
if (bfd_is_com_section (symbol->section))
{
/* We are relocating a common symbol. The current value in the
object file is ORIG + OFFSET, where ORIG is the value of the
common symbol as seen by the object file when it was compiled
(this may be zero if the symbol was undefined) and OFFSET is
the offset into the common symbol (normally zero, but may be
non-zero when referring to a field in a common structure).
ORIG is the negative of reloc_entry->addend, which is set by
the CALC_ADDEND macro below. We want to replace the value in
the object file with NEW + OFFSET, where NEW is the value of
the common symbol which we are going to put in the final
object file. NEW is symbol->value. */
diff = symbol->value + reloc_entry->addend;
}
else
{
/* For some reason bfd_perform_relocation always effectively
ignores the addend for a COFF target when producing
relocatable output. This seems to be always wrong for 860
COFF, so we handle the addend here instead. */
diff = reloc_entry->addend;
}
#define DOIT(x) \
x = ((x & ~howto->dst_mask) | (((x & howto->src_mask) + diff) & howto->dst_mask))
if (diff != 0)
{
reloc_howto_type *howto = reloc_entry->howto;
unsigned char *addr = (unsigned char *) data + reloc_entry->address;
if (! bfd_reloc_offset_in_range (howto, abfd, input_section,
reloc_entry->address
* bfd_octets_per_byte (abfd)))
return bfd_reloc_outofrange;
switch (howto->size)
{
case 0:
{
char x = bfd_get_8 (abfd, addr);
DOIT (x);
bfd_put_8 (abfd, x, addr);
}
break;
case 1:
{
short x = bfd_get_16 (abfd, addr);
DOIT (x);
bfd_put_16 (abfd, (bfd_vma) x, addr);
}
break;
case 2:
{
long x = bfd_get_32 (abfd, addr);
DOIT (x);
bfd_put_32 (abfd, (bfd_vma) x, addr);
}
break;
default:
abort ();
}
}
/* Now let bfd_perform_relocation finish everything up. */
return bfd_reloc_continue;
}
/* This is just a temporary measure until we teach bfd to generate
these relocations. */
static bfd_reloc_status_type
coff_i860_reloc_nyi (bfd *abfd,
arelent *reloc_entry,
asymbol *symbol ATTRIBUTE_UNUSED,
void *data ATTRIBUTE_UNUSED,
asection *input_section ATTRIBUTE_UNUSED,
bfd *output_bfd ATTRIBUTE_UNUSED,
char **error_message ATTRIBUTE_UNUSED)
{
reloc_howto_type *howto = reloc_entry->howto;
_bfd_error_handler (_("%pB: %s unsupported"), abfd, howto->name);
return bfd_reloc_notsupported;
}
#ifndef PCRELOFFSET
#define PCRELOFFSET FALSE
#endif
static reloc_howto_type howto_table[] =
{
EMPTY_HOWTO (0),
EMPTY_HOWTO (1),
EMPTY_HOWTO (2),
EMPTY_HOWTO (3),
EMPTY_HOWTO (4),
EMPTY_HOWTO (5),
HOWTO (R_DIR32, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
coff_i860_reloc, /* special_function */
"dir32", /* name */
TRUE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
TRUE), /* pcrel_offset */
/* {7}, */
HOWTO (R_IMAGEBASE, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
coff_i860_reloc, /* special_function */
"rva32", /* name */
TRUE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
FALSE), /* pcrel_offset */
EMPTY_HOWTO (010),
EMPTY_HOWTO (011),
EMPTY_HOWTO (012),
EMPTY_HOWTO (013),
EMPTY_HOWTO (014),
EMPTY_HOWTO (015),
EMPTY_HOWTO (016),
HOWTO (R_RELBYTE, /* type */
0, /* rightshift */
0, /* size (0 = byte, 1 = short, 2 = long) */
8, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
coff_i860_reloc, /* special_function */
"8", /* name */
TRUE, /* partial_inplace */
0x000000ff, /* src_mask */
0x000000ff, /* dst_mask */
PCRELOFFSET), /* pcrel_offset */
HOWTO (R_RELWORD, /* type */
0, /* rightshift */
1, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
coff_i860_reloc, /* special_function */
"16", /* name */
TRUE, /* partial_inplace */
0x0000ffff, /* src_mask */
0x0000ffff, /* dst_mask */
PCRELOFFSET), /* pcrel_offset */
HOWTO (R_RELLONG, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
coff_i860_reloc, /* special_function */
"32", /* name */
TRUE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
PCRELOFFSET), /* pcrel_offset */
HOWTO (R_PCRBYTE, /* type */
0, /* rightshift */
0, /* size (0 = byte, 1 = short, 2 = long) */
8, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
coff_i860_reloc, /* special_function */
"DISP8", /* name */
TRUE, /* partial_inplace */
0x000000ff, /* src_mask */
0x000000ff, /* dst_mask */
PCRELOFFSET), /* pcrel_offset */
HOWTO (R_PCRWORD, /* type */
0, /* rightshift */
1, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
coff_i860_reloc, /* special_function */
"DISP16", /* name */
TRUE, /* partial_inplace */
0x0000ffff, /* src_mask */
0x0000ffff, /* dst_mask */
PCRELOFFSET), /* pcrel_offset */
HOWTO (R_PCRLONG, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
coff_i860_reloc, /* special_function */
"DISP32", /* name */
TRUE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
PCRELOFFSET), /* pcrel_offset */
EMPTY_HOWTO (0x15),
EMPTY_HOWTO (0x16),
EMPTY_HOWTO (0x17),
EMPTY_HOWTO (0x18),
EMPTY_HOWTO (0x19),
EMPTY_HOWTO (0x1a),
EMPTY_HOWTO (0x1b),
HOWTO (COFF860_R_PAIR, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
coff_i860_reloc_nyi, /* special_function */
"PAIR", /* name */
FALSE, /* partial_inplace */
0xffff, /* src_mask */
0xffff, /* dst_mask */
FALSE), /* pcrel_offset */
EMPTY_HOWTO (0x1d),
HOWTO (COFF860_R_HIGH, /* type */
16, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
coff_i860_reloc, /* special_function */
"HIGH", /* name */
FALSE, /* partial_inplace */
0xffff, /* src_mask */
0xffff, /* dst_mask */
FALSE), /* pcrel_offset */
HOWTO (COFF860_R_LOW0, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
coff_i860_reloc, /* special_function */
"LOW0", /* name */
FALSE, /* partial_inplace */
0xffff, /* src_mask */
0xffff, /* dst_mask */
FALSE), /* pcrel_offset */
HOWTO (COFF860_R_LOW1, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
coff_i860_reloc, /* special_function */
"LOW1", /* name */
FALSE, /* partial_inplace */
0xfffe, /* src_mask */
0xfffe, /* dst_mask */
FALSE), /* pcrel_offset */
HOWTO (COFF860_R_LOW2, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
coff_i860_reloc, /* special_function */
"LOW2", /* name */
FALSE, /* partial_inplace */
0xfffc, /* src_mask */
0xfffc, /* dst_mask */
FALSE), /* pcrel_offset */
HOWTO (COFF860_R_LOW3, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
coff_i860_reloc, /* special_function */
"LOW3", /* name */
FALSE, /* partial_inplace */
0xfff8, /* src_mask */
0xfff8, /* dst_mask */
FALSE), /* pcrel_offset */
HOWTO (COFF860_R_LOW4, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
coff_i860_reloc, /* special_function */
"LOW4", /* name */
FALSE, /* partial_inplace */
0xfff0, /* src_mask */
0xfff0, /* dst_mask */
FALSE), /* pcrel_offset */
HOWTO (COFF860_R_SPLIT0, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
coff_i860_reloc_nyi, /* special_function */
"SPLIT0", /* name */
FALSE, /* partial_inplace */
0x1f07ff, /* src_mask */
0x1f07ff, /* dst_mask */
FALSE), /* pcrel_offset */
HOWTO (COFF860_R_SPLIT1, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
coff_i860_reloc_nyi, /* special_function */
"SPLIT1", /* name */
FALSE, /* partial_inplace */
0x1f07fe, /* src_mask */
0x1f07fe, /* dst_mask */
FALSE), /* pcrel_offset */
HOWTO (COFF860_R_SPLIT2, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
coff_i860_reloc_nyi, /* special_function */
"SPLIT2", /* name */
FALSE, /* partial_inplace */
0x1f07fc, /* src_mask */
0x1f07fc, /* dst_mask */
FALSE), /* pcrel_offset */
HOWTO (COFF860_R_HIGHADJ, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
coff_i860_reloc_nyi, /* special_function */
"HIGHADJ", /* name */
FALSE, /* partial_inplace */
0xffff, /* src_mask */
0xffff, /* dst_mask */
FALSE), /* pcrel_offset */
HOWTO (COFF860_R_BRADDR, /* type */
2, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
26, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
coff_i860_reloc_nyi, /* special_function */
"BRADDR", /* name */
FALSE, /* partial_inplace */
0x3ffffff, /* src_mask */
0x3ffffff, /* dst_mask */
TRUE) /* pcrel_offset */
};
/* Turn a howto into a reloc number. */
#define SELECT_RELOC(x,howto) { x.r_type = howto->type; }
#define BADMAG(x) I860BADMAG(x)
#define I860 1 /* Customize coffcode.h */
#define RTYPE2HOWTO(cache_ptr, dst) \
((cache_ptr)->howto = \
((dst)->r_type < sizeof (howto_table) / sizeof (howto_table[0]) \
? howto_table + (dst)->r_type \
: NULL))
/* For 860 COFF a STYP_NOLOAD | STYP_BSS section is part of a shared
library. On some other COFF targets STYP_BSS is normally
STYP_NOLOAD. */
#define BSS_NOLOAD_IS_SHARED_LIBRARY
/* Compute the addend of a reloc. If the reloc is to a common symbol,
the object file contains the value of the common symbol. By the
time this is called, the linker may be using a different symbol
from a different object file with a different value. Therefore, we
hack wildly to locate the original symbol from this file so that we
can make the correct adjustment. This macro sets coffsym to the
symbol from the original file, and uses it to set the addend value
correctly. If this is not a common symbol, the usual addend
calculation is done, except that an additional tweak is needed for
PC relative relocs.
FIXME: This macro refers to symbols and asect; these are from the
calling function, not the macro arguments. */
/* PR 17512: file: 0a38fb7c
Set an addend value, even if it is not going to be used. A tool
like coffdump might be used to print out the contents of the reloc. */
#define CALC_ADDEND(abfd, ptr, reloc, cache_ptr) (cache_ptr)->addend = 0
/* We use the special COFF backend linker. */
#define coff_relocate_section _bfd_coff_generic_relocate_section
static reloc_howto_type *
coff_i860_rtype_to_howto (bfd *abfd ATTRIBUTE_UNUSED,
asection *sec,
struct internal_reloc *rel,
struct coff_link_hash_entry *h,
struct internal_syment *sym,
bfd_vma *addendp)
{
reloc_howto_type *howto;
if (rel->r_type > sizeof (howto_table) / sizeof (howto_table[0]))
{
bfd_set_error (bfd_error_bad_value);
return NULL;
}
howto = howto_table + rel->r_type;
if (howto->pc_relative)
*addendp += sec->vma;
if (sym != NULL && sym->n_scnum == 0 && sym->n_value != 0)
{
/* This is a common symbol. The section contents include the
size (sym->n_value) as an addend. The relocate_section
function will be adding in the final value of the symbol. We
need to subtract out the current size in order to get the
correct result. */
BFD_ASSERT (h != NULL);
/* I think we *do* want to bypass this. If we don't, I have seen some data
parameters get the wrong relocation address. If I link two versions
with and without this section bypassed and then do a binary comparison,
the addresses which are different can be looked up in the map. The
case in which this section has been bypassed has addresses which correspond
to values I can find in the map. */
*addendp -= sym->n_value;
}
/* If the output symbol is common (in which case this must be a
relocatable link), we need to add in the final size of the
common symbol. */
if (h != NULL && h->root.type == bfd_link_hash_common)
*addendp += h->root.u.c.size;
return howto;
}
static reloc_howto_type *
coff_i860_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
bfd_reloc_code_real_type code)
{
switch (code)
{
case BFD_RELOC_32:
return howto_table + R_DIR32;
case BFD_RELOC_860_PC26:
return howto_table + COFF860_R_BRADDR;
case BFD_RELOC_860_PC16:
/* ??? How to handle PC16 for COFF? SPLIT0 is close for now. */
return howto_table + COFF860_R_SPLIT0;
case BFD_RELOC_860_LOW0:
return howto_table + COFF860_R_LOW0;
case BFD_RELOC_860_SPLIT0:
return howto_table + COFF860_R_SPLIT0;
case BFD_RELOC_860_LOW1:
return howto_table + COFF860_R_LOW1;
case BFD_RELOC_860_SPLIT1:
return howto_table + COFF860_R_SPLIT1;
case BFD_RELOC_860_LOW2:
return howto_table + COFF860_R_LOW2;
case BFD_RELOC_860_SPLIT2:
return howto_table + COFF860_R_SPLIT2;
case BFD_RELOC_860_LOW3:
return howto_table + COFF860_R_LOW3;
case BFD_RELOC_860_HIGHADJ:
return howto_table + COFF860_R_HIGHADJ;
case BFD_RELOC_860_HIGH:
return howto_table + COFF860_R_HIGH;
default:
BFD_FAIL ();
return 0;
}
}
static reloc_howto_type *
coff_i860_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
const char *r_name)
{
unsigned int i;
for (i = 0; i < sizeof (howto_table) / sizeof (howto_table[0]); i++)
if (howto_table[i].name != NULL
&& strcasecmp (howto_table[i].name, r_name) == 0)
return &howto_table[i];
return NULL;
}
/* This is called from coff_slurp_reloc_table for each relocation
entry. This special handling is due to the `PAIR' relocation
which has a different meaning for the `r_symndx' field. */
static void
i860_reloc_processing (arelent *cache_ptr, struct internal_reloc *dst,
asymbol **symbols, bfd *abfd, asection *asect)
{
if (dst->r_type == COFF860_R_PAIR)
{
/* Handle the PAIR relocation specially. */
cache_ptr->howto = howto_table + dst->r_type;
cache_ptr->address = dst->r_vaddr;
cache_ptr->addend = dst->r_symndx;
cache_ptr->sym_ptr_ptr= bfd_abs_section_ptr->symbol_ptr_ptr;
}
else
{
/* For every other relocation, do exactly what coff_slurp_reloc_table
would do (which this code is taken directly from). */
asymbol *ptr = NULL;
cache_ptr->address = dst->r_vaddr;
if (dst->r_symndx != -1)
{
if (dst->r_symndx < 0 || dst->r_symndx >= obj_conv_table_size (abfd))
{
_bfd_error_handler
/* xgettext: c-format */
(_("%pB: warning: illegal symbol index %ld in relocs"),
abfd, dst->r_symndx);
cache_ptr->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr;
ptr = NULL;
}
else
{
cache_ptr->sym_ptr_ptr = (symbols
+ obj_convert (abfd)[dst->r_symndx]);
ptr = *(cache_ptr->sym_ptr_ptr);
}
}
else
{
cache_ptr->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr;
ptr = NULL;
}
/* The symbols definitions that we have read in have been
relocated as if their sections started at 0. But the offsets
refering to the symbols in the raw data have not been
modified, so we have to have a negative addend to compensate.
Note that symbols which used to be common must be left alone. */
/* Calculate any reloc addend by looking at the symbol. */
CALC_ADDEND (abfd, ptr, (*dst), cache_ptr);
(void) ptr;
cache_ptr->address -= asect->vma;
/* Fill in the cache_ptr->howto field from dst->r_type. */
RTYPE2HOWTO (cache_ptr, dst);
}
}
#define coff_rtype_to_howto coff_i860_rtype_to_howto
#define coff_bfd_reloc_type_lookup coff_i860_reloc_type_lookup
#define coff_bfd_reloc_name_lookup coff_i860_reloc_name_lookup
#define RELOC_PROCESSING(relent, reloc, symbols, abfd, section) \
i860_reloc_processing (relent, reloc, symbols, abfd, section)
#include "coffcode.h"
static const bfd_target *
i3coff_object_p(bfd *a)
{
return coff_object_p (a);
}
const bfd_target
#ifdef TARGET_SYM
TARGET_SYM =
#else
i860_coff_vec =
#endif
{
#ifdef TARGET_NAME
TARGET_NAME,
#else
"coff-i860", /* name */
#endif
bfd_target_coff_flavour,
BFD_ENDIAN_LITTLE, /* data byte order is little */
BFD_ENDIAN_LITTLE, /* header byte order is little */
(HAS_RELOC | EXEC_P /* object flags */
| HAS_LINENO | HAS_DEBUG
| HAS_SYMS | HAS_LOCALS | WP_TEXT | D_PAGED),
(SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC), /* section flags */
'_', /* leading underscore */
'/', /* ar_pad_char */
15, /* ar_max_namelen */
0, /* match priority. */
bfd_getl64, bfd_getl_signed_64, bfd_putl64,
bfd_getl32, bfd_getl_signed_32, bfd_putl32,
bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */
bfd_getl64, bfd_getl_signed_64, bfd_putl64,
bfd_getl32, bfd_getl_signed_32, bfd_putl32,
bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* hdrs */
/* Note that we allow an object file to be treated as a core file as well. */
{ /* bfd_check_format */
_bfd_dummy_target,
i3coff_object_p,
bfd_generic_archive_p,
i3coff_object_p
},
{ /* bfd_set_format */
_bfd_bool_bfd_false_error,
coff_mkobject,
_bfd_generic_mkarchive,
_bfd_bool_bfd_false_error
},
{ /* bfd_write_contents */
_bfd_bool_bfd_false_error,
coff_write_object_contents,
_bfd_write_archive_contents,
_bfd_bool_bfd_false_error
},
BFD_JUMP_TABLE_GENERIC (coff),
BFD_JUMP_TABLE_COPY (coff),
BFD_JUMP_TABLE_CORE (_bfd_nocore),
BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
BFD_JUMP_TABLE_SYMBOLS (coff),
BFD_JUMP_TABLE_RELOCS (coff),
BFD_JUMP_TABLE_WRITE (coff),
BFD_JUMP_TABLE_LINK (coff),
BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
NULL,
COFF_SWAP_TABLE
};

666
bfd/coff-i960.c
View File

@ -1,666 +0,0 @@
/* BFD back-end for Intel 960 COFF files.
Copyright (C) 1990-2018 Free Software Foundation, Inc.
Written by Cygnus Support.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#define I960 1
#define BADMAG(x) I960BADMAG(x)
#include "sysdep.h"
#include "bfd.h"
#include "libbfd.h"
#include "coff/i960.h"
#include "coff/internal.h"
#ifndef bfd_pe_print_pdata
#define bfd_pe_print_pdata NULL
#endif
#include "libcoff.h" /* To allow easier abstraction-breaking. */
#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER (3)
#define COFF_ALIGN_IN_SECTION_HEADER 1
#define GET_SCNHDR_ALIGN H_GET_32
#define PUT_SCNHDR_ALIGN H_PUT_32
/* The i960 does not support an MMU, so COFF_PAGE_SIZE can be
arbitrarily small. */
#define COFF_PAGE_SIZE 1
#define COFF_LONG_FILENAMES
/* This set of local label names is taken from gas. */
static bfd_boolean
coff_i960_is_local_label_name (bfd *abfd ATTRIBUTE_UNUSED, const char *name)
{
return (name[0] == 'L'
|| (name[0] == '.'
&& (name[1] == 'C'
|| name[1] == 'I'
|| name[1] == '.')));
}
/* This is just like the usual CALC_ADDEND, but it includes the
section VMA for PC relative relocs. */
#ifndef CALC_ADDEND
#define CALC_ADDEND(abfd, ptr, reloc, cache_ptr) \
{ \
coff_symbol_type *coffsym = (coff_symbol_type *) NULL; \
if (ptr && bfd_asymbol_bfd (ptr) != abfd) \
coffsym = (obj_symbols (abfd) \
+ (cache_ptr->sym_ptr_ptr - symbols)); \
else if (ptr) \
coffsym = coff_symbol_from (ptr); \
if (coffsym != (coff_symbol_type *) NULL \
&& coffsym->native->u.syment.n_scnum == 0) \
cache_ptr->addend = 0; \
else if (ptr && bfd_asymbol_bfd (ptr) == abfd \
&& ptr->section != (asection *) NULL) \
cache_ptr->addend = - (ptr->section->vma + ptr->value); \
else \
cache_ptr->addend = 0; \
if (ptr && (reloc.r_type == 25 || reloc.r_type == 27)) \
cache_ptr->addend += asect->vma; \
}
#endif
#define CALLS 0x66003800 /* Template for 'calls' instruction */
#define BAL 0x0b000000 /* Template for 'bal' instruction */
#define BAL_MASK 0x00ffffff
static bfd_reloc_status_type
optcall_callback (bfd *abfd,
arelent *reloc_entry,
asymbol *symbol_in,
void * data,
asection *input_section,
bfd *ignore_bfd ATTRIBUTE_UNUSED,
char **error_message)
{
/* This item has already been relocated correctly, but we may be
* able to patch in yet better code - done by digging out the
* correct info on this symbol */
bfd_reloc_status_type result;
coff_symbol_type *cs = coffsymbol(symbol_in);
/* Don't do anything with symbols which aren't tied up yet,
except move the reloc. */
if (bfd_is_und_section (cs->symbol.section)) {
reloc_entry->address += input_section->output_offset;
return bfd_reloc_ok;
}
/* So the target symbol has to be of coff type, and the symbol
has to have the correct native information within it */
if ((bfd_asymbol_flavour(&cs->symbol) != bfd_target_coff_flavour)
|| (cs->native == (combined_entry_type *)NULL))
{
/* This is interesting, consider the case where we're outputting coff
from a mix n match input, linking from coff to a symbol defined in a
bout file will cause this match to be true. Should I complain? This
will only work if the bout symbol is non leaf. */
*error_message =
(char *) _("uncertain calling convention for non-COFF symbol");
result = bfd_reloc_dangerous;
}
else
{
switch (cs->native->u.syment.n_sclass)
{
case C_LEAFSTAT:
case C_LEAFEXT:
/* This is a call to a leaf procedure, replace instruction with a bal
to the correct location. */
{
union internal_auxent *aux = &((cs->native+2)->u.auxent);
int word = bfd_get_32 (abfd, (bfd_byte *)data + reloc_entry->address);
int olf = (aux->x_bal.x_balntry - cs->native->u.syment.n_value);
BFD_ASSERT(cs->native->u.syment.n_numaux==2);
/* We replace the original call instruction with a bal to
the bal entry point - the offset of which is described in
the 2nd auxent of the original symbol. We keep the native
sym and auxents untouched, so the delta between the two
is the offset of the bal entry point. */
word = ((word + olf) & BAL_MASK) | BAL;
bfd_put_32 (abfd, (bfd_vma) word,
(bfd_byte *) data + reloc_entry->address);
}
result = bfd_reloc_ok;
break;
case C_SCALL:
/* This is a call to a system call, replace with a calls to # */
BFD_ASSERT(0);
result = bfd_reloc_ok;
break;
default:
result = bfd_reloc_ok;
break;
}
}
return result;
}
/* i960 COFF is used by VxWorks 5.1. However, VxWorks 5.1 does not
appear to correctly handle a reloc against a symbol defined in the
same object file. It appears to simply discard such relocs, rather
than adding their values into the object file. We handle this here
by converting all relocs against defined symbols into relocs
against the section symbol, when generating a relocatable output
file.
Note that this function is only called if we are not using the COFF
specific backend linker. It only does something when doing a
relocatable link, which will almost certainly fail when not
generating COFF i960 output, so this function is actually no longer
useful. It was used before this target was converted to use the
COFF specific backend linker. */
static bfd_reloc_status_type
coff_i960_relocate (bfd *abfd,
arelent *reloc_entry,
asymbol *symbol,
void * data ATTRIBUTE_UNUSED,
asection *input_section ATTRIBUTE_UNUSED,
bfd *output_bfd,
char **error_message ATTRIBUTE_UNUSED)
{
asection *osec;
if (output_bfd == NULL)
{
/* Not generating relocatable output file. */
return bfd_reloc_continue;
}
if (bfd_is_und_section (bfd_get_section (symbol)))
{
/* Symbol is not defined, so no need to worry about it. */
return bfd_reloc_continue;
}
if (bfd_is_com_section (bfd_get_section (symbol)))
{
/* I don't really know what the right action is for a common
symbol. */
return bfd_reloc_continue;
}
/* Convert the reloc to use the section symbol. FIXME: This method
is ridiculous. */
osec = bfd_get_section (symbol)->output_section;
if (coff_section_data (output_bfd, osec) != NULL
&& coff_section_data (output_bfd, osec)->tdata != NULL)
reloc_entry->sym_ptr_ptr =
(asymbol **) coff_section_data (output_bfd, osec)->tdata;
else
{
const char *sec_name;
asymbol **syms, **sym_end;
sec_name = bfd_get_section_name (output_bfd, osec);
syms = bfd_get_outsymbols (output_bfd);
sym_end = syms + bfd_get_symcount (output_bfd);
for (; syms < sym_end; syms++)
{
if (bfd_asymbol_name (*syms) != NULL
&& (*syms)->value == 0
&& strcmp ((*syms)->section->output_section->name,
sec_name) == 0)
break;
}
if (syms >= sym_end)
abort ();
reloc_entry->sym_ptr_ptr = syms;
if (coff_section_data (output_bfd, osec) == NULL)
{
bfd_size_type amt = sizeof (struct coff_section_tdata);
osec->used_by_bfd = bfd_zalloc (abfd, amt);
if (osec->used_by_bfd == NULL)
return bfd_reloc_overflow;
}
coff_section_data (output_bfd, osec)->tdata = syms;
}
/* Let bfd_perform_relocation do its thing, which will include
stuffing the symbol addend into the object file. */
return bfd_reloc_continue;
}
static reloc_howto_type howto_rellong =
HOWTO ((unsigned int) R_RELLONG, 0, 2, 32,FALSE, 0,
complain_overflow_bitfield, coff_i960_relocate,"rellong", TRUE,
0xffffffff, 0xffffffff, 0);
static reloc_howto_type howto_iprmed =
HOWTO (R_IPRMED, 0, 2, 24,TRUE,0, complain_overflow_signed,
coff_i960_relocate, "iprmed ", TRUE, 0x00ffffff, 0x00ffffff, 0);
static reloc_howto_type howto_optcall =
HOWTO (R_OPTCALL, 0,2,24,TRUE,0, complain_overflow_signed,
optcall_callback, "optcall", TRUE, 0x00ffffff, 0x00ffffff, 0);
static reloc_howto_type *
coff_i960_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
bfd_reloc_code_real_type code)
{
switch (code)
{
default:
return 0;
case BFD_RELOC_I960_CALLJ:
return &howto_optcall;
case BFD_RELOC_32:
case BFD_RELOC_CTOR:
return &howto_rellong;
case BFD_RELOC_24_PCREL:
return &howto_iprmed;
}
}
static reloc_howto_type *
coff_i960_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
const char *r_name)
{
if (strcasecmp (howto_optcall.name, r_name) == 0)
return &howto_optcall;
if (strcasecmp (howto_rellong.name, r_name) == 0)
return &howto_rellong;
if (strcasecmp (howto_iprmed.name, r_name) == 0)
return &howto_iprmed;
return NULL;
}
/* The real code is in coffcode.h */
#define RTYPE2HOWTO(cache_ptr, dst) \
{ \
reloc_howto_type *howto_ptr; \
switch ((dst)->r_type) { \
case 17: howto_ptr = &howto_rellong; break; \
case 25: howto_ptr = &howto_iprmed; break; \
case 27: howto_ptr = &howto_optcall; break; \
default: howto_ptr = 0; break; \
} \
(cache_ptr)->howto = howto_ptr; \
}
/* i960 COFF is used by VxWorks 5.1. However, VxWorks 5.1 does not
appear to correctly handle a reloc against a symbol defined in the
same object file. It appears to simply discard such relocs, rather
than adding their values into the object file. We handle this by
converting all relocs against global symbols into relocs against
internal symbols at the start of the section. This routine is
called at the start of the linking process, and it creates the
necessary symbols. */
static bfd_boolean
coff_i960_start_final_link (bfd *abfd, struct bfd_link_info *info)
{
bfd_size_type symesz = bfd_coff_symesz (abfd);
asection *o;
bfd_byte *esym;
if (! bfd_link_relocatable (info))
return TRUE;
esym = (bfd_byte *) bfd_malloc (symesz);
if (esym == NULL)
return FALSE;
if (bfd_seek (abfd, obj_sym_filepos (abfd), SEEK_SET) != 0)
return FALSE;
for (o = abfd->sections; o != NULL; o = o->next)
{
struct internal_syment isym;
strncpy (isym._n._n_name, o->name, SYMNMLEN);
isym.n_value = 0;
isym.n_scnum = o->target_index;
isym.n_type = T_NULL;
isym.n_sclass = C_STAT;
isym.n_numaux = 0;
bfd_coff_swap_sym_out (abfd, &isym, esym);
if (bfd_bwrite (esym, symesz, abfd) != symesz)
{
free (esym);
return FALSE;
}
obj_raw_syment_count (abfd) += 1;
}
free (esym);
return TRUE;
}
/* The reloc processing routine for the optimized COFF linker. */
static bfd_boolean
coff_i960_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
struct bfd_link_info *info,
bfd *input_bfd,
asection *input_section,
bfd_byte *contents,
struct internal_reloc *relocs,
struct internal_syment *syms,
asection **sections)
{
struct internal_reloc *rel;
struct internal_reloc *relend;
rel = relocs;
relend = rel + input_section->reloc_count;
for (; rel < relend; rel++)
{
long symndx;
struct coff_link_hash_entry *h;
struct internal_syment *sym;
bfd_vma addend;
bfd_vma val;
reloc_howto_type *howto;
bfd_reloc_status_type rstat = bfd_reloc_ok;
bfd_boolean done;
symndx = rel->r_symndx;
if (symndx == -1)
{
h = NULL;
sym = NULL;
}
else
{
h = obj_coff_sym_hashes (input_bfd)[symndx];
sym = syms + symndx;
}
if (sym != NULL && sym->n_scnum != 0)
addend = - sym->n_value;
else
addend = 0;
switch (rel->r_type)
{
case 17: howto = &howto_rellong; break;
case 25: howto = &howto_iprmed; break;
case 27: howto = &howto_optcall; break;
default:
bfd_set_error (bfd_error_bad_value);
return FALSE;
}
val = 0;
if (h == NULL)
{
asection *sec;
if (symndx == -1)
{
sec = bfd_abs_section_ptr;
val = 0;
}
else
{
sec = sections[symndx];
val = (sec->output_section->vma
+ sec->output_offset
+ sym->n_value
- sec->vma);
}
}
else
{
if (h->root.type == bfd_link_hash_defined
|| h->root.type == bfd_link_hash_defweak)
{
asection *sec;
sec = h->root.u.def.section;
val = (h->root.u.def.value
+ sec->output_section->vma
+ sec->output_offset);
}
else if (! bfd_link_relocatable (info))
(*info->callbacks->undefined_symbol)
(info, h->root.root.string, input_bfd, input_section,
rel->r_vaddr - input_section->vma, TRUE);
}
done = FALSE;
if (howto->type == R_OPTCALL && ! bfd_link_relocatable (info) && symndx != -1)
{
int class_val;
if (h != NULL)
class_val = h->symbol_class;
else
class_val = sym->n_sclass;
switch (class_val)
{
case C_NULL:
/* This symbol is apparently not from a COFF input file.
We warn, and then assume that it is not a leaf
function. */
(*info->callbacks->reloc_dangerous)
(info,
_("uncertain calling convention for non-COFF symbol"),
input_bfd, input_section,
rel->r_vaddr - input_section->vma);
break;
case C_LEAFSTAT:
case C_LEAFEXT:
/* This is a call to a leaf procedure; use the bal
instruction. */
{
long olf;
unsigned long word;
if (h != NULL)
{
BFD_ASSERT (h->numaux == 2);
olf = h->aux[1].x_bal.x_balntry;
}
else
{
bfd_byte *esyms;
union internal_auxent aux;
BFD_ASSERT (sym->n_numaux == 2);
esyms = (bfd_byte *) obj_coff_external_syms (input_bfd);
esyms += (symndx + 2) * bfd_coff_symesz (input_bfd);
bfd_coff_swap_aux_in (input_bfd, esyms, sym->n_type,
sym->n_sclass, 1, sym->n_numaux,
&aux);
olf = aux.x_bal.x_balntry;
}
word = bfd_get_32 (input_bfd,
(contents
+ (rel->r_vaddr - input_section->vma)));
word = ((word + olf - val) & BAL_MASK) | BAL;
bfd_put_32 (input_bfd,
(bfd_vma) word,
contents + (rel->r_vaddr - input_section->vma));
done = TRUE;
}
break;
case C_SCALL:
BFD_ASSERT (0);
break;
}
}
if (! done)
{
if (howto->pc_relative)
addend += input_section->vma;
rstat = _bfd_final_link_relocate (howto, input_bfd, input_section,
contents,
rel->r_vaddr - input_section->vma,
val, addend);
}
switch (rstat)
{
default:
abort ();
case bfd_reloc_ok:
break;
case bfd_reloc_overflow:
{
const char *name;
char buf[SYMNMLEN + 1];
if (symndx == -1)
name = "*ABS*";
else if (h != NULL)
name = NULL;
else
{
name = _bfd_coff_internal_syment_name (input_bfd, sym, buf);
if (name == NULL)
return FALSE;
}
(*info->callbacks->reloc_overflow)
(info, (h ? &h->root : NULL), name, howto->name,
(bfd_vma) 0, input_bfd, input_section,
rel->r_vaddr - input_section->vma);
}
}
}
return TRUE;
}
/* Adjust the symbol index of any reloc against a global symbol to
instead be a reloc against the internal symbol we created specially
for the section. */
static bfd_boolean
coff_i960_adjust_symndx (bfd *obfd ATTRIBUTE_UNUSED,
struct bfd_link_info *info ATTRIBUTE_UNUSED,
bfd *ibfd,
asection *sec ATTRIBUTE_UNUSED,
struct internal_reloc *irel,
bfd_boolean *adjustedp)
{
struct coff_link_hash_entry *h;
*adjustedp = FALSE;
h = obj_coff_sym_hashes (ibfd)[irel->r_symndx];
if (h == NULL
|| (h->root.type != bfd_link_hash_defined
&& h->root.type != bfd_link_hash_defweak))
return TRUE;
irel->r_symndx = h->root.u.def.section->output_section->target_index - 1;
*adjustedp = TRUE;
return TRUE;
}
#define coff_bfd_is_local_label_name coff_i960_is_local_label_name
#define coff_start_final_link coff_i960_start_final_link
#define coff_relocate_section coff_i960_relocate_section
#define coff_adjust_symndx coff_i960_adjust_symndx
#define coff_bfd_reloc_type_lookup coff_i960_reloc_type_lookup
#define coff_bfd_reloc_name_lookup coff_i960_reloc_name_lookup
#include "coffcode.h"
extern const bfd_target icoff_be_vec;
CREATE_LITTLE_COFF_TARGET_VEC (icoff_le_vec, "coff-Intel-little", 0, 0, '_', & icoff_be_vec, COFF_SWAP_TABLE)
const bfd_target icoff_be_vec =
{
"coff-Intel-big", /* name */
bfd_target_coff_flavour,
BFD_ENDIAN_LITTLE, /* data byte order is little */
BFD_ENDIAN_BIG, /* header byte order is big */
(HAS_RELOC | EXEC_P /* object flags */
| HAS_LINENO | HAS_DEBUG
| HAS_SYMS | HAS_LOCALS | WP_TEXT),
(SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC), /* section flags */
'_', /* leading underscore */
'/', /* ar_pad_char */
15, /* ar_max_namelen */
0, /* match priority. */
bfd_getl64, bfd_getl_signed_64, bfd_putl64,
bfd_getl32, bfd_getl_signed_32, bfd_putl32,
bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */
bfd_getb64, bfd_getb_signed_64, bfd_putb64,
bfd_getb32, bfd_getb_signed_32, bfd_putb32,
bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* hdrs */
{ /* bfd_check_format */
_bfd_dummy_target,
coff_object_p,
bfd_generic_archive_p,
_bfd_dummy_target
},
{ /* bfd_set_format */
_bfd_bool_bfd_false_error,
coff_mkobject,
_bfd_generic_mkarchive,
_bfd_bool_bfd_false_error
},
{ /* bfd_write_contents */
_bfd_bool_bfd_false_error,
coff_write_object_contents,
_bfd_write_archive_contents,
_bfd_bool_bfd_false_error
},
BFD_JUMP_TABLE_GENERIC (coff),
BFD_JUMP_TABLE_COPY (coff),
BFD_JUMP_TABLE_CORE (_bfd_nocore),
BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
BFD_JUMP_TABLE_SYMBOLS (coff),
BFD_JUMP_TABLE_RELOCS (coff),
BFD_JUMP_TABLE_WRITE (coff),
BFD_JUMP_TABLE_LINK (coff),
BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
&icoff_le_vec,
COFF_SWAP_TABLE
};

168
bfd/coffcode.h
View File

@ -40,11 +40,6 @@ SECTION
defines the relocations used by the 88k format
@xref{Relocations}.
The Intel i960 processor version of coff is implemented in
@file{coff-i960.c}. This file has the same structure as
@file{coff-m88k.c}, except that it includes @file{coff/i960.h}
rather than @file{coff-m88k.h}.
SUBSECTION
Porting to a new version of coff
@ -97,15 +92,6 @@ SUBSUBSECTION
Some of the Coff targets then also have additional routines in
the target source file itself.
For example, @file{coff-i960.c} includes
@file{coff/internal.h} and @file{coff/i960.h}. It then
defines a few constants, such as @code{I960}, and includes
@file{coffcode.h}. Since the i960 has complex relocation
types, @file{coff-i960.c} also includes some code to
manipulate the i960 relocs. This code is not in
@file{coffcode.h} because it would not be used by any other
target.
SUBSUBSECTION
Coff long section names
@ -1664,19 +1650,6 @@ coff_bad_format_hook (bfd * abfd ATTRIBUTE_UNUSED, void * filehdr)
if (BADMAG (*internal_f))
return FALSE;
/* If the optional header is NULL or not the correct size then
quit; the only difference I can see between m88k dgux headers (MC88DMAGIC)
and Intel 960 readwrite headers (I960WRMAGIC) is that the
optional header is of a different size.
But the mips keeps extra stuff in it's opthdr, so dont check
when doing that. */
#if defined(M88) || defined(I960)
if (internal_f->f_opthdr != 0 && bfd_coff_aoutsz (abfd) != internal_f->f_opthdr)
return FALSE;
#endif
return TRUE;
}
@ -1848,12 +1821,6 @@ coff_set_alignment_hook (bfd * abfd ATTRIBUTE_UNUSED,
struct internal_scnhdr *hdr = (struct internal_scnhdr *) scnhdr;
unsigned int i;
#ifdef I960
/* Extract ALIGN from 2**ALIGN stored in section header. */
for (i = 0; i < 32; i++)
if ((1 << i) >= hdr->s_align)
break;
#endif
#ifdef COFF_DECODE_ALIGNMENT
i = COFF_DECODE_ALIGNMENT(hdr->s_flags);
#endif
@ -2235,47 +2202,6 @@ coff_set_arch_mach_hook (bfd *abfd, void * filehdr)
}
break;
#endif
#ifdef I860
case I860MAGIC:
arch = bfd_arch_i860;
break;
#endif
#ifdef I960
#ifdef I960ROMAGIC
case I960ROMAGIC:
case I960RWMAGIC:
arch = bfd_arch_i960;
switch (F_I960TYPE & internal_f->f_flags)
{
default:
case F_I960CORE:
machine = bfd_mach_i960_core;
break;
case F_I960KB:
machine = bfd_mach_i960_kb_sb;
break;
case F_I960MC:
machine = bfd_mach_i960_mc;
break;
case F_I960XA:
machine = bfd_mach_i960_xa;
break;
case F_I960CA:
machine = bfd_mach_i960_ca;
break;
case F_I960KA:
machine = bfd_mach_i960_ka_sa;
break;
case F_I960JX:
machine = bfd_mach_i960_jx;
break;
case F_I960HX:
machine = bfd_mach_i960_hx;
break;
}
break;
#endif
#endif
#ifdef RS6000COFF_C
#ifdef XCOFF64
@ -2552,31 +2478,7 @@ coff_pointerize_aux_hook (bfd *abfd ATTRIBUTE_UNUSED,
}
#else
#ifdef I960
/* We don't want to pointerize bal entries. */
static bfd_boolean
coff_pointerize_aux_hook (bfd *abfd ATTRIBUTE_UNUSED,
combined_entry_type *table_base ATTRIBUTE_UNUSED,
combined_entry_type *symbol,
unsigned int indaux,
combined_entry_type *aux ATTRIBUTE_UNUSED)
{
/* Return TRUE if we don't want to pointerize this aux entry, which
is the case for the lastfirst aux entry for a C_LEAFPROC symbol. */
return (indaux == 1
&& symbol->is_sym
&& (symbol->u.syment.n_sclass == C_LEAFPROC
|| symbol->u.syment.n_sclass == C_LEAFSTAT
|| symbol->u.syment.n_sclass == C_LEAFEXT));
}
#else /* ! I960 */
#define coff_pointerize_aux_hook 0
#endif /* ! I960 */
#endif /* ! RS6000COFF_C */
/* Print an aux entry. This returns TRUE if it has printed it. */
@ -2856,32 +2758,6 @@ coff_set_flags (bfd * abfd,
return TRUE;
#endif
#ifdef I960ROMAGIC
case bfd_arch_i960:
{
unsigned flags;
*magicp = I960ROMAGIC;
switch (bfd_get_mach (abfd))
{
case bfd_mach_i960_core: flags = F_I960CORE; break;
case bfd_mach_i960_kb_sb: flags = F_I960KB; break;
case bfd_mach_i960_mc: flags = F_I960MC; break;
case bfd_mach_i960_xa: flags = F_I960XA; break;
case bfd_mach_i960_ca: flags = F_I960CA; break;
case bfd_mach_i960_ka_sa: flags = F_I960KA; break;
case bfd_mach_i960_jx: flags = F_I960JX; break;
case bfd_mach_i960_hx: flags = F_I960HX; break;
default: return FALSE;
}
*flagsp = flags;
return TRUE;
}
break;
#endif
#ifdef TIC30MAGIC
case bfd_arch_tic30:
*magicp = TIC30MAGIC;
@ -2981,12 +2857,6 @@ coff_set_flags (bfd * abfd,
return TRUE;
#endif
#ifdef I860MAGIC
case bfd_arch_i860:
*magicp = I860MAGIC;
return TRUE;
#endif
#ifdef IA64MAGIC
case bfd_arch_ia64:
*magicp = IA64MAGIC;
@ -3146,9 +3016,7 @@ sort_by_secaddr (const void * arg1, const void * arg2)
/* Calculate the file position for each section. */
#ifndef I960
#define ALIGN_SECTIONS_IN_FILE
#endif
#if defined(TIC80COFF) || defined(TICOFF)
#undef ALIGN_SECTIONS_IN_FILE
#endif
@ -3389,9 +3257,7 @@ coff_compute_section_file_positions (bfd * abfd)
#endif
/* Align the sections in the file to the same boundary on
which they are aligned in virtual memory. I960 doesn't
do this (FIXME) so we can stay in sync with Intel. 960
doesn't yet page from files... */
which they are aligned in virtual memory. */
#ifdef ALIGN_SECTIONS_IN_FILE
if ((abfd->flags & EXEC_P) != 0)
{
@ -3855,11 +3721,6 @@ coff_write_object_contents (bfd * abfd)
else if (!strcmp (current->name, _BSS))
bss_sec = current;
#ifdef I960
section.s_align = (current->alignment_power
? 1 << current->alignment_power
: 0);
#endif
#ifdef COFF_ENCODE_ALIGNMENT
COFF_ENCODE_ALIGNMENT(section, current->alignment_power);
if ((unsigned int)COFF_DECODE_ALIGNMENT(section.s_flags)
@ -4118,15 +3979,6 @@ coff_write_object_contents (bfd * abfd)
internal_a.magic = TIC80_ARCH_MAGIC;
#define __A_MAGIC_SET__
#endif /* TIC80 */
#ifdef I860
/* FIXME: What are the a.out magic numbers for the i860? */
internal_a.magic = 0;
#define __A_MAGIC_SET__
#endif /* I860 */
#ifdef I960
internal_a.magic = (magic == I960ROMAGIC ? NMAGIC : OMAGIC);
#define __A_MAGIC_SET__
#endif /* I960 */
#if M88
#define __A_MAGIC_SET__
internal_a.magic = PAGEMAGICBCS;
@ -4820,11 +4672,6 @@ coff_slurp_symbol_table (bfd * abfd)
switch (src->u.syment.n_sclass)
{
#ifdef I960
case C_LEAFEXT:
/* Fall through to next case. */
#endif
case C_EXT:
case C_WEAKEXT:
#if defined ARM
@ -4918,9 +4765,6 @@ coff_slurp_symbol_table (bfd * abfd)
break;
case C_STAT: /* Static. */
#ifdef I960
case C_LEAFSTAT: /* Static leaf procedure. */
#endif
#if defined ARM
case C_THUMBSTAT: /* Thumb static. */
case C_THUMBLABEL: /* Thumb label. */
@ -4958,11 +4802,6 @@ coff_slurp_symbol_table (bfd * abfd)
case C_REGPARM: /* Register parameter. */
case C_REG: /* register variable. */
/* C_AUTOARG conflicts with TI COFF C_UEXT. */
#if !defined (TIC80COFF) && !defined (TICOFF)
#ifdef C_AUTOARG
case C_AUTOARG: /* 960-specific storage class. */
#endif
#endif
case C_TPDEF: /* Type definition. */
case C_ARG:
case C_AUTO: /* Automatic variable. */
@ -5158,9 +4997,6 @@ coff_classify_symbol (bfd *abfd,
{
case C_EXT:
case C_WEAKEXT:
#ifdef I960
case C_LEAFEXT:
#endif
#ifdef ARM
case C_THUMBEXT:
case C_THUMBEXTFUNC:
@ -5262,7 +5098,7 @@ SUBSUBSECTION
o The reloc index is turned into a pointer to a howto
structure, in a back end specific way. For instance, the 386
and 960 use the @code{r_type} to directly produce an index
uses the @code{r_type} to directly produce an index
into a howto table vector; the 88k subtracts a number from the
@code{r_type} field and creates an addend field.
*/

14
bfd/coffswap.h
View File

@ -618,10 +618,6 @@ coff_swap_aouthdr_in (bfd * abfd, void * aouthdr_ext1, void * aouthdr_int1)
aouthdr_int->data_start =
GET_AOUTHDR_DATA_START (abfd, aouthdr_ext->data_start);
#ifdef I960
aouthdr_int->tagentries = H_GET_32 (abfd, aouthdr_ext->tagentries);
#endif
#ifdef APOLLO_M68
H_PUT_32 (abfd, aouthdr_int->o_inlib, aouthdr_ext->o_inlib);
H_PUT_32 (abfd, aouthdr_int->o_sri, aouthdr_ext->o_sri);
@ -689,10 +685,6 @@ coff_swap_aouthdr_out (bfd * abfd, void * in, void * out)
PUT_AOUTHDR_DATA_START (abfd, aouthdr_in->data_start,
aouthdr_out->data_start);
#ifdef I960
H_PUT_32 (abfd, aouthdr_in->tagentries, aouthdr_out->tagentries);
#endif
#ifdef RS6000COFF_C
#ifdef XCOFF64
H_PUT_64 (abfd, aouthdr_in->o_toc, aouthdr_out->o_toc);
@ -767,9 +759,6 @@ coff_swap_scnhdr_in (bfd * abfd, void * ext, void * in)
scnhdr_int->s_flags = GET_SCNHDR_FLAGS (abfd, scnhdr_ext->s_flags);
scnhdr_int->s_nreloc = GET_SCNHDR_NRELOC (abfd, scnhdr_ext->s_nreloc);
scnhdr_int->s_nlnno = GET_SCNHDR_NLNNO (abfd, scnhdr_ext->s_nlnno);
#ifdef I960
scnhdr_int->s_align = GET_SCNHDR_ALIGN (abfd, scnhdr_ext->s_align);
#endif
#ifdef COFF_ADJUST_SCNHDR_IN_POST
COFF_ADJUST_SCNHDR_IN_POST (abfd, ext, in);
#endif
@ -830,9 +819,6 @@ coff_swap_scnhdr_out (bfd * abfd, void * in, void * out)
}
#endif
#ifdef I960
PUT_SCNHDR_ALIGN (abfd, scnhdr_int->s_align, scnhdr_ext->s_align);
#endif
#ifdef COFF_ADJUST_SCNHDR_OUT_POST
COFF_ADJUST_SCNHDR_OUT_POST (abfd, in, out);
#endif

43
bfd/config.bfd
View File

@ -81,8 +81,6 @@ case $targ in
i[3-7]86-*-os9k | \
i[3-7]86-none-* | \
i[3-7]86-*-aout* | i[3-7]86*-*-vsta* | \
i860-*-* | \
i960-*-* | \
m68*-motorola-sysv* | m68*-hp-bsd* | m68*-*-aout* | \
m68*-*-coff* | m68*-*-sysv* | \
m68*-*-hpux* | \
@ -115,7 +113,6 @@ case $targ in
we32k-*-* | \
w65-*-* | \
*-*-ieee* | \
*-adobe-* | \
*-sony-* | \
*-tandem-* | \
i370-* | \
@ -131,13 +128,15 @@ case $targ in
esac
case $targ in
*-adobe-* | \
*-go32-rtems* | \
*-*-rtemsaout* | \
*-*-rtemscoff* | \
a29k-* | \
arm-*-oabi | \
hppa*-*-rtems* | \
i960-*-rtems* | \
i860-*-* | \
i960-*-* | \
m68*-*-lynxos* | \
m68*-apollo-* | \
m68*-apple-aux* | \
@ -882,37 +881,6 @@ case "${targ}" in
targ_selfvecs="iamcu_elf32_vec i386chaos_vec"
;;
i860-*-mach3* | i860-*-osf1* | i860-*-coff*)
targ_defvec=i860_coff_vec
;;
i860-stardent-sysv4* | i860-stardent-elf*)
targ_defvec=i860_elf32_le_vec
targ_selvecs="i860_elf32_vec i860_elf32_le_vec"
;;
i860-*-sysv4* | i860-*-elf*)
targ_defvec=i860_elf32_vec
;;
i960-*-vxworks4* | i960-*-vxworks5.0)
targ_defvec=bout_le_vec
targ_selvecs="bout_be_vec icoff_le_vec icoff_be_vec ieee_vec"
targ_underscore=yes
;;
i960-*-vxworks5.* | i960-*-coff* | i960-*-sysv*)
targ_defvec=icoff_le_vec
targ_selvecs="icoff_be_vec bout_le_vec bout_be_vec ieee_vec"
targ_underscore=yes
;;
i960-*-vxworks* | i960-*-aout* | i960-*-bout* | i960-*-nindy*)
targ_defvec=bout_le_vec
targ_selvecs="bout_be_vec icoff_le_vec icoff_be_vec ieee_vec"
targ_underscore=yes
;;
i960-*-elf*)
targ_defvec=i960_elf32_vec
targ_selvecs="icoff_le_vec icoff_be_vec"
;;
ia16-*-elf)
targ_defvec=i386_elf32_vec
targ_selvecs="i386_msdos_vec i386_aout_vec"
@ -1854,11 +1822,6 @@ case "${targ}" in
targ_defvec=ieee_vec
;;
*-adobe-*)
targ_defvec=aout_adobe_vec
targ_underscore=yes
;;
*-sony-*)
targ_defvec=m68k_aout_newsos3_vec
targ_underscore=yes

13
bfd/configure vendored
View File

@ -14344,7 +14344,6 @@ do
aout0_be_vec) tb="$tb aout0.lo aout32.lo" ;;
aout64_vec) tb="$tb demo64.lo aout64.lo"; target_size=64 ;;
aout_vec) tb="$tb host-aout.lo aout32.lo" ;;
aout_adobe_vec) tb="$tb aout-adobe.lo aout32.lo" ;;
arc_elf32_be_vec) tb="$tb elf32-arc.lo elf32.lo $elf" ;;
arc_elf32_le_vec) tb="$tb elf32-arc.lo elf32.lo $elf" ;;
arm_aout_be_vec) tb="$tb aout-arm.lo aout32.lo" ;;
@ -14377,8 +14376,6 @@ do
avr_elf32_vec) tb="$tb elf32-avr.lo elf32.lo $elf" ;;
bfin_elf32_vec) tb="$tb elf32-bfin.lo elf32.lo $elf" ;;
bfin_elf32_fdpic_vec) tb="$tb elf32-bfin.lo elf32.lo $elf" ;;
bout_be_vec) tb="$tb bout.lo aout32.lo" ;;
bout_le_vec) tb="$tb bout.lo aout32.lo" ;;
cr16_elf32_vec) tb="$tb elf32-cr16.lo elf32.lo $elf" ;;
cr16c_elf32_vec) tb="$tb elf32-cr16c.lo elf32.lo $elf" ;;
cris_aout_vec) tb="$tb aout-cris.lo" ;;
@ -14431,10 +14428,6 @@ do
i386_pe_vec) tb="$tb pe-i386.lo peigen.lo $coff" ;;
i386_pei_vec) tb="$tb pei-i386.lo peigen.lo $coff" ;;
iamcu_elf32_vec) tb="$tb elf32-i386.lo elfxx-x86.lo elf-ifunc.lo elf-nacl.lo elf-vxworks.lo elf32.lo $elf" ;;
i860_coff_vec) tb="$tb coff-i860.lo $coff" ;;
i860_elf32_vec) tb="$tb elf32-i860.lo elf32.lo $elf" ;;
i860_elf32_le_vec) tb="$tb elf32-i860.lo elf32.lo $elf" ;;
i960_elf32_vec) tb="$tb elf32-i960.lo elf32.lo $elf" ;;
ia64_elf32_be_vec) tb="$tb elf32-ia64.lo elfxx-ia64.lo elf32.lo $elf" ;;
ia64_elf32_hpux_be_vec) tb="$tb elf32-ia64.lo elfxx-ia64.lo elf32.lo $elf" ;;
ia64_elf64_be_vec) tb="$tb elf64-ia64.lo elfxx-ia64.lo elf64.lo $elf"; target_size=64 ;;
@ -14442,8 +14435,6 @@ do
ia64_elf64_hpux_be_vec) tb="$tb elf64-ia64.lo elfxx-ia64.lo elf64.lo $elf"; target_size=64 ;;
ia64_elf64_vms_vec) tb="$tb elf64-ia64-vms.lo elf64-ia64.lo elfxx-ia64.lo elf64.lo vms-lib.lo vms-misc.lo $elf"; target_size=64 ;;
ia64_pei_vec) tb="$tb pei-ia64.lo pepigen.lo $coff"; target_size=64 ;;
icoff_be_vec) tb="$tb coff-i960.lo $coff" ;;
icoff_le_vec) tb="$tb coff-i960.lo $coff" ;;
ieee_vec) tb="$tb ieee.lo" ;;
ip2k_elf32_vec) tb="$tb elf32-ip2k.lo elf32.lo $elf" ;;
iq2000_elf32_vec) tb="$tb elf32-iq2000.lo elf32.lo $elf" ;;
@ -14890,10 +14881,6 @@ if test "${target}" = "${host}"; then
;;
i[3-7]86-*-isc*) COREFILE=trad-core.lo ;;
i[3-7]86-*-aix*) COREFILE=aix386-core.lo ;;
i860-*-mach3* | i860-*-osf1*)
COREFILE=trad-core.lo
TRAD_HEADER='"hosts/i860mach3.h"'
;;
mips-*-netbsd* | mips*-*-openbsd*)
COREFILE=netbsd-core.lo
;;

13
bfd/configure.ac
View File

@ -421,7 +421,6 @@ do
aout0_be_vec) tb="$tb aout0.lo aout32.lo" ;;
aout64_vec) tb="$tb demo64.lo aout64.lo"; target_size=64 ;;
aout_vec) tb="$tb host-aout.lo aout32.lo" ;;
aout_adobe_vec) tb="$tb aout-adobe.lo aout32.lo" ;;
arc_elf32_be_vec) tb="$tb elf32-arc.lo elf32.lo $elf" ;;
arc_elf32_le_vec) tb="$tb elf32-arc.lo elf32.lo $elf" ;;
arm_aout_be_vec) tb="$tb aout-arm.lo aout32.lo" ;;
@ -454,8 +453,6 @@ do
avr_elf32_vec) tb="$tb elf32-avr.lo elf32.lo $elf" ;;
bfin_elf32_vec) tb="$tb elf32-bfin.lo elf32.lo $elf" ;;
bfin_elf32_fdpic_vec) tb="$tb elf32-bfin.lo elf32.lo $elf" ;;
bout_be_vec) tb="$tb bout.lo aout32.lo" ;;
bout_le_vec) tb="$tb bout.lo aout32.lo" ;;
cr16_elf32_vec) tb="$tb elf32-cr16.lo elf32.lo $elf" ;;
cr16c_elf32_vec) tb="$tb elf32-cr16c.lo elf32.lo $elf" ;;
cris_aout_vec) tb="$tb aout-cris.lo" ;;
@ -508,10 +505,6 @@ do
i386_pe_vec) tb="$tb pe-i386.lo peigen.lo $coff" ;;
i386_pei_vec) tb="$tb pei-i386.lo peigen.lo $coff" ;;
iamcu_elf32_vec) tb="$tb elf32-i386.lo elfxx-x86.lo elf-ifunc.lo elf-nacl.lo elf-vxworks.lo elf32.lo $elf" ;;
i860_coff_vec) tb="$tb coff-i860.lo $coff" ;;
i860_elf32_vec) tb="$tb elf32-i860.lo elf32.lo $elf" ;;
i860_elf32_le_vec) tb="$tb elf32-i860.lo elf32.lo $elf" ;;
i960_elf32_vec) tb="$tb elf32-i960.lo elf32.lo $elf" ;;
ia64_elf32_be_vec) tb="$tb elf32-ia64.lo elfxx-ia64.lo elf32.lo $elf" ;;
ia64_elf32_hpux_be_vec) tb="$tb elf32-ia64.lo elfxx-ia64.lo elf32.lo $elf" ;;
ia64_elf64_be_vec) tb="$tb elf64-ia64.lo elfxx-ia64.lo elf64.lo $elf"; target_size=64 ;;
@ -519,8 +512,6 @@ do
ia64_elf64_hpux_be_vec) tb="$tb elf64-ia64.lo elfxx-ia64.lo elf64.lo $elf"; target_size=64 ;;
ia64_elf64_vms_vec) tb="$tb elf64-ia64-vms.lo elf64-ia64.lo elfxx-ia64.lo elf64.lo vms-lib.lo vms-misc.lo $elf"; target_size=64 ;;
ia64_pei_vec) tb="$tb pei-ia64.lo pepigen.lo $coff"; target_size=64 ;;
icoff_be_vec) tb="$tb coff-i960.lo $coff" ;;
icoff_le_vec) tb="$tb coff-i960.lo $coff" ;;
ieee_vec) tb="$tb ieee.lo" ;;
ip2k_elf32_vec) tb="$tb elf32-ip2k.lo elf32.lo $elf" ;;
iq2000_elf32_vec) tb="$tb elf32-iq2000.lo elf32.lo $elf" ;;
@ -976,10 +967,6 @@ changequote(,)dnl
i[3-7]86-*-isc*) COREFILE=trad-core.lo ;;
i[3-7]86-*-aix*) COREFILE=aix386-core.lo ;;
changequote([,])dnl
i860-*-mach3* | i860-*-osf1*)
COREFILE=trad-core.lo
TRAD_HEADER='"hosts/i860mach3.h"'
;;
mips-*-netbsd* | mips*-*-openbsd*)
COREFILE=netbsd-core.lo
;;

42
bfd/cpu-i860.c
View File

@ -1,42 +0,0 @@
/* BFD support for the Intel 860 architecture.
Copyright (C) 1992-2018 Free Software Foundation, Inc.
Created mostly by substituting "860" for "386" in cpu-i386.c
Harry Dolan <dolan@ssd.intel.com>, October 1995
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "sysdep.h"
#include "bfd.h"
#include "libbfd.h"
const bfd_arch_info_type bfd_i860_arch =
{
32, /* 32 bits in a word */
32, /* 32 bits in an address */
8, /* 8 bits in a byte */
bfd_arch_i860, /* Architecture */
0, /* Only one machine */
"i860", /* Architecture name */
"i860", /* Printable name */
3, /* Section alignment exponent */
TRUE, /* Is this the default architecture? */
bfd_default_compatible,
bfd_default_scan,
bfd_arch_default_fill,
0, /* Next in list */
};

172
bfd/cpu-i960.c
View File

@ -1,172 +0,0 @@
/* BFD library support routines for the i960 architecture.
Copyright (C) 1990-2018 Free Software Foundation, Inc.
Hacked by Steve Chamberlain of Cygnus Support.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "sysdep.h"
#include "bfd.h"
#include "libbfd.h"
/* This routine is provided a string, and tries to work out if it
could possibly refer to the i960 machine pointed at in the
info_struct pointer */
static bfd_boolean
scan_960_mach (const bfd_arch_info_type *ap,
const char *string)
{
unsigned long machine;
int fail_because_not_80960 = FALSE;
/* Look for the string i960 at the front of the string. */
if (strncasecmp ("i960", string, 4) == 0)
{
string += 4;
/* i960 on it's own means core to us. */
if (* string == 0)
return ap->mach == bfd_mach_i960_core;
/* "i960:*" is valid, anything else is not. */
if (* string != ':')
return FALSE;
string ++;
}
/* In some bfds the cpu-id is written as "80960KA", "80960KB",
"80960CA" or "80960MC". */
else if (CONST_STRNEQ (string, "80960"))
{
string += 5;
/* Set this to TRUE here. If a correct matching postfix
is detected below it will be reset to FALSE. */
fail_because_not_80960 = TRUE;
}
/* No match, can't be us. */
else
return FALSE;
if (* string == '\0')
return FALSE;
if (string[0] == 'c' && string[1] == 'o' && string[2] == 'r' &&
string[3] == 'e' && string[4] == '\0')
machine = bfd_mach_i960_core;
else if (strcasecmp (string, "ka_sa") == 0)
machine = bfd_mach_i960_ka_sa;
else if (strcasecmp (string, "kb_sb") == 0)
machine = bfd_mach_i960_kb_sb;
else if (string[1] == '\0' || string[2] != '\0') /* rest are 2-char. */
return FALSE;
else if (string[0] == 'k' && string[1] == 'b')
{ machine = bfd_mach_i960_kb_sb; fail_because_not_80960 = FALSE; }
else if (string[0] == 's' && string[1] == 'b')
machine = bfd_mach_i960_kb_sb;
else if (string[0] == 'm' && string[1] == 'c')
{ machine = bfd_mach_i960_mc; fail_because_not_80960 = FALSE; }
else if (string[0] == 'x' && string[1] == 'a')
machine = bfd_mach_i960_xa;
else if (string[0] == 'c' && string[1] == 'a')
{ machine = bfd_mach_i960_ca; fail_because_not_80960 = FALSE; }
else if (string[0] == 'k' && string[1] == 'a')
{ machine = bfd_mach_i960_ka_sa; fail_because_not_80960 = FALSE; }
else if (string[0] == 's' && string[1] == 'a')
machine = bfd_mach_i960_ka_sa;
else if (string[0] == 'j' && string[1] == 'x')
machine = bfd_mach_i960_jx;
else if (string[0] == 'h' && string[1] == 'x')
machine = bfd_mach_i960_hx;
else
return FALSE;
if (fail_because_not_80960)
return FALSE;
if (machine == ap->mach)
return TRUE;
return FALSE;
}
/* This routine is provided two arch_infos and works out the i960
machine which would be compatible with both and returns a pointer
to its info structure */
static const bfd_arch_info_type *
compatible (const bfd_arch_info_type *a,
const bfd_arch_info_type *b)
{
/* The i960 has distinct subspecies which may not interbreed:
CORE CA
CORE KA KB MC XA
CORE HX JX
Any architecture on the same line is compatible, the one on
the right is the least restrictive.
We represent this information in an array, each machine to a side */
#define ERROR 0
#define CORE bfd_mach_i960_core /*1*/
#define KA bfd_mach_i960_ka_sa /*2*/
#define KB bfd_mach_i960_kb_sb /*3*/
#define MC bfd_mach_i960_mc /*4*/
#define XA bfd_mach_i960_xa /*5*/
#define CA bfd_mach_i960_ca /*6*/
#define JX bfd_mach_i960_jx /*7*/
#define HX bfd_mach_i960_hx /*8*/
#define MAX_ARCH ((int)HX)
static const unsigned long matrix[MAX_ARCH+1][MAX_ARCH+1] =
{
{ ERROR, CORE, KA, KB, MC, XA, CA, JX, HX },
{ CORE, CORE, KA, KB, MC, XA, CA, JX, HX },
{ KA, KA, KA, KB, MC, XA, ERROR, ERROR, ERROR},
{ KB, KB, KB, KB, MC, XA, ERROR, ERROR, ERROR},
{ MC, MC, MC, MC, MC, XA, ERROR, ERROR, ERROR},
{ XA, XA, XA, XA, XA, XA, ERROR, ERROR, ERROR},
{ CA, CA, ERROR, ERROR, ERROR, ERROR, CA, ERROR, ERROR},
{ JX, JX, ERROR, ERROR, ERROR, ERROR, ERROR, JX, HX },
{ HX, HX, ERROR, ERROR, ERROR, ERROR, ERROR, HX, HX },
};
if (a->arch != b->arch || matrix[a->mach][b->mach] == ERROR)
return NULL;
return (a->mach == matrix[a->mach][b->mach]) ? a : b;
}
#define N(a,b,d,n) \
{ 32, 32, 8,bfd_arch_i960,a,"i960",b,3,d,compatible,scan_960_mach, \
bfd_arch_default_fill, n,}
static const bfd_arch_info_type arch_info_struct[] =
{
N(bfd_mach_i960_ka_sa,"i960:ka_sa",FALSE, &arch_info_struct[1]),
N(bfd_mach_i960_kb_sb,"i960:kb_sb",FALSE, &arch_info_struct[2]),
N(bfd_mach_i960_mc, "i960:mc", FALSE, &arch_info_struct[3]),
N(bfd_mach_i960_xa, "i960:xa", FALSE, &arch_info_struct[4]),
N(bfd_mach_i960_ca, "i960:ca", FALSE, &arch_info_struct[5]),
N(bfd_mach_i960_jx, "i960:jx", FALSE, &arch_info_struct[6]),
N(bfd_mach_i960_hx, "i960:hx", FALSE, 0),
};
const bfd_arch_info_type bfd_i960_arch =
N(bfd_mach_i960_core, "i960:core", TRUE, &arch_info_struct[0]);

1274
bfd/elf32-i860.c
View File

File diff suppressed because it is too large Load Diff

169
bfd/elf32-i960.c
View File

@ -1,169 +0,0 @@
/* Intel 960 specific support for 32-bit ELF
Copyright (C) 1999-2018 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "sysdep.h"
#include "bfd.h"
#include "libbfd.h"
#include "elf-bfd.h"
#include "elf/i960.h"
#define USE_REL 1
#define bfd_elf32_bfd_reloc_type_lookup elf32_i960_reloc_type_lookup
#define bfd_elf32_bfd_reloc_name_lookup \
elf32_i960_reloc_name_lookup
#define elf_info_to_howto NULL
#define elf_info_to_howto_rel elf32_i960_info_to_howto_rel
/* ELF relocs are against symbols. If we are producing relocatable
output, and the reloc is against an external symbol, and nothing
has given us any additional addend, the resulting reloc will also
be against the same symbol. In such a case, we don't want to
change anything about the way the reloc is handled, since it will
all be done at final link time. Rather than put special case code
into bfd_perform_relocation, all the reloc types use this howto
function. It just short circuits the reloc if producing
relocatable output against an external symbol. */
static bfd_reloc_status_type
elf32_i960_relocate (bfd *abfd ATTRIBUTE_UNUSED,
arelent *reloc_entry,
asymbol *symbol,
void * data ATTRIBUTE_UNUSED,
asection *input_section,
bfd *output_bfd,
char **error_message ATTRIBUTE_UNUSED)
{
/* HACK: I think this first condition is necessary when producing
relocatable output. After the end of HACK, the code is identical
to bfd_elf_generic_reloc(). I would _guess_ the first change
belongs there rather than here. martindo 1998-10-23. */
if (output_bfd != (bfd *) NULL
&& reloc_entry->howto->pc_relative
&& !reloc_entry->howto->pcrel_offset)
reloc_entry->addend -= symbol->value;
/* This is more dubious. */
else if (output_bfd != (bfd *) NULL
&& (symbol->flags & BSF_SECTION_SYM) != 0)
reloc_entry->addend -= symbol->section->output_section->vma;
else
{
/* ...end of HACK. */
if (output_bfd != (bfd *) NULL
&& (symbol->flags & BSF_SECTION_SYM) == 0
&& (! reloc_entry->howto->partial_inplace
|| reloc_entry->addend == 0))
{
reloc_entry->address += input_section->output_offset;
return bfd_reloc_ok;
}
}
return bfd_reloc_continue;
}
static reloc_howto_type elf_howto_table[]=
{
HOWTO (R_960_NONE, 0, 3, 0, FALSE, 0, complain_overflow_dont,
elf32_i960_relocate, "R_960_NONE", TRUE,
0x00000000, 0x00000000, FALSE),
EMPTY_HOWTO (1),
HOWTO (R_960_32, 0, 2, 32, FALSE, 0, complain_overflow_bitfield,
elf32_i960_relocate, "R_960_32", TRUE,
0xffffffff, 0xffffffff, FALSE),
HOWTO (R_960_IP24, 0, 2, 24, TRUE, 0, complain_overflow_signed,
elf32_i960_relocate, "R_960_IP24 ", TRUE,
0x00ffffff, 0x00ffffff, FALSE),
EMPTY_HOWTO (4),
EMPTY_HOWTO (5),
EMPTY_HOWTO (6),
EMPTY_HOWTO (7)
};
static enum elf_i960_reloc_type
elf32_i960_bfd_to_reloc_type (bfd_reloc_code_real_type code)
{
switch (code)
{
default:
return R_960_NONE;
case BFD_RELOC_I960_CALLJ:
return R_960_OPTCALL;
case BFD_RELOC_32:
case BFD_RELOC_CTOR:
return R_960_32;
case BFD_RELOC_24_PCREL:
return R_960_IP24;
}
}
static bfd_boolean
elf32_i960_info_to_howto_rel (bfd *abfd ATTRIBUTE_UNUSED,
arelent *cache_ptr,
Elf_Internal_Rela *dst)
{
enum elf_i960_reloc_type type;
type = (enum elf_i960_reloc_type) ELF32_R_TYPE (dst->r_info);
/* PR 17521: file: 9609b8d6. */
if (type >= R_960_max)
{
/* xgettext:c-format */
_bfd_error_handler (_("%pB: unsupported relocation type %#x"),
abfd, type);
bfd_set_error (bfd_error_bad_value);
return FALSE;
}
cache_ptr->howto = &elf_howto_table[(int) type];
return TRUE;
}
static reloc_howto_type *
elf32_i960_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
bfd_reloc_code_real_type code)
{
return elf_howto_table + elf32_i960_bfd_to_reloc_type (code);
}
static reloc_howto_type *
elf32_i960_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
const char *r_name)
{
unsigned int i;
for (i = 0; i < sizeof (elf_howto_table) / sizeof (elf_howto_table[0]); i++)
if (elf_howto_table[i].name != NULL
&& strcasecmp (elf_howto_table[i].name, r_name) == 0)
return &elf_howto_table[i];
return NULL;
}
#define TARGET_LITTLE_SYM i960_elf32_vec
#define TARGET_LITTLE_NAME "elf32-i960"
#define ELF_ARCH bfd_arch_i960
#define ELF_MACHINE_CODE EM_960
#define ELF_MAXPAGESIZE 1 /* FIXME: This number is wrong, It should be the page size in bytes. */
#include "elf32-target.h"

46
bfd/hosts/i860mach3.h
View File

@ -1,46 +0,0 @@
/* Copyright (C) 2007-2018 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
/* This file was hacked from i386mach3.h [dolan@ssd.intel.com] */
#include <machine/vmparam.h>
#include <sys/param.h>
/* This is an ugly way to hack around the incorrect
* definition of UPAGES in i386/machparam.h.
*
* The definition should specify the size reserved
* for "struct user" in core files in PAGES,
* but instead it gives it in 512-byte core-clicks
* for i386 and i860. UPAGES is used only in trad-core.c.
*/
#if UPAGES == 16
#undef UPAGES
#define UPAGES 2
#endif
#if UPAGES != 2
FIXME!! UPAGES is neither 2 nor 16
#endif
#define HOST_PAGE_SIZE 1
#define HOST_SEGMENT_SIZE NBPG
#define HOST_MACHINE_ARCH bfd_arch_i860
#define HOST_TEXT_START_ADDR USRTEXT
#define HOST_STACK_END_ADDR USRSTACK

28
bfd/ieee.c
View File

@ -3567,34 +3567,6 @@ ieee_write_processor (bfd *abfd)
return FALSE;
break;
case bfd_arch_i960:
switch (arch->mach)
{
default:
case bfd_mach_i960_core:
case bfd_mach_i960_ka_sa:
if (! ieee_write_id (abfd, "80960KA"))
return FALSE;
break;
case bfd_mach_i960_kb_sb:
if (! ieee_write_id (abfd, "80960KB"))
return FALSE;
break;
case bfd_mach_i960_ca:
if (! ieee_write_id (abfd, "80960CA"))
return FALSE;
break;
case bfd_mach_i960_mc:
case bfd_mach_i960_xa:
if (! ieee_write_id (abfd, "80960MC"))
return FALSE;
break;
}
break;
case bfd_arch_m68k:
{
const char *id;

33
bfd/libbfd.h
View File

@ -981,7 +981,6 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_LO10",
"BFD_RELOC_GPREL16",
"BFD_RELOC_GPREL32",
"BFD_RELOC_I960_CALLJ",
"BFD_RELOC_NONE",
"BFD_RELOC_SPARC_WDISP22",
"BFD_RELOC_SPARC22",
@ -2588,38 +2587,6 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_CRIS_16_TPREL",
"BFD_RELOC_CRIS_DTPMOD",
"BFD_RELOC_CRIS_32_IE",
"BFD_RELOC_860_COPY",
"BFD_RELOC_860_GLOB_DAT",
"BFD_RELOC_860_JUMP_SLOT",
"BFD_RELOC_860_RELATIVE",
"BFD_RELOC_860_PC26",
"BFD_RELOC_860_PLT26",
"BFD_RELOC_860_PC16",
"BFD_RELOC_860_LOW0",
"BFD_RELOC_860_SPLIT0",
"BFD_RELOC_860_LOW1",
"BFD_RELOC_860_SPLIT1",
"BFD_RELOC_860_LOW2",
"BFD_RELOC_860_SPLIT2",
"BFD_RELOC_860_LOW3",
"BFD_RELOC_860_LOGOT0",
"BFD_RELOC_860_SPGOT0",
"BFD_RELOC_860_LOGOT1",
"BFD_RELOC_860_SPGOT1",
"BFD_RELOC_860_LOGOTOFF0",
"BFD_RELOC_860_SPGOTOFF0",
"BFD_RELOC_860_LOGOTOFF1",
"BFD_RELOC_860_SPGOTOFF1",
"BFD_RELOC_860_LOGOTOFF2",
"BFD_RELOC_860_LOGOTOFF3",
"BFD_RELOC_860_LOPC",
"BFD_RELOC_860_HIGHADJ",
"BFD_RELOC_860_HAGOT",
"BFD_RELOC_860_HAGOTOFF",
"BFD_RELOC_860_HAPC",
"BFD_RELOC_860_HIGH",
"BFD_RELOC_860_HIGOT",
"BFD_RELOC_860_HIGOTOFF",
"BFD_RELOC_OR1K_REL_26",
"BFD_RELOC_OR1K_GOTPC_HI16",
"BFD_RELOC_OR1K_GOTPC_LO16",

5
bfd/mach-o.c
View File

@ -1047,9 +1047,6 @@ bfd_mach_o_convert_architecture (bfd_mach_o_cpu_type mtype,
*type = bfd_arch_sparc;
*subtype = bfd_mach_sparc;
break;
case BFD_MACH_O_CPU_TYPE_I860:
*type = bfd_arch_i860;
break;
case BFD_MACH_O_CPU_TYPE_ALPHA:
*type = bfd_arch_alpha;
break;
@ -5446,8 +5443,6 @@ bfd_mach_o_stack_addr (enum bfd_mach_o_cpu_type type)
return 0xc0000000;
case BFD_MACH_O_CPU_TYPE_SPARC:
return 0xf0000000;
case BFD_MACH_O_CPU_TYPE_I860:
return 0;
case BFD_MACH_O_CPU_TYPE_HPPA:
return 0xc0000000 - 0x04000000;
default:

8
bfd/po/SRC-POTFILES.in
View File

@ -1,6 +1,5 @@
aix386-core.c
aix5ppc-core.c
aout-adobe.c
aout-arm.c
aout-cris.c
aout-ns32k.c
@ -20,7 +19,6 @@ bfd.c
bfdio.c
bfdwin.c
binary.c
bout.c
cache.c
cf-i386lynx.c
cf-sparclynx.c
@ -34,8 +32,6 @@ coff-go32.c
coff-h8300.c
coff-h8500.c
coff-i386.c
coff-i860.c
coff-i960.c
coff-m68k.c
coff-m88k.c
coff-mips.c
@ -83,8 +79,6 @@ cpu-h8500.c
cpu-hppa.c
cpu-i370.c
cpu-i386.c
cpu-i860.c
cpu-i960.c
cpu-ia64.c
cpu-iamcu.c
cpu-ip2k.c
@ -190,8 +184,6 @@ elf32-hppa.c
elf32-hppa.h
elf32-i370.c
elf32-i386.c
elf32-i860.c
elf32-i960.c
elf32-ip2k.c
elf32-iq2000.c
elf32-lm32.c

84
bfd/reloc.c
View File

@ -87,10 +87,9 @@ CODE_FRAGMENT
. {* The symbol to relocate against was undefined. *}
. bfd_reloc_undefined,
.
. {* The relocation was performed, but may not be ok - presently
. generated only when linking i960 coff files with i960 b.out
. symbols. If this type is returned, the error_message argument
. to bfd_perform_relocation will be set. *}
. {* The relocation was performed, but may not be ok. If this type is
. returned, the error_message argument to bfd_perform_relocation
. will be set. *}
. bfd_reloc_dangerous
. }
. bfd_reloc_status_type;
@ -318,8 +317,7 @@ CODE_FRAGMENT
.
. {* If this field is non null, then the supplied function is
. called rather than the normal function. This allows really
. strange relocation methods to be accommodated (e.g., i960 callj
. instructions). *}
. strange relocation methods to be accommodated. *}
. bfd_reloc_status_type (*special_function)
. (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
. bfd *, char **);
@ -1739,8 +1737,6 @@ ENUMDOC
of the relocation itself; sometimes they are relative to the start of
the section containing the relocation. It depends on the specific target.
The 24-bit relocation is used in some Intel 960 configurations.
ENUM
BFD_RELOC_32_SECREL
ENUMDOC
@ -1891,11 +1887,6 @@ displacements off that register. These relocation types are
handled specially, because the value the register will have is
decided relatively late.
ENUM
BFD_RELOC_I960_CALLJ
ENUMDOC
Reloc types used for i960/b.out.
ENUM
BFD_RELOC_NONE
ENUMX
@ -6224,73 +6215,6 @@ ENUMX
ENUMDOC
Relocs used in TLS code for CRIS.
ENUM
BFD_RELOC_860_COPY
ENUMX
BFD_RELOC_860_GLOB_DAT
ENUMX
BFD_RELOC_860_JUMP_SLOT
ENUMX
BFD_RELOC_860_RELATIVE
ENUMX
BFD_RELOC_860_PC26
ENUMX
BFD_RELOC_860_PLT26
ENUMX
BFD_RELOC_860_PC16
ENUMX
BFD_RELOC_860_LOW0
ENUMX
BFD_RELOC_860_SPLIT0
ENUMX
BFD_RELOC_860_LOW1
ENUMX
BFD_RELOC_860_SPLIT1
ENUMX
BFD_RELOC_860_LOW2
ENUMX
BFD_RELOC_860_SPLIT2
ENUMX
BFD_RELOC_860_LOW3
ENUMX
BFD_RELOC_860_LOGOT0
ENUMX
BFD_RELOC_860_SPGOT0
ENUMX
BFD_RELOC_860_LOGOT1
ENUMX
BFD_RELOC_860_SPGOT1
ENUMX
BFD_RELOC_860_LOGOTOFF0
ENUMX
BFD_RELOC_860_SPGOTOFF0
ENUMX
BFD_RELOC_860_LOGOTOFF1
ENUMX
BFD_RELOC_860_SPGOTOFF1
ENUMX
BFD_RELOC_860_LOGOTOFF2
ENUMX
BFD_RELOC_860_LOGOTOFF3
ENUMX
BFD_RELOC_860_LOPC
ENUMX
BFD_RELOC_860_HIGHADJ
ENUMX
BFD_RELOC_860_HAGOT
ENUMX
BFD_RELOC_860_HAGOTOFF
ENUMX
BFD_RELOC_860_HAPC
ENUMX
BFD_RELOC_860_HIGH
ENUMX
BFD_RELOC_860_HIGOT
ENUMX
BFD_RELOC_860_HIGOTOFF
ENUMDOC
Intel i860 Relocations.
ENUM
BFD_RELOC_OR1K_REL_26
ENUMX

22
bfd/targets.c
View File

@ -601,7 +601,6 @@ extern const bfd_target am33_elf32_linux_vec;
extern const bfd_target aout0_be_vec;
extern const bfd_target aout64_vec;
extern const bfd_target aout_vec;
extern const bfd_target aout_adobe_vec;
extern const bfd_target arc_elf32_be_vec;
extern const bfd_target arc_elf32_le_vec;
extern const bfd_target arm_aout_be_vec;
@ -634,8 +633,6 @@ extern const bfd_target arm_pei_wince_le_vec;
extern const bfd_target avr_elf32_vec;
extern const bfd_target bfin_elf32_vec;
extern const bfd_target bfin_elf32_fdpic_vec;
extern const bfd_target bout_be_vec;
extern const bfd_target bout_le_vec;
extern const bfd_target cr16_elf32_vec;
extern const bfd_target cr16c_elf32_vec;
extern const bfd_target cris_aout_vec;
@ -688,10 +685,6 @@ extern const bfd_target i386_nlm32_vec;
extern const bfd_target i386_pe_vec;
extern const bfd_target i386_pei_vec;
extern const bfd_target iamcu_elf32_vec;
extern const bfd_target i860_coff_vec;
extern const bfd_target i860_elf32_vec;
extern const bfd_target i860_elf32_le_vec;
extern const bfd_target i960_elf32_vec;
extern const bfd_target ia64_elf32_be_vec;
extern const bfd_target ia64_elf32_hpux_be_vec;
extern const bfd_target ia64_elf64_be_vec;
@ -699,8 +692,6 @@ extern const bfd_target ia64_elf64_le_vec;
extern const bfd_target ia64_elf64_hpux_be_vec;
extern const bfd_target ia64_elf64_vms_vec;
extern const bfd_target ia64_pei_vec;
extern const bfd_target icoff_be_vec;
extern const bfd_target icoff_le_vec;
extern const bfd_target ieee_vec;
extern const bfd_target ip2k_elf32_vec;
extern const bfd_target iq2000_elf32_vec;
@ -1002,7 +993,6 @@ static const bfd_target * const _bfd_target_vector[] =
which kind of a.out file it is. */
&aout_vec,
#endif
&aout_adobe_vec,
&arc_elf32_be_vec,
&arc_elf32_le_vec,
@ -1044,9 +1034,6 @@ static const bfd_target * const _bfd_target_vector[] =
&bfin_elf32_vec,
&bfin_elf32_fdpic_vec,
&bout_be_vec,
&bout_le_vec,
&cr16_elf32_vec,
&cr16c_elf32_vec,
@ -1130,12 +1117,6 @@ static const bfd_target * const _bfd_target_vector[] =
&iamcu_elf32_vec,
&i860_coff_vec,
&i860_elf32_vec,
&i860_elf32_le_vec,
&i960_elf32_vec,
#ifdef BFD64
#if 0
&ia64_elf32_be_vec,
@ -1148,9 +1129,6 @@ static const bfd_target * const _bfd_target_vector[] =
&ia64_pei_vec,
#endif
&icoff_be_vec,
&icoff_le_vec,
&ieee_vec,
&ip2k_elf32_vec,

9
binutils/ChangeLog
View File

@ -1,3 +1,12 @@
2018-04-11 Alan Modra <amodra@gmail.com>
* ieee.c: Remove i960 support.
* od-macho.c: Remove i860 support.
* readelf.c: Remove i860 and i960 support.
* testsuite/binutils-all/objcopy.exp: Likewise.
* testsuite/binutils-all/objdump.exp: Likewise.
* testsuite/lib/binutils-common.exp: Likewise.
2018-04-11 Maciej W. Rozycki <macro@mips.com>
* testsuite/lib/binutils-common.exp (is_elf_format): Also return

12
binutils/ieee.c
View File

@ -3561,12 +3561,6 @@ ieee_regno_to_genreg (bfd *abfd, int r)
r += 2;
break;
case bfd_arch_i960:
/* Stabs uses 0 to 15 for r0 to r15, 16 to 31 for g0 to g15, and
32 to 35 for fp0 to fp3. */
--r;
break;
default:
break;
}
@ -3588,12 +3582,6 @@ ieee_genreg_to_regno (bfd *abfd, int r)
r -= 2;
break;
case bfd_arch_i960:
/* Stabs uses 0 to 15 for r0 to r15, 16 to 31 for g0 to g15, and
32 to 35 for fp0 to fp3. */
++r;
break;
default:
break;
}

1
binutils/od-macho.c
View File

@ -106,7 +106,6 @@ static const bfd_mach_o_xlat_name bfd_mach_o_cpu_name[] =
{ "arm", BFD_MACH_O_CPU_TYPE_ARM },
{ "mc88000", BFD_MACH_O_CPU_TYPE_MC88000 },
{ "sparc", BFD_MACH_O_CPU_TYPE_SPARC },
{ "i860", BFD_MACH_O_CPU_TYPE_I860 },
{ "alpha", BFD_MACH_O_CPU_TYPE_ALPHA },
{ "powerpc", BFD_MACH_O_CPU_TYPE_POWERPC },
{ "powerpc_64", BFD_MACH_O_CPU_TYPE_POWERPC_64 },

18
binutils/readelf.c
View File

@ -109,8 +109,6 @@
#include "elf/hppa.h"
#include "elf/i386.h"
#include "elf/i370.h"
#include "elf/i860.h"
#include "elf/i960.h"
#include "elf/ia64.h"
#include "elf/ip2k.h"
#include "elf/lm32.h"
@ -765,7 +763,6 @@ guess_is_rela (unsigned int e_machine)
/* Targets that use REL relocations. */
case EM_386:
case EM_IAMCU:
case EM_960:
case EM_ARM:
case EM_D10V:
case EM_CYGNUS_D10V:
@ -779,7 +776,6 @@ guess_is_rela (unsigned int e_machine)
/* Targets that use RELA relocations. */
case EM_68K:
case EM_860:
case EM_AARCH64:
case EM_ADAPTEVA_EPIPHANY:
case EM_ALPHA:
@ -1275,10 +1271,6 @@ dump_relocations (Filedata * filedata,
rtype = elf_m68k_reloc_type (type);
break;
case EM_960:
rtype = elf_i960_reloc_type (type);
break;
case EM_AVR:
case EM_AVR_OLD:
rtype = elf_avr_reloc_type (type);
@ -1428,10 +1420,6 @@ dump_relocations (Filedata * filedata,
rtype = elf_cris_reloc_type (type);
break;
case EM_860:
rtype = elf_i860_reloc_type (type);
break;
case EM_X86_64:
case EM_L1OM:
case EM_K1OM:
@ -2264,7 +2252,6 @@ get_machine_name (unsigned e_machine)
case EM_68K: return "MC68000";
case EM_88K: return "MC88000";
case EM_IAMCU: return "Intel MCU";
case EM_860: return "Intel 80860";
case EM_MIPS: return "MIPS R3000";
case EM_S370: return "IBM System/370";
/* 10 */
@ -2273,7 +2260,6 @@ get_machine_name (unsigned e_machine)
case EM_PARISC: return "HPPA";
case EM_VPP550: return "Fujitsu VPP500";
case EM_SPARC32PLUS: return "Sparc v8+" ;
case EM_960: return "Intel 90860";
case EM_PPC: return "PowerPC";
/* 20 */
case EM_PPC64: return "PowerPC64";
@ -12195,10 +12181,6 @@ is_32bit_abs_reloc (Filedata * filedata, unsigned int reloc_type)
return reloc_type == 1; /* R_386_32. */
case EM_68K:
return reloc_type == 1; /* R_68K_32. */
case EM_860:
return reloc_type == 1; /* R_860_32. */
case EM_960:
return reloc_type == 2; /* R_960_32. */
case EM_AARCH64:
return (reloc_type == 258
|| reloc_type == 1); /* R_AARCH64_ABS32 || R_AARCH64_P32_ABS32 */

2
binutils/testsuite/binutils-all/objcopy.exp
View File

@ -80,7 +80,6 @@ proc objcopy_test {testname srcfile} {
setup_xfail "h8300-*-coff"
setup_xfail "h8500-*-rtems*" "h8500-*-coff"
setup_xfail "hppa*-*-*"
setup_xfail "i960-*"
setup_xfail "m68*-*-*coff" "m68*-*-hpux*" "m68*-*-lynxos*"
setup_xfail "m68*-*-sysv*" "m68*-apple-aux*"
setup_xfail "m8*-*"
@ -1091,7 +1090,6 @@ if [is_elf_format] {
|| [istarget "d10v-*"] \
|| [istarget "dlx-*"] \
|| [istarget "i*86-*"] \
|| [istarget "i960-*"] \
|| [istarget "m681*-*"] \
|| [istarget "m68hc1*-*"] \
|| ([istarget "mips*-*"] \

3
binutils/testsuite/binutils-all/objdump.exp
View File

@ -35,7 +35,7 @@ set got [binutils_run $OBJDUMP "$OBJDUMPFLAGS -i"]
set cpus_expected [list]
lappend cpus_expected aarch64 alpha am33-2 arc ARC700 ARCv2 arm cris
lappend cpus_expected d10v d30v fr30 fr500 fr550 h8 hppa i386 i860 i960 iamcu ip2022
lappend cpus_expected d10v d30v fr30 fr500 fr550 h8 hppa i386 iamcu ip2022
lappend cpus_expected m16c m32c m32r m68hc11 m68hc12 m68k m88k MCore mep c5 h1 MicroBlaze
lappend cpus_expected mips mn10200 mn10300 ms1 msp MSP430 nds32 n1h_v3 ns32k
lappend cpus_expected or1k or1knd pj powerpc pyramid riscv romp rs6000 s390 sh sparc
@ -279,7 +279,6 @@ if { ![is_elf_format] } then {
if { ![is_elf_format]
|| [istarget "hppa64*-*-hpux*"]
|| [istarget "i370-*-*"]
|| [istarget "i960-*-*"]
|| [istarget "ia64*-*-*"]
|| [istarget "mcore-*-*"]
|| [istarget "moxie-*-*"]

6
binutils/testsuite/lib/binutils-common.exp
View File

@ -59,8 +59,7 @@ proc is_elf_format {} {
|| [istarget *-*-linux*oldld*]
|| [istarget *-*-rtemscoff*]
|| [istarget h8500-*-rtems*]
|| [istarget i?86-*-freebsd\[12\].*]
|| [istarget i960-*-rtems*] } {
|| [istarget i?86-*-freebsd\[12\].*] } {
return 0
}
@ -173,7 +172,7 @@ proc is_elf64 { binary_file } {
# and Visium targets set OSABI to ELFOSABI_STANDALONE and cannot
# support STB_GNU_UNIQUE. Likewise non-EABI ARM targets set OSABI to
# ELFOSABI_ARM, and TI C6X targets to ELFOSABI_C6000_*. Finally
# rather than `bfd_elf_final_link' AM33/2.0, D30V, DLX, i960, and
# rather than `bfd_elf_final_link' AM33/2.0, D30V, DLX, and
# picoJava targets use `_bfd_generic_final_link', which does not
# support STB_GNU_UNIQUE symbol binding causing assertion failures.
#
@ -201,7 +200,6 @@ proc supports_gnu_unique {} {
if { [istarget "am33_2.0-*-*"]
|| [istarget "d30v-*-*"]
|| [istarget "dlx-*-*"]
|| [istarget "i960-*-*"]
|| [istarget "pj*-*-*"] } {
return 0
}

118
gas/ChangeLog
View File

@ -1,3 +1,121 @@
2018-04-11 Alan Modra <amodra@gmail.com>
* config/aout_gnu.h: Delete.
* config/tc-i860.c: Delete.
* config/tc-i860.h: Delete.
* config/tc-i960.c: Delete.
* config/tc-i960.h: Delete.
* doc/c-i860.texi: Delete.
* doc/c-i960.texi: Delete.
* testsuite/gas/i860/README.i860: Delete.
* testsuite/gas/i860/bitwise.d: Delete.
* testsuite/gas/i860/bitwise.s: Delete.
* testsuite/gas/i860/branch.d: Delete.
* testsuite/gas/i860/branch.s: Delete.
* testsuite/gas/i860/bte.d: Delete.
* testsuite/gas/i860/bte.s: Delete.
* testsuite/gas/i860/dir-align01.d: Delete.
* testsuite/gas/i860/dir-align01.s: Delete.
* testsuite/gas/i860/dir-intel01.d: Delete.
* testsuite/gas/i860/dir-intel01.s: Delete.
* testsuite/gas/i860/dir-intel02.d: Delete.
* testsuite/gas/i860/dir-intel02.s: Delete.
* testsuite/gas/i860/dir-intel03-err.l: Delete.
* testsuite/gas/i860/dir-intel03-err.s: Delete.
* testsuite/gas/i860/dual01.d: Delete.
* testsuite/gas/i860/dual01.s: Delete.
* testsuite/gas/i860/dual02-err.l: Delete.
* testsuite/gas/i860/dual02-err.s: Delete.
* testsuite/gas/i860/dual03.d: Delete.
* testsuite/gas/i860/dual03.s: Delete.
* testsuite/gas/i860/fldst01.d: Delete.
* testsuite/gas/i860/fldst01.s: Delete.
* testsuite/gas/i860/fldst02.d: Delete.
* testsuite/gas/i860/fldst02.s: Delete.
* testsuite/gas/i860/fldst03.d: Delete.
* testsuite/gas/i860/fldst03.s: Delete.
* testsuite/gas/i860/fldst04.d: Delete.
* testsuite/gas/i860/fldst04.s: Delete.
* testsuite/gas/i860/fldst05.d: Delete.
* testsuite/gas/i860/fldst05.s: Delete.
* testsuite/gas/i860/fldst06.d: Delete.
* testsuite/gas/i860/fldst06.s: Delete.
* testsuite/gas/i860/fldst07.d: Delete.
* testsuite/gas/i860/fldst07.s: Delete.
* testsuite/gas/i860/fldst08.d: Delete.
* testsuite/gas/i860/fldst08.s: Delete.
* testsuite/gas/i860/float01.d: Delete.
* testsuite/gas/i860/float01.s: Delete.
* testsuite/gas/i860/float02.d: Delete.
* testsuite/gas/i860/float02.s: Delete.
* testsuite/gas/i860/float03.d: Delete.
* testsuite/gas/i860/float03.s: Delete.
* testsuite/gas/i860/float04.d: Delete.
* testsuite/gas/i860/float04.s: Delete.
* testsuite/gas/i860/form.d: Delete.
* testsuite/gas/i860/form.s: Delete.
* testsuite/gas/i860/i860.exp: Delete.
* testsuite/gas/i860/iarith.d: Delete.
* testsuite/gas/i860/iarith.s: Delete.
* testsuite/gas/i860/ldst01.d: Delete.
* testsuite/gas/i860/ldst01.s: Delete.
* testsuite/gas/i860/ldst02.d: Delete.
* testsuite/gas/i860/ldst02.s: Delete.
* testsuite/gas/i860/ldst03.d: Delete.
* testsuite/gas/i860/ldst03.s: Delete.
* testsuite/gas/i860/ldst04.d: Delete.
* testsuite/gas/i860/ldst04.s: Delete.
* testsuite/gas/i860/ldst05.d: Delete.
* testsuite/gas/i860/ldst05.s: Delete.
* testsuite/gas/i860/ldst06.d: Delete.
* testsuite/gas/i860/ldst06.s: Delete.
* testsuite/gas/i860/pfam.d: Delete.
* testsuite/gas/i860/pfam.s: Delete.
* testsuite/gas/i860/pfmam.d: Delete.
* testsuite/gas/i860/pfmam.s: Delete.
* testsuite/gas/i860/pfmsm.d: Delete.
* testsuite/gas/i860/pfmsm.s: Delete.
* testsuite/gas/i860/pfsm.d: Delete.
* testsuite/gas/i860/pfsm.s: Delete.
* testsuite/gas/i860/pseudo-ops01.d: Delete.
* testsuite/gas/i860/pseudo-ops01.s: Delete.
* testsuite/gas/i860/regress01.d: Delete.
* testsuite/gas/i860/regress01.s: Delete.
* testsuite/gas/i860/shift.d: Delete.
* testsuite/gas/i860/shift.s: Delete.
* testsuite/gas/i860/simd.d: Delete.
* testsuite/gas/i860/simd.s: Delete.
* testsuite/gas/i860/system.d: Delete.
* testsuite/gas/i860/system.s: Delete.
* testsuite/gas/i860/xp.d: Delete.
* testsuite/gas/i860/xp.s: Delete.
* Makefile.am: Remove i860 and i960 support.
* configure.tgt: Likewise.
* doc/Makefile.am: Likewise.
* doc/all.texi: Likewise.
* testsuite/gas/all/gas.exp
* config/obj-coff.h: Remove i960 support.
* doc/internals.texi: Likewise.
* expr.c: Likewise.
* read.c: Likewise.
* write.c: Likewise.
* write.h: Likewise.
* testsuite/gas/lns/lns.exp: Likewise.
* testsuite/gas/symver/symver.exp: Likewise.
* config/tc-m68k.c: Remove BOUT support.
* config/tc-score.c: Likewise.
* config/tc-score7.c: Likewise.
* config/tc-sparc.c: Likewise.
* symbols.c: Likewise.
* doc/h8.texi: Likewise.
* configure.ac: Remove BOUT and i860 support.
* doc/as.texinfo: Remove BOUT, i860 and i960 support
* Makefile.in: Regenerate.
* config.in: Regenerate.
* configure: Regenerate.
* doc/Makefile.in: Regenerate.
* po/POTFILES.in: Regenerate.
2018-04-05 H.J. Lu <hongjiu.lu@intel.com>
PR gas/22318

4
gas/Makefile.am
View File

@ -150,8 +150,6 @@ TARGET_CPU_CFILES = \
config/tc-ia64.c \
config/tc-i370.c \
config/tc-i386.c \
config/tc-i860.c \
config/tc-i960.c \
config/tc-ip2k.c \
config/tc-iq2000.c \
config/tc-lm32.c \
@ -227,8 +225,6 @@ TARGET_CPU_HFILES = \
config/tc-ia64.h \
config/tc-i370.h \
config/tc-i386.h \
config/tc-i860.h \
config/tc-i960.h \
config/tc-ip2k.h \
config/tc-iq2000.h \
config/tc-lm32.h \

34
gas/Makefile.in
View File

@ -446,8 +446,6 @@ TARGET_CPU_CFILES = \
config/tc-ia64.c \
config/tc-i370.c \
config/tc-i386.c \
config/tc-i860.c \
config/tc-i960.c \
config/tc-ip2k.c \
config/tc-iq2000.c \
config/tc-lm32.c \
@ -523,8 +521,6 @@ TARGET_CPU_HFILES = \
config/tc-ia64.h \
config/tc-i370.h \
config/tc-i386.h \
config/tc-i860.h \
config/tc-i960.h \
config/tc-ip2k.h \
config/tc-iq2000.h \
config/tc-lm32.h \
@ -882,8 +878,6 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-hppa.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-i370.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-i386.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-i860.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-i960.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-ia64.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-ip2k.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-iq2000.Po@am__quote@
@ -1255,34 +1249,6 @@ tc-i386.obj: config/tc-i386.c
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-i386.obj `if test -f 'config/tc-i386.c'; then $(CYGPATH_W) 'config/tc-i386.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-i386.c'; fi`
tc-i860.o: config/tc-i860.c
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-i860.o -MD -MP -MF $(DEPDIR)/tc-i860.Tpo -c -o tc-i860.o `test -f 'config/tc-i860.c' || echo '$(srcdir)/'`config/tc-i860.c
@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-i860.Tpo $(DEPDIR)/tc-i860.Po
@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-i860.c' object='tc-i860.o' libtool=no @AMDEPBACKSLASH@
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-i860.o `test -f 'config/tc-i860.c' || echo '$(srcdir)/'`config/tc-i860.c
tc-i860.obj: config/tc-i860.c
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-i860.obj -MD -MP -MF $(DEPDIR)/tc-i860.Tpo -c -o tc-i860.obj `if test -f 'config/tc-i860.c'; then $(CYGPATH_W) 'config/tc-i860.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-i860.c'; fi`
@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-i860.Tpo $(DEPDIR)/tc-i860.Po
@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-i860.c' object='tc-i860.obj' libtool=no @AMDEPBACKSLASH@
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-i860.obj `if test -f 'config/tc-i860.c'; then $(CYGPATH_W) 'config/tc-i860.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-i860.c'; fi`
tc-i960.o: config/tc-i960.c
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-i960.o -MD -MP -MF $(DEPDIR)/tc-i960.Tpo -c -o tc-i960.o `test -f 'config/tc-i960.c' || echo '$(srcdir)/'`config/tc-i960.c
@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-i960.Tpo $(DEPDIR)/tc-i960.Po
@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-i960.c' object='tc-i960.o' libtool=no @AMDEPBACKSLASH@
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-i960.o `test -f 'config/tc-i960.c' || echo '$(srcdir)/'`config/tc-i960.c
tc-i960.obj: config/tc-i960.c
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-i960.obj -MD -MP -MF $(DEPDIR)/tc-i960.Tpo -c -o tc-i960.obj `if test -f 'config/tc-i960.c'; then $(CYGPATH_W) 'config/tc-i960.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-i960.c'; fi`
@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-i960.Tpo $(DEPDIR)/tc-i960.Po
@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-i960.c' object='tc-i960.obj' libtool=no @AMDEPBACKSLASH@
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-i960.obj `if test -f 'config/tc-i960.c'; then $(CYGPATH_W) 'config/tc-i960.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-i960.c'; fi`
tc-ip2k.o: config/tc-ip2k.c
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-ip2k.o -MD -MP -MF $(DEPDIR)/tc-ip2k.Tpo -c -o tc-ip2k.o `test -f 'config/tc-ip2k.c' || echo '$(srcdir)/'`config/tc-ip2k.c
@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-ip2k.Tpo $(DEPDIR)/tc-ip2k.Po

3
gas/config.in
View File

@ -238,9 +238,6 @@
/* a.out support? */
#undef OBJ_MAYBE_AOUT
/* b.out support? */
#undef OBJ_MAYBE_BOUT
/* COFF support? */
#undef OBJ_MAYBE_COFF

451
gas/config/aout_gnu.h
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@ -1,451 +0,0 @@
/* This file is aout_gnu.h
Copyright (C) 1987-2018 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to
the Free Software Foundation, 51 Franklin Street - Fifth Floor,
Boston, MA 02110-1301, USA. */
#ifndef __A_OUT_GNU_H__
#define __A_OUT_GNU_H__
/* There are two main flavours of a.out, one which uses the standard
relocations, and one which uses extended relocations.
Today, the extended reloc uses are
TC_SPARC
each must define the enum reloc_type
*/
#if defined(TC_SPARC)
enum reloc_type
{
RELOC_8, RELOC_16, RELOC_32,/* simple relocations */
RELOC_DISP8, RELOC_DISP16, RELOC_DISP32, /* pc-rel displacement */
RELOC_WDISP30, RELOC_WDISP22,
RELOC_HI22, RELOC_22,
RELOC_13, RELOC_LO10,
RELOC_SFA_BASE, RELOC_SFA_OFF13,
RELOC_BASE10, RELOC_BASE13, RELOC_BASE22, /* P.I.C. (base-relative) */
RELOC_PC10, RELOC_PC22, /* for some sort of pc-rel P.I.C. (?) */
RELOC_JMP_TBL, /* P.I.C. jump table */
RELOC_SEGOFF16, /* reputedly for shared libraries somehow */
RELOC_GLOB_DAT, RELOC_JMP_SLOT, RELOC_RELATIVE,
RELOC_10, RELOC_11,
RELOC_WDISP2_14,
RELOC_WDISP19,
RELOC_HHI22,
RELOC_HLO10,
/* 29K relocation types */
RELOC_JUMPTARG, RELOC_CONST, RELOC_CONSTH,
RELOC_WDISP14, RELOC_WDISP21,
NO_RELOC
};
#define USE_EXTENDED_RELOC 1
#else
#define USE_EXTENDED_RELOC 0
#endif /* TC_SPARC */
#define __GNU_EXEC_MACROS__
#ifndef __STRUCT_EXEC_OVERRIDE__
/* This is the layout on disk of a Unix V7, Berkeley, SunOS, Vax Ultrix
"struct exec". Don't assume that on this machine, the "struct exec"
will lay out the same sizes or alignments. */
struct exec_bytes
{
unsigned char a_info[4];
unsigned char a_text[4];
unsigned char a_data[4];
unsigned char a_bss[4];
unsigned char a_syms[4];
unsigned char a_entry[4];
unsigned char a_trsize[4];
unsigned char a_drsize[4];
};
/* How big the "struct exec" is on disk */
#define EXEC_BYTES_SIZE (8 * 4)
/* This is the layout in memory of a "struct exec" while we process it. */
struct exec
{
unsigned long a_info; /* Use macros N_MAGIC, etc for access */
unsigned a_text; /* length of text, in bytes */
unsigned a_data; /* length of data, in bytes */
unsigned a_bss; /* length of uninitialized data area for file, in bytes */
unsigned a_syms; /* length of symbol table data in file, in bytes */
unsigned a_entry; /* start address */
unsigned a_trsize; /* length of relocation info for text, in bytes */
unsigned a_drsize; /* length of relocation info for data, in bytes */
};
#endif /* __STRUCT_EXEC_OVERRIDE__ */
/* these go in the N_MACHTYPE field */
/* These symbols could be defined by code from Suns...punt 'em */
#undef M_UNKNOWN
#undef M_68010
#undef M_68020
#undef M_SPARC
enum machine_type
{
M_UNKNOWN = 0,
M_68010 = 1,
M_68020 = 2,
M_SPARC = 3,
/* skip a bunch so we don't run into any of sun's numbers */
M_386 = 100,
M_29K = 101,
M_RS6000 = 102, /* IBM RS/6000 */
M_VAX4K_NETBSD = 150,
/* HP/BSD formats */
M_HP200 = 200, /* hp200 (68010) BSD binary */
M_HP300 = 300, /* hp300 (68020+68881) BSD binary */
M_HPUX23 = 0x020C /* hp200/300 HPUX binary */
};
#define N_MAGIC(execp) ((execp)->a_info & 0xffff)
#define N_MACHTYPE(execp) ((enum machine_type)(((execp)->a_info >> 16) & 0xff))
#define N_FLAGS(execp) (((execp)->a_info >> 24) & 0xff)
#define N_SET_INFO(execp, magic, type, flags) \
((execp)->a_info = ((magic) & 0xffff) \
| (((int)(type) & 0xff) << 16) \
| (((flags) & 0xff) << 24))
#define N_SET_MAGIC(execp, magic) \
((execp)->a_info = (((execp)->a_info & 0xffff0000) | ((magic) & 0xffff)))
#define N_SET_MACHTYPE(execp, machtype) \
((execp)->a_info = \
((execp)->a_info & 0xff00ffff) | ((((int) (machtype)) & 0xff) << 16))
#define N_SET_FLAGS(execp, flags) \
((execp)->a_info = \
((execp)->a_info & 0x00ffffff) | (((flags) & 0xff) << 24))
/* Code indicating object file or impure executable. */
#ifndef OMAGIC
#define OMAGIC 0407
#endif
/* Code indicating pure executable. */
#define NMAGIC 0410
/* Code indicating demand-paged executable. */
#define ZMAGIC 0413
/* Virtual Address of text segment from the a.out file. For OMAGIC,
(almost always "unlinked .o's" these days), should be zero.
For linked files, should reflect reality if we know it. */
#ifndef N_TXTADDR
#define N_TXTADDR(x) (N_MAGIC(x)==OMAGIC? 0 : TEXT_START_ADDR)
#endif
#ifndef N_BADMAG
#define N_BADMAG(x) (N_MAGIC(x) != OMAGIC \
&& N_MAGIC(x) != NMAGIC \
&& N_MAGIC(x) != ZMAGIC)
#endif
/* By default, segment size is constant. But on some machines, it can
be a function of the a.out header (e.g. machine type). */
#ifndef N_SEGSIZE
#define N_SEGSIZE(x) SEGMENT_SIZE
#endif
/* This complexity is for encapsulated COFF support */
#ifndef _N_HDROFF
#define _N_HDROFF(x) (N_SEGSIZE(x) - sizeof (struct exec))
#endif
#ifndef N_TXTOFF
#define N_TXTOFF(x) (N_MAGIC(x) == ZMAGIC ? \
_N_HDROFF((x)) + sizeof (struct exec) : \
sizeof (struct exec))
#endif
#ifndef N_DATOFF
#define N_DATOFF(x) ( N_TXTOFF(x) + (x)->a_text )
#endif
#ifndef N_TRELOFF
#define N_TRELOFF(x) ( N_DATOFF(x) + (x)->a_data )
#endif
#ifndef N_DRELOFF
#define N_DRELOFF(x) ( N_TRELOFF(x) + (x)->a_trsize )
#endif
#ifndef N_SYMOFF
#define N_SYMOFF(x) ( N_DRELOFF(x) + (x)->a_drsize )
#endif
#ifndef N_STROFF
#define N_STROFF(x) ( N_SYMOFF(x) + (x)->a_syms )
#endif
/* Address of text segment in memory after it is loaded. */
#ifndef N_TXTADDR
#define N_TXTADDR(x) 0
#endif
#ifndef N_DATADDR
#define N_DATADDR(x) \
(N_MAGIC(x)==OMAGIC? (N_TXTADDR(x)+(x)->a_text) \
: (N_SEGSIZE(x) + ((N_TXTADDR(x)+(x)->a_text-1) & ~(N_SEGSIZE(x)-1))))
#endif
/* Address of bss segment in memory after it is loaded. */
#define N_BSSADDR(x) (N_DATADDR(x) + (x)->a_data)
struct nlist
{
union
{
char *n_name;
struct nlist *n_next;
long n_strx;
}
n_un;
unsigned char n_type;
char n_other;
short n_desc;
unsigned long n_value;
};
#define N_UNDF 0
#define N_ABS 2
#define N_TEXT 4
#define N_DATA 6
#define N_BSS 8
#define N_COMM 0x12 /* common (visible in shared lib commons) */
#define N_FN 0x1F /* File name of a .o file */
/* Note: N_EXT can only usefully be OR-ed with N_UNDF, N_ABS, N_TEXT,
N_DATA, or N_BSS. When the low-order bit of other types is set,
(e.g. N_WARNING versus N_FN), they are two different types. */
#define N_EXT 1
#define N_TYPE 036
#define N_STAB 0340
/* The following type indicates the definition of a symbol as being
an indirect reference to another symbol. The other symbol
appears as an undefined reference, immediately following this symbol.
Indirection is asymmetrical. The other symbol's value will be used
to satisfy requests for the indirect symbol, but not vice versa.
If the other symbol does not have a definition, libraries will
be searched to find a definition. */
#define N_INDR 0xa
/* The following symbols refer to set elements.
All the N_SET[ATDB] symbols with the same name form one set.
Space is allocated for the set in the text section, and each set
element's value is stored into one word of the space.
The first word of the space is the length of the set (number of elements).
The address of the set is made into an N_SETV symbol
whose name is the same as the name of the set.
This symbol acts like a N_DATA global symbol
in that it can satisfy undefined external references. */
/* These appear as input to LD, in a .o file. */
#define N_SETA 0x14 /* Absolute set element symbol */
#define N_SETT 0x16 /* Text set element symbol */
#define N_SETD 0x18 /* Data set element symbol */
#define N_SETB 0x1A /* Bss set element symbol */
/* This is output from LD. */
#define N_SETV 0x1C /* Pointer to set vector in data area. */
/* Warning symbol. The text gives a warning message, the next symbol
in the table will be undefined. When the symbol is referenced, the
message is printed. */
#define N_WARNING 0x1e
/* Weak symbols. These are a GNU extension to the a.out format. The
semantics are those of ELF weak symbols. Weak symbols are always
externally visible. The N_WEAK? values are squeezed into the
available slots. The value of a N_WEAKU symbol is 0. The values
of the other types are the definitions. */
#define N_WEAKU 0x0d /* Weak undefined symbol. */
#define N_WEAKA 0x0e /* Weak absolute symbol. */
#define N_WEAKT 0x0f /* Weak text symbol. */
#define N_WEAKD 0x10 /* Weak data symbol. */
#define N_WEAKB 0x11 /* Weak bss symbol. */
/* This structure describes a single relocation to be performed.
The text-relocation section of the file is a vector of these structures,
all of which apply to the text section.
Likewise, the data-relocation section applies to the data section. */
/* The following enum and struct were borrowed from SunOS's
/usr/include/sun4/a.out.h and extended to handle
other machines. It is currently used on SPARC.
reloc_ext_bytes is how it looks on disk. reloc_info_extended is
how we might process it on a native host. */
#if USE_EXTENDED_RELOC
struct reloc_ext_bytes
{
unsigned char r_address[4];
unsigned char r_index[3];
unsigned char r_bits[1];
unsigned char r_addend[4];
};
#define RELOC_EXT_BITS_EXTERN_BIG 0x80
#define RELOC_EXT_BITS_EXTERN_LITTLE 0x01
#define RELOC_EXT_BITS_TYPE_BIG 0x1F
#define RELOC_EXT_BITS_TYPE_SH_BIG 0
#define RELOC_EXT_BITS_TYPE_LITTLE 0xF8
#define RELOC_EXT_BITS_TYPE_SH_LITTLE 3
#define RELOC_EXT_SIZE 12 /* Bytes per relocation entry */
struct reloc_info_extended
{
unsigned long r_address;
unsigned int r_index:24;
# define r_symbolnum r_index
unsigned r_extern:1;
unsigned:2;
/* RS/6000 compiler does not support enum bitfield
enum reloc_type r_type:5; */
enum reloc_type r_type;
long int r_addend;
};
#else
/* The standard, old-fashioned, Berkeley compatible relocation struct */
#ifdef TC_I860
/* NOTE: three bits max, see struct reloc_info_i860.r_type */
enum i860_reloc_type
{
NO_RELOC = 0, BRADDR, LOW0, LOW1, LOW2, LOW3, LOW4, SPLIT0, SPLIT1, SPLIT2, RELOC_32,
};
typedef enum i860_reloc_type reloc_type;
/* NOTE: two bits max, see reloc_info_i860.r_type */
enum highlow_type
{
NO_SPEC = 0, PAIR, HIGH, HIGHADJ,
};
struct reloc_info_i860
{
unsigned long r_address;
/*
* Using bit fields here is a bad idea because the order is not portable. :-(
*/
unsigned int r_symbolnum:24;
unsigned int r_pcrel:1;
unsigned int r_extern:1;
/* combining the two field simplifies the argument passing in "new_fix()" */
/* and is compatible with the existing Sparc #ifdef's */
/* r_type: highlow_type - bits 5,4; reloc_type - bits 3-0 */
unsigned int r_type:6;
long r_addend;
};
#endif /* TC_I860 */
struct reloc_std_bytes
{
unsigned char r_address[4];
unsigned char r_index[3];
unsigned char r_bits[1];
};
#define RELOC_STD_BITS_PCREL_BIG 0x80
#define RELOC_STD_BITS_PCREL_LITTLE 0x01
#define RELOC_STD_BITS_LENGTH_BIG 0x60
#define RELOC_STD_BITS_LENGTH_SH_BIG 5 /* To shift to units place */
#define RELOC_STD_BITS_LENGTH_LITTLE 0x06
#define RELOC_STD_BITS_LENGTH_SH_LITTLE 1
#define RELOC_STD_BITS_EXTERN_BIG 0x10
#define RELOC_STD_BITS_EXTERN_LITTLE 0x08
#define RELOC_STD_BITS_BASEREL_BIG 0x08
#define RELOC_STD_BITS_BASEREL_LITTLE 0x08
#define RELOC_STD_BITS_JMPTABLE_BIG 0x04
#define RELOC_STD_BITS_JMPTABLE_LITTLE 0x04
#define RELOC_STD_BITS_RELATIVE_BIG 0x02
#define RELOC_STD_BITS_RELATIVE_LITTLE 0x02
#define RELOC_STD_SIZE 8 /* Bytes per relocation entry */
#endif /* USE_EXTENDED_RELOC */
#ifndef CUSTOM_RELOC_FORMAT
struct relocation_info
{
/* Address (within segment) to be relocated. */
int r_address;
/* The meaning of r_symbolnum depends on r_extern. */
unsigned int r_symbolnum:24;
/* Nonzero means value is a pc-relative offset
and it should be relocated for changes in its own address
as well as for changes in the symbol or section specified. */
unsigned int r_pcrel:1;
/* Length (as exponent of 2) of the field to be relocated.
Thus, a value of 2 indicates 1<<2 bytes. */
unsigned int r_length:2;
/* 1 => relocate with value of symbol.
r_symbolnum is the index of the symbol
in file's the symbol table.
0 => relocate with the address of a segment.
r_symbolnum is N_TEXT, N_DATA, N_BSS or N_ABS
(the N_EXT bit may be set also, but signifies nothing). */
unsigned int r_extern:1;
/* The next three bits are for SunOS shared libraries, and seem to
be undocumented. */
#ifdef TC_NS32K
unsigned int r_bsr:1;
unsigned int r_disp:2;
#else
unsigned int r_baserel:1; /* Linkage table relative */
unsigned int r_jmptable:1; /* pc-relative to jump table */
unsigned int r_relative:1; /* "relative relocation" */
#endif /* TC_NS32K */
/* unused */
unsigned int r_pad:1; /* Padding -- set to zero */
};
#endif /* CUSTOM_RELOC_FORMAT */
#endif /* __A_OUT_GNU_H__ */
/* end of aout_gnu.h */

38
gas/config/obj-coff.h
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@ -75,11 +75,6 @@
#endif
#endif
#ifdef TC_I960
#include "coff/i960.h"
#define TARGET_FORMAT "coff-Intel-little"
#endif
#ifdef TC_Z80
#include "coff/z80.h"
#define TARGET_FORMAT "coff-z80"
@ -168,11 +163,6 @@
/* Alter the field names, for now, until we've fixed up the other
references to use the new name. */
#ifdef TC_I960
#define TC_SYMFIELD_TYPE symbolS *
#define sy_tc bal
#endif
#define OBJ_SYMFIELD_TYPE unsigned long
#define sy_obj sy_obj_flags
@ -224,17 +214,7 @@
/* Internal use only definitions. SF_ stands for symbol flags.
These values can be assigned to sy_symbol.ost_flags field of a symbolS.
You'll break i960 if you shift the SYSPROC bits anywhere else. for
more on the balname/callname hack, see tc-i960.h. b.out is done
differently. */
#define SF_I960_MASK 0x000001ff /* Bits 0-8 are used by the i960 port. */
#define SF_SYSPROC 0x0000003f /* bits 0-5 are used to store the sysproc number. */
#define SF_IS_SYSPROC 0x00000040 /* bit 6 marks symbols that are sysprocs. */
#define SF_BALNAME 0x00000080 /* bit 7 marks BALNAME symbols. */
#define SF_CALLNAME 0x00000100 /* bit 8 marks CALLNAME symbols. */
These values can be assigned to sy_symbol.ost_flags field of a symbolS. */
#define SF_NORMAL_MASK 0x0000ffff /* bits 12-15 are general purpose. */
@ -269,11 +249,6 @@
#define SF_GET_TAGGED(s) (SF_GET (s) & SF_TAGGED)
#define SF_GET_TAG(s) (SF_GET (s) & SF_TAG)
#define SF_GET_GET_SEGMENT(s) (SF_GET (s) & SF_GET_SEGMENT)
#define SF_GET_I960(s) (SF_GET (s) & SF_I960_MASK) /* Used by i960. */
#define SF_GET_BALNAME(s) (SF_GET (s) & SF_BALNAME) /* Used by i960. */
#define SF_GET_CALLNAME(s) (SF_GET (s) & SF_CALLNAME) /* Used by i960. */
#define SF_GET_IS_SYSPROC(s) (SF_GET (s) & SF_IS_SYSPROC) /* Used by i960. */
#define SF_GET_SYSPROC(s) (SF_GET (s) & SF_SYSPROC) /* Used by i960. */
/* Modifiers. */
#define SF_SET(s,v) (SF_GET (s) = (v))
@ -290,11 +265,6 @@
#define SF_SET_TAGGED(s) (SF_GET (s) |= SF_TAGGED)
#define SF_SET_TAG(s) (SF_GET (s) |= SF_TAG)
#define SF_SET_GET_SEGMENT(s) (SF_GET (s) |= SF_GET_SEGMENT)
#define SF_SET_I960(s,v) (SF_GET (s) |= ((v) & SF_I960_MASK)) /* Used by i960. */
#define SF_SET_BALNAME(s) (SF_GET (s) |= SF_BALNAME) /* Used by i960. */
#define SF_SET_CALLNAME(s) (SF_GET (s) |= SF_CALLNAME) /* Used by i960. */
#define SF_SET_IS_SYSPROC(s) (SF_GET (s) |= SF_IS_SYSPROC) /* Used by i960. */
#define SF_SET_SYSPROC(s,v) (SF_GET (s) |= ((v) & SF_SYSPROC)) /* Used by i960. */
/* Line number handling. */
@ -330,12 +300,6 @@ extern symbolS *coff_last_function;
/* Sanity check. */
#ifdef TC_I960
#ifndef C_LEAFSTAT
hey ! Where is the C_LEAFSTAT definition ? i960 - coff support is depending on it.
#endif /* no C_LEAFSTAT */
#endif /* TC_I960 */
extern const pseudo_typeS coff_pseudo_table[];
#ifndef obj_pop_insert

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gas/config/tc-i860.c
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95
gas/config/tc-i860.h
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@ -1,95 +0,0 @@
/* tc-i860.h -- Header file for the i860.
Copyright (C) 1991-2018 Free Software Foundation, Inc.
Brought back from the dead and completely reworked
by Jason Eckhardt <jle@cygnus.com>.
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with GAS; see the file COPYING. If not, write to the Free Software
Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
#ifndef TC_I860
#define TC_I860 1
enum i860_fix_info
{
OP_NONE = 0x00000,
OP_IMM_U5 = 0x00001,
OP_IMM_S16 = 0x00002,
OP_IMM_U16 = 0x00004,
OP_IMM_SPLIT16 = 0x00008,
OP_IMM_BR26 = 0x00010,
OP_IMM_BR16 = 0x00020,
OP_ENCODE1 = 0x00040,
OP_ENCODE2 = 0x00080,
OP_ENCODE3 = 0x00100,
OP_SEL_HA = 0x00200,
OP_SEL_H = 0x00400,
OP_SEL_L = 0x00800,
OP_SEL_GOT = 0x01000,
OP_SEL_GOTOFF = 0x02000,
OP_SEL_PLT = 0x04000,
OP_ALIGN2 = 0x08000,
OP_ALIGN4 = 0x10000,
OP_ALIGN8 = 0x20000,
OP_ALIGN16 = 0x40000
};
/* Set the endianness we are using. Default to little endian. */
#ifndef TARGET_BYTES_BIG_ENDIAN
#define TARGET_BYTES_BIG_ENDIAN 0
#endif
/* Whether or not the target is big endian. */
extern int target_big_endian;
/* BFD target architecture. */
#define TARGET_ARCH bfd_arch_i860
/* The target BFD format. */
#ifdef OBJ_ELF
#define TARGET_FORMAT (target_big_endian ? "elf32-i860" : "elf32-i860-little")
#else
#error i860 GAS currently supports only the ELF object format
#endif
#define WORKING_DOT_WORD
#define DIFF_EXPR_OK
/* Permit temporary numeric labels. */
#define LOCAL_LABELS_FB 1
#define LISTING_HEADER "GAS for i860"
#define md_convert_frag(b,s,f) abort ()
/* Values passed to md_apply_fix don't include the symbol value. */
#define MD_APPLY_SYM_VALUE(FIX) 0
/* No shared lib support, so we don't need to ensure externally
visible symbols can be overridden. */
#define EXTERN_FORCE_RELOC 0
/* Bits for post-processing of a user defined label to check if
it has a double colon (Intel syntax only). */
extern void i860_check_label (symbolS *labelsym);
#define tc_check_label(ls) i860_check_label (ls)
/* Bits for filling in rs_align_code fragments with NOPs. */
extern void i860_handle_align (struct frag *);
#define HANDLE_ALIGN(fragp) i860_handle_align (fragp)
#define MAX_MEM_FOR_RS_ALIGN_CODE (3 + 4 + 4)
#endif /* TC_I860 */

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gas/config/tc-i960.c
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gas/config/tc-i960.h
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@ -1,185 +0,0 @@
/* tc-i960.h - Basic 80960 instruction formats.
Copyright (C) 1989-2018 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as
published by the Free Software Foundation; either version 3,
or (at your option) any later version.
GAS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
#ifndef TC_I960
#define TC_I960 1
#ifdef OBJ_ELF
#define TARGET_FORMAT "elf32-i960"
#define TARGET_ARCH bfd_arch_i960
#endif
#define TARGET_BYTES_BIG_ENDIAN 0
#define WORKING_DOT_WORD
/*
* The 'COJ' instructions are actually COBR instructions with the 'b' in
* the mnemonic replaced by a 'j'; they are ALWAYS "de-optimized" if necessary:
* if the displacement will not fit in 13 bits, the assembler will replace them
* with the corresponding compare and branch instructions.
*
* All of the 'MEMn' instructions are the same format; the 'n' in the name
* indicates the default index scale factor (the size of the datum operated on).
*
* The FBRA formats are not actually an instruction format. They are the
* "convenience directives" for branching on floating-point comparisons,
* each of which generates 2 instructions (a 'bno' and one other branch).
*
* The CALLJ format is not actually an instruction format. It indicates that
* the instruction generated (a CTRL-format 'call') should have its relocation
* specially flagged for link-time replacement with a 'bal' or 'calls' if
* appropriate.
*/
/* tailor gas */
#define LOCAL_LABELS_FB 1
#define BITFIELD_CONS_EXPRESSIONS
/* tailor the coff format */
#define COFF_MAGIC I960ROMAGIC
#define OBJ_COFF_MAX_AUXENTRIES (2)
/* MEANING OF 'n_other' in the symbol record.
*
* If non-zero, the 'n_other' fields indicates either a leaf procedure or
* a system procedure, as follows:
*
* 1 <= n_other <= 32 :
* The symbol is the entry point to a system procedure.
* 'n_value' is the address of the entry, as for any other
* procedure. The system procedure number (which can be used in
* a 'calls' instruction) is (n_other-1). These entries come from
* '.sysproc' directives.
*
* n_other == N_CALLNAME
* the symbol is the 'call' entry point to a leaf procedure.
* The *next* symbol in the symbol table must be the corresponding
* 'bal' entry point to the procedure (see following). These
* entries come from '.leafproc' directives in which two different
* symbols are specified (the first one is represented here).
*
*
* n_other == N_BALNAME
* the symbol is the 'bal' entry point to a leaf procedure.
* These entries result from '.leafproc' directives in which only
* one symbol is specified, or in which the same symbol is
* specified twice.
*
* Note that an N_CALLNAME entry *must* have a corresponding N_BALNAME entry,
* but not every N_BALNAME entry must have an N_CALLNAME entry.
*/
#define N_CALLNAME ((char)-1)
#define N_BALNAME ((char)-2)
/* i960 uses a custom relocation record. */
/* let obj-aout.h know */
#define CUSTOM_RELOC_FORMAT 1
/* let aout_gnu.h know */
#define N_RELOCATION_INFO_DECLARED 1
struct relocation_info
{
int r_address; /* File address of item to be relocated */
unsigned
r_index:24, /* Index of symbol on which relocation is based*/
r_pcrel:1, /* 1 => relocate PC-relative; else absolute
* On i960, pc-relative implies 24-bit
* address, absolute implies 32-bit.
*/
r_length:2, /* Number of bytes to relocate:
* 0 => 1 byte
* 1 => 2 bytes
* 2 => 4 bytes -- only value used for i960
*/
r_extern:1, r_bsr:1, /* Something for the GNU NS32K assembler */
r_disp:1, /* Something for the GNU NS32K assembler */
r_callj:1, /* 1 if relocation target is an i960 'callj' */
nuthin:1; /* Unused */
};
/* No shared lib support, so we don't need to ensure externally
visible symbols can be overridden. */
#define EXTERN_FORCE_RELOC 0
/* Makes no sense to use the difference of 2 arbitrary symbols
as the target of a call instruction. */
#define TC_FORCE_RELOCATION_SUB_SAME(FIX, SEG) \
(GENERIC_FORCE_RELOCATION_SUB_SAME (FIX, SEG) \
|| (FIX)->fx_tcbit \
|| TC_FORCE_RELOCATION (FIX))
/* reloc_callj() may replace a 'call' with a 'calls' or a
'bal', in which cases it modifies *fixP as appropriate.
In the case of a 'calls', no further work is required. */
extern int reloc_callj (struct fix *);
#define TC_FORCE_RELOCATION_ABS(FIX) \
(TC_FORCE_RELOCATION (FIX) \
|| reloc_callj (FIX))
#define TC_FORCE_RELOCATION_LOCAL(FIX) \
(GENERIC_FORCE_RELOCATION_LOCAL (FIX) \
|| reloc_callj (FIX))
#ifdef OBJ_COFF
/* We store the bal information in the sy_tc field. */
#define TC_SYMFIELD_TYPE symbolS *
#endif
extern int i960_validate_fix (struct fix *, segT);
#define TC_VALIDATE_FIX(FIX,SEGTYPE,LABEL) \
if (!i960_validate_fix (FIX, SEGTYPE)) goto LABEL
#define tc_fix_adjustable(FIX) ((FIX)->fx_bsr == 0)
#ifndef OBJ_ELF
/* Values passed to md_apply_fix sometimes include symbol values. */
#define MD_APPLY_SYM_VALUE(FIX) tc_fix_adjustable (FIX)
#else
/* Values passed to md_apply_fix don't include the symbol value. */
#define MD_APPLY_SYM_VALUE(FIX) 0
#endif
extern void brtab_emit (void);
#define md_end() brtab_emit ()
extern void tc_set_bal_of_call (symbolS *, symbolS *);
extern struct symbol *tc_get_bal_of_call (symbolS *);
extern void i960_handle_align (struct frag *);
#define HANDLE_ALIGN(FRAG) i960_handle_align (FRAG)
#define NO_RELOC -1
#define md_operand(x)
extern const struct relax_type md_relax_table[];
#define TC_GENERIC_RELAX_TABLE md_relax_table
#define LINKER_RELAXING_SHRINKS_ONLY
#define TC_FIX_TYPE struct { unsigned bsr : 1; }
#define fx_bsr tc_fix_data.bsr
#define TC_INIT_FIX_DATA(F) ((F)->tc_fix_data.bsr = 0)
#endif

4
gas/config/tc-m68k.c
View File

@ -5405,7 +5405,7 @@ md_estimate_size_before_relax (fragS *fragP, segT segment)
return md_relax_table[fragP->fr_subtype].rlx_length;
}
#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
#if defined(OBJ_AOUT)
/* the bit-field entries in the relocation_info struct plays hell
with the byte-order problems of cross-assembly. So as a hack,
I added this mach. dependent ri twiddler. Ugly, but it gets
@ -5433,7 +5433,7 @@ md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
#endif
#endif /* OBJ_AOUT or OBJ_BOUT */
#endif /* OBJ_AOUT */
#ifndef WORKING_DOT_WORD
int md_short_jump_size = 4;

3
gas/config/tc-score.c
View File

@ -6217,8 +6217,7 @@ s3_s_score_lcomm (int bytes_p)
*p = c;
if (
#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT) \
|| defined (OBJ_BOUT) || defined (OBJ_MAYBE_BOUT))
#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
#ifdef BFD_ASSEMBLER
(OUTPUT_FLAVOR != bfd_target_aout_flavour
|| (S_GET_OTHER (symbolP) == 0 && S_GET_DESC (symbolP) == 0)) &&

3
gas/config/tc-score7.c
View File

@ -6077,8 +6077,7 @@ s7_s_score_lcomm (int bytes_p)
*p = c;
if (
#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT) \
|| defined (OBJ_BOUT) || defined (OBJ_MAYBE_BOUT))
#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
#ifdef BFD_ASSEMBLER
(OUTPUT_FLAVOR != bfd_target_aout_flavour
|| (S_GET_OTHER (symbolP) == 0 && S_GET_DESC (symbolP) == 0)) &&

4
gas/config/tc-sparc.c
View File

@ -365,10 +365,6 @@ sparc_target_format (void)
#endif
#endif
#ifdef OBJ_BOUT
return "b.out.big";
#endif
#ifdef OBJ_COFF
#ifdef TE_LYNX
return "coff-sparc-lynx";

10
gas/configure vendored
View File

@ -11936,7 +11936,7 @@ case "${host}" in
esac
#We need this for the host. BOUT header is in host order.
#We need this for the host.
{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether byte ordering is bigendian" >&5
$as_echo_n "checking whether byte ordering is bigendian... " >&6; }
if test "${ac_cv_c_bigendian+set}" = set; then :
@ -12250,11 +12250,6 @@ $as_echo "#define STRICTCOFF 1" >>confdefs.h
fi
;;
i860-*-*)
{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: GAS support for ${generic_target} is preliminary and a work in progress" >&5
$as_echo "$as_me: WARNING: GAS support for ${generic_target} is preliminary and a work in progress" >&2;}
;;
microblaze*)
;;
@ -12862,9 +12857,6 @@ if test `set . $formats ; shift ; echo $#` -gt 1 ; then
case $fmt in
aout)
$as_echo "#define OBJ_MAYBE_AOUT 1" >>confdefs.h
;;
bout)
$as_echo "#define OBJ_MAYBE_BOUT 1" >>confdefs.h
;;
coff)
$as_echo "#define OBJ_MAYBE_COFF 1" >>confdefs.h

7
gas/configure.ac
View File

@ -141,7 +141,7 @@ case "${host}" in
esac
AC_SUBST(GDBINIT)
#We need this for the host. BOUT header is in host order.
#We need this for the host.
AC_C_BIGENDIAN
te_file=generic
@ -213,10 +213,6 @@ for this_target in $target $canon_targets ; do
fi
;;
i860-*-*)
AC_MSG_WARN(GAS support for ${generic_target} is preliminary and a work in progress)
;;
microblaze*)
;;
@ -737,7 +733,6 @@ if test `set . $formats ; shift ; echo $#` -gt 1 ; then
for fmt in $formats ; do
case $fmt in
aout) AC_DEFINE(OBJ_MAYBE_AOUT, 1, [a.out support?]) ;;
bout) AC_DEFINE(OBJ_MAYBE_BOUT, 1, [b.out support?]) ;;
coff) AC_DEFINE(OBJ_MAYBE_COFF, 1, [COFF support?]) ;;
ecoff) AC_DEFINE(OBJ_MAYBE_ECOFF, 1, [ECOFF support?]) ;;
elf) AC_DEFINE(OBJ_MAYBE_ELF, 1, [ELF support?]) ;;

4
gas/configure.tgt
View File

@ -292,10 +292,6 @@ case ${generic_target} in
i386-*-rdos*) fmt=elf ;;
i386-*-darwin*) fmt=macho ;;
i860-*-*) fmt=elf endian=little ;;
i960-*-elf*) fmt=elf ;;
ia16-*-elf*) fmt=elf ;;
ia64-*-elf*) fmt=elf ;;

2
gas/doc/Makefile.am
View File

@ -60,8 +60,6 @@ CPU_DOCS = \
c-hppa.texi \
c-i370.texi \
c-i386.texi \
c-i860.texi \
c-i960.texi \
c-ip2k.texi \
c-lm32.texi \
c-m32c.texi \

2
gas/doc/Makefile.in
View File

@ -335,8 +335,6 @@ CPU_DOCS = \
c-hppa.texi \
c-i370.texi \
c-i386.texi \
c-i860.texi \
c-i960.texi \
c-ip2k.texi \
c-lm32.texi \
c-m32c.texi \

2
gas/doc/all.texi
View File

@ -39,8 +39,6 @@
@set HPPA
@set I370
@set I80386
@set I860
@set I960
@set IA64
@set IP2K
@set LM32

278
gas/doc/as.texinfo
View File

@ -32,7 +32,7 @@
@set COFF-ELF
@end ifset
@ifset AOUT
@set aout-bout
@set aout
@end ifset
@ifset ARM/Thumb
@set ARM
@ -40,9 +40,6 @@
@ifset Blackfin
@set Blackfin
@end ifset
@ifset BOUT
@set aout-bout
@end ifset
@ifset H8/300
@set H8
@end ifset
@ -337,14 +334,6 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
[@b{--32}|@b{--x32}|@b{--64}] [@b{-n}]
[@b{-march}=@var{CPU}[+@var{EXTENSION}@dots{}]] [@b{-mtune}=@var{CPU}]
@end ifset
@ifset I960
@emph{Target i960 options:}
@c see md_parse_option in tc-i960.c
[@b{-ACA}|@b{-ACA_A}|@b{-ACB}|@b{-ACC}|@b{-AKA}|@b{-AKB}|
@b{-AKC}|@b{-AMC}]
[@b{-b}] [@b{-no-relax}]
@end ifset
@ifset IA64
@emph{Target IA-64 options:}
@ -1069,24 +1058,6 @@ an i386 processor.
@end ifset
@c man begin OPTIONS
@ifset I960
The following options are available when @value{AS} is configured for the
Intel 80960 processor.
@table @gcctabopt
@item -ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC
Specify which variant of the 960 architecture is the target.
@item -b
Add code to collect statistics about branches taken.
@item -no-relax
Do not alter compare-and-branch instructions for long displacements;
error if necessary.
@end table
@end ifset
@ifset IP2K
The following options are available when @value{AS} is configured for the
Ubicom IP2K series.
@ -1995,10 +1966,6 @@ For the @value{TARGET} target, @command{@value{AS}} is configured to produce
@value{OBJ-NAME} format object files.
@end ifclear
@c The following should exhaust all configs that set MULTI-OBJ, ideally
@ifset I960
On the @value{TARGET}, @command{@value{AS}} can be configured to produce either
@code{b.out} or COFF format object files.
@end ifset
@ifset HPPA
On the @value{TARGET}, @command{@value{AS}} can be configured to produce either
SOM or ELF format object files.
@ -2104,16 +2071,7 @@ is itself synthesized from other files. @command{@value{AS}} understands the
@kindex .o
Every time you run @command{@value{AS}} it produces an output file, which is
your assembly language program translated into numbers. This file
is the object file. Its default name is
@ifclear BOUT
@code{a.out}.
@end ifclear
@ifset BOUT
@ifset GENERIC
@code{a.out}, or
@end ifset
@code{b.out} when @command{@value{AS}} is configured for the Intel 80960.
@end ifset
is the object file. Its default name is @code{a.out}.
You can give it another name by using the @option{-o} option. Conventionally,
object file names end with @file{.o}. The default name is used for historical
reasons: older assemblers were capable of assembling self-contained programs
@ -2447,8 +2405,8 @@ displayed for a given single line of source input. The default value is 4.
@cindex MRI compatibility mode
The @option{-M} or @option{--mri} option selects MRI compatibility mode. This
changes the syntax and pseudo-op handling of @command{@value{AS}} to make it
compatible with the @code{ASM68K} or the @code{ASM960} (depending upon the
configured target) assembler from Microtec Research. The exact nature of the
compatible with the @code{ASM68K} assembler from Microtec Research.
The exact nature of the
MRI syntax will not be documented here; see the MRI manuals for more
information. Note in particular that the handling of macros and macro
arguments is somewhat different. The purpose of this option is to permit
@ -2545,30 +2503,6 @@ The m68k @code{OPT} @code{D} option is the default, unlike the MRI assembler.
The m68k @code{XREF} pseudo-op is ignored.
@item @code{.debug} pseudo-op
The i960 @code{.debug} pseudo-op is not supported.
@item @code{.extended} pseudo-op
The i960 @code{.extended} pseudo-op is not supported.
@item @code{.list} pseudo-op.
The various options of the i960 @code{.list} pseudo-op are not supported.
@item @code{.optimize} pseudo-op
The i960 @code{.optimize} pseudo-op is not supported.
@item @code{.output} pseudo-op
The i960 @code{.output} pseudo-op is not supported.
@item @code{.setreal} pseudo-op
The i960 @code{.setreal} pseudo-op is not supported.
@end itemize
@node MD
@ -2602,23 +2536,7 @@ disable this behaviour.
@cindex naming object file
@cindex object file name
There is always one object file output when you run @command{@value{AS}}. By
default it has the name
@ifset GENERIC
@ifset I960
@file{a.out} (or @file{b.out}, for Intel 960 targets only).
@end ifset
@ifclear I960
@file{a.out}.
@end ifclear
@end ifset
@ifclear GENERIC
@ifset I960
@file{b.out}.
@end ifset
@ifclear I960
@file{a.out}.
@end ifclear
@end ifclear
default it has the name @file{a.out}.
You use this option (which takes exactly one filename) to give the
object file a different name.
@ -3153,9 +3071,6 @@ are floating point numbers, described below.
* Bignums:: Bignums
* Flonums:: Flonums
@ifclear GENERIC
@ifset I960
* Bit Fields:: Bit Fields
@end ifset
@end ifclear
@end menu
@ -3230,16 +3145,12 @@ A letter, to tell @command{@value{AS}} the rest of the number is a flonum.
4.2 assembler seems to allow any of @samp{defghDEFGH}.)
@end ignore
On the H8/300, Renesas / SuperH SH,
and AMD 29K architectures, the letter must be
On the H8/300 and Renesas / SuperH SH architectures, the letter must be
one of the letters @samp{DFPRSX} (in upper or lower case).
On the ARC, the letter must be one of the letters @samp{DFRS}
(in upper or lower case).
On the Intel 960 architecture, the letter must be
one of the letters @samp{DFT} (in upper or lower case).
On the HPPA architecture, the letter must be @samp{E} (upper case only).
@end ifset
@ifclear GENERIC
@ -3252,9 +3163,6 @@ One of the letters @samp{DFPRSX} (in upper or lower case).
@ifset HPPA
The letter @samp{E} (upper case only).
@end ifset
@ifset I960
One of the letters @samp{DFT} (in upper or lower case).
@end ifset
@end ifclear
@item
@ -3290,41 +3198,6 @@ present. The floating point number has the usual base-10 value.
independently of any floating point hardware in the computer running
@command{@value{AS}}.
@ifclear GENERIC
@ifset I960
@c Bit fields are written as a general facility but are also controlled
@c by a conditional-compilation flag---which is as of now (21mar91)
@c turned on only by the i960 config of GAS.
@node Bit Fields
@subsubsection Bit Fields
@cindex bit fields
@cindex constants, bit field
You can also define numeric constants as @dfn{bit fields}.
Specify two numbers separated by a colon---
@example
@var{mask}:@var{value}
@end example
@noindent
@command{@value{AS}} applies a bitwise @sc{and} between @var{mask} and
@var{value}.
The resulting number is then packed
@ifset GENERIC
@c this conditional paren in case bit fields turned on elsewhere than 960
(in host-dependent byte order)
@end ifset
into a field whose width depends on which assembler directive has the
bit-field as its argument. Overflow (a result from the bitwise and
requiring more binary digits to represent) is not an error; instead,
more constants are generated, of the specified width, beginning with the
least significant digits.@refill
The directives @code{.byte}, @code{.hword}, @code{.int}, @code{.long},
@code{.short}, and @code{.word} accept bit-field arguments.
@end ifset
@end ifclear
@node Sections
@chapter Sections and Relocation
@cindex sections
@ -3486,7 +3359,7 @@ use of @command{@value{AS}} and have no meaning except during assembly.
@cindex sections, named
@item named sections
@end ifset
@ifset aout-bout
@ifset aout
@cindex text section
@cindex data section
@itemx text section
@ -3495,7 +3368,7 @@ use of @command{@value{AS}} and have no meaning except during assembly.
These sections hold your program. @command{@value{AS}} and @code{@value{LD}} treat them as
separate but equal sections. Anything you can say of one section is
true of another.
@c @ifset aout-bout
@c @ifset aout
When the program is running, however, it is
customary for the text section to be unalterable. The
text section is often shared among processes: it contains
@ -3615,7 +3488,7 @@ it in the expr section.
@cindex numbered subsections
@cindex grouping data
@ifset aout-bout
@ifset aout
Assembled bytes
@ifset COFF-ELF
conventionally
@ -3627,10 +3500,10 @@ You may have separate groups of
data in named sections
@end ifset
@ifclear GENERIC
@ifclear aout-bout
@ifclear aout
data in named sections
@end ifclear
@ifset aout-bout
@ifset aout
text or data
@end ifset
@end ifclear
@ -3659,14 +3532,6 @@ On the H8/300 platform, each subsection is zero-padded to a word
boundary (two bytes).
The same is true on the Renesas SH.
@end ifset
@ifset I960
@c FIXME section padding (alignment)?
@c Rich Pixley says padding here depends on target obj code format; that
@c doesn't seem particularly useful to say without further elaboration,
@c so for now I say nothing about it. If this is a generic BFD issue,
@c these paragraphs might need to vanish from this manual, and be
@c discussed in BFD chapter of binutils (or some such).
@end ifset
@end ifclear
Subsections appear in your object file in numeric order, lowest numbered
@ -3990,19 +3855,9 @@ would want.
@menu
* Symbol Value:: Value
* Symbol Type:: Type
@ifset aout-bout
@ifset GENERIC
@ifset aout
* a.out Symbols:: Symbol Attributes: @code{a.out}
@end ifset
@ifclear GENERIC
@ifclear BOUT
* a.out Symbols:: Symbol Attributes: @code{a.out}
@end ifclear
@ifset BOUT
* a.out Symbols:: Symbol Attributes: @code{a.out}, @code{b.out}
@end ifset
@end ifclear
@end ifset
@ifset COFF
* COFF Symbols:: Symbol Attributes for COFF
@end ifset
@ -4043,39 +3898,13 @@ information, any flag settings indicating that a symbol is external, and
(optionally), other information for linkers and debuggers. The exact
format depends on the object-code output format in use.
@ifset aout-bout
@ifclear GENERIC
@ifset BOUT
@c The following avoids a "widow" subsection title. @group would be
@c better if it were available outside examples.
@need 1000
@node a.out Symbols
@subsection Symbol Attributes: @code{a.out}, @code{b.out}
@cindex @code{b.out} symbol attributes
@cindex symbol attributes, @code{b.out}
These symbol attributes appear only when @command{@value{AS}} is configured for
one of the Berkeley-descended object output formats---@code{a.out} or
@code{b.out}.
@end ifset
@ifclear BOUT
@ifset aout
@node a.out Symbols
@subsection Symbol Attributes: @code{a.out}
@cindex @code{a.out} symbol attributes
@cindex symbol attributes, @code{a.out}
@end ifclear
@end ifclear
@ifset GENERIC
@node a.out Symbols
@subsection Symbol Attributes: @code{a.out}
@cindex @code{a.out} symbol attributes
@cindex symbol attributes, @code{a.out}
@end ifset
@menu
* Symbol Desc:: Descriptor
* Symbol Other:: Other
@ -4410,7 +4239,7 @@ Some machine configurations provide additional directives.
@ifset COFF
* Def:: @code{.def @var{name}}
@end ifset
@ifset aout-bout
@ifset aout
* Desc:: @code{.desc @var{symbol}, @var{abs-expression}}
@end ifset
@ifset COFF
@ -4594,10 +4423,6 @@ quit also. One day @code{.abort} will not be supported.
When producing COFF output, @command{@value{AS}} accepts this directive as a
synonym for @samp{.abort}.
@ifset BOUT
When producing @code{b.out} output, @command{@value{AS}} accepts this directive,
but ignores it.
@end ifset
@end ifset
@node Align
@ -4624,7 +4449,7 @@ required alignment; this can be useful if you want the alignment to be filled
with no-op instructions when appropriate.
The way the required alignment is specified varies from system to system.
For the arc, hppa, i386 using ELF, i860, iq2000, m68k, or1k,
For the arc, hppa, i386 using ELF, iq2000, m68k, or1k,
s390, sparc, tic4x, tic80 and xtensa, the first expression is the
alignment request in bytes. For example @samp{.align 8} advances
the location counter until it is a multiple of 8. If the location counter
@ -5163,15 +4988,9 @@ The byte ordering is target dependent.
@cindex debugging COFF symbols
Begin defining debugging information for a symbol @var{name}; the
definition extends until the @code{.endef} directive is encountered.
@ifset BOUT
This directive is only observed when @command{@value{AS}} is configured for COFF
format output; when producing @code{b.out}, @samp{.def} is recognized,
but ignored.
@end ifset
@end ifset
@ifset aout-bout
@ifset aout
@node Desc
@section @code{.desc @var{symbol}, @var{abs-expression}}
@ -5199,12 +5018,6 @@ it, but produces no output, when configured for COFF.
This directive is generated by compilers to include auxiliary debugging
information in the symbol table. It is only permitted inside
@code{.def}/@code{.endef} pairs.
@ifset BOUT
@samp{.dim} is only meaningful when generating COFF format output; when
@command{@value{AS}} is generating @code{b.out}, it accepts this directive but
ignores it.
@end ifset
@end ifset
@node Double
@ -5265,12 +5078,6 @@ process anything in the file past the @code{.end} directive.
@cindex @code{endef} directive
This directive flags the end of a symbol definition begun with
@code{.def}.
@ifset BOUT
@samp{.endef} is only meaningful when generating COFF format output; if
@command{@value{AS}} is configured to generate @code{b.out}, it accepts this
directive but ignores it.
@end ifset
@end ifset
@node Endfunc
@ -5801,7 +5608,7 @@ assemblers, but ignores it.
@cindex @code{line} directive
@cindex logical line number
@ifset aout-bout
@ifset aout
Change the logical line number. @var{line-number} must be an absolute
expression. The next line has that logical line number. Therefore any other
statements on the current line (after a statement separator character) are
@ -5886,12 +5693,6 @@ must be an absolute expression. The next line has that logical
line number, so any other statements on the current line (after a
statement separator character @code{;}) are reported as on logical
line number @var{line-number} @minus{} 1.
@ifset BOUT
This directive is accepted, but ignored, when @command{@value{AS}} is
configured for @code{b.out}; its effect is only associated with COFF
output format.
@end ifset
@end ifset
@node Loc
@ -6220,7 +6021,7 @@ instruction size limit is set to the maximum supported size.
@node Octa
@section @code{.octa @var{bignums}}
@c FIXME: double size emitted for "octa" on i960, others? Or warn?
@c FIXME: double size emitted for "octa" on some? Or warn?
@cindex @code{octa} directive
@cindex integer, 16-byte
@cindex sixteen byte integer
@ -6535,12 +6336,6 @@ Set the storage-class value for a symbol. This directive may only be
used inside a @code{.def}/@code{.endef} pair. Storage class may flag
whether a symbol is static or external, or it may record further
symbolic debugging information.
@ifset BOUT
The @samp{.scl} directive is primarily associated with COFF output; when
configured to generate @code{b.out} output format, @command{@value{AS}}
accepts this directive but ignores it.
@end ifset
@end ifset
@ifset COFF-ELF
@ -6900,11 +6695,6 @@ For COFF targets, the @code{.size} directive is only permitted inside
.size @var{expression}
@end smallexample
@ifset BOUT
@samp{.size} is only meaningful when generating COFF format output; when
@command{@value{AS}} is generating @code{b.out}, it accepts this directive but
ignores it.
@end ifset
@end ifset
@ifset ELF
@ -7172,12 +6962,6 @@ This directive is generated by compilers to include auxiliary debugging
information in the symbol table. It is only permitted inside
@code{.def}/@code{.endef} pairs. Tags are used to link structure
definitions in the symbol table with instances of those structures.
@ifset BOUT
@samp{.tag} is only used when generating COFF format output; when
@command{@value{AS}} is generating @code{b.out}, it accepts this directive but
ignores it.
@end ifset
@end ifset
@node Text
@ -7225,11 +7009,6 @@ For COFF targets, this directive is permitted only within
This records the integer @var{int} as the type attribute of a symbol table
entry.
@ifset BOUT
@samp{.type} is associated only with COFF format output; when
@command{@value{AS}} is configured for @code{b.out} output, it accepts this
directive but ignores it.
@end ifset
@end ifset
@ifset ELF
@ -7328,11 +7107,6 @@ symbolic debugging format. @xref{Sleb128, ,@code{.sleb128}}.
This directive, permitted only within @code{.def}/@code{.endef} pairs,
records the address @var{addr} as the value attribute of a symbol table
entry.
@ifset BOUT
@samp{.val} is used only for COFF output; when @command{@value{AS}} is
configured for @code{b.out}, it accepts this directive but ignores it.
@end ifset
@end ifset
@ifset ELF
@ -7422,7 +7196,7 @@ The size of the number emitted, and its byte order,
depend on what target computer the assembly is for.
@end ifset
@c on amd29k, i960, sparc the "special treatment to support compilers" doesn't
@c on sparc the "special treatment to support compilers" doesn't
@c happen---32-bit addressability, period; no long/short jumps.
@ifset DIFF-TBL-KLUGE
@cindex difference tables altered
@ -7764,12 +7538,6 @@ subject, see the hardware manufacturer's manual.
@ifset I80386
* i386-Dependent:: Intel 80386 and AMD x86-64 Dependent Features
@end ifset
@ifset I860
* i860-Dependent:: Intel 80860 Dependent Features
@end ifset
@ifset I960
* i960-Dependent:: Intel 80960 Dependent Features
@end ifset
@ifset IA64
* IA-64-Dependent:: Intel IA-64 Dependent Features
@end ifset
@ -7979,14 +7747,6 @@ family.
@include c-i386.texi
@end ifset
@ifset I860
@include c-i860.texi
@end ifset
@ifset I960
@include c-i960.texi
@end ifset
@ifset IA64
@include c-ia64.texi
@end ifset

197
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@ -1,197 +0,0 @@
@c Copyright (C) 2000-2018 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@ifset GENERIC
@page
@node i860-Dependent
@chapter Intel i860 Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter Intel i860 Dependent Features
@end ifclear
@ignore
@c FIXME: This is basically a stub for i860. There is tons more information
that I will add later (jle@cygnus.com).
@end ignore
@cindex i860 support
@menu
* Notes-i860:: i860 Notes
* Options-i860:: i860 Command-line Options
* Directives-i860:: i860 Machine Directives
* Opcodes for i860:: i860 Opcodes
* Syntax of i860:: i860 Syntax
@end menu
@node Notes-i860
@section i860 Notes
This is a fairly complete i860 assembler which is compatible with the
UNIX System V/860 Release 4 assembler. However, it does not currently
support SVR4 PIC (i.e., @code{@@GOT, @@GOTOFF, @@PLT}).
Like the SVR4/860 assembler, the output object format is ELF32. Currently,
this is the only supported object format. If there is sufficient interest,
other formats such as COFF may be implemented.
Both the Intel and AT&T/SVR4 syntaxes are supported, with the latter
being the default. One difference is that AT&T syntax requires the '%'
prefix on register names while Intel syntax does not. Another difference
is in the specification of relocatable expressions. The Intel syntax
is @code{ha%expression} whereas the SVR4 syntax is @code{[expression]@@ha}
(and similarly for the "l" and "h" selectors).
@node Options-i860
@section i860 Command-line Options
@subsection SVR4 compatibility options
@table @code
@item -V
Print assembler version.
@item -Qy
Ignored.
@item -Qn
Ignored.
@end table
@subsection Other options
@table @code
@item -EL
Select little endian output (this is the default).
@item -EB
Select big endian output. Note that the i860 always reads instructions
as little endian data, so this option only effects data and not
instructions.
@item -mwarn-expand
Emit a warning message if any pseudo-instruction expansions occurred.
For example, a @code{or} instruction with an immediate larger than 16-bits
will be expanded into two instructions. This is a very undesirable feature to
rely on, so this flag can help detect any code where it happens. One
use of it, for instance, has been to find and eliminate any place
where @code{gcc} may emit these pseudo-instructions.
@item -mxp
Enable support for the i860XP instructions and control registers. By default,
this option is disabled so that only the base instruction set (i.e., i860XR)
is supported.
@item -mintel-syntax
The i860 assembler defaults to AT&T/SVR4 syntax. This option enables the
Intel syntax.
@end table
@node Directives-i860
@section i860 Machine Directives
@cindex machine directives, i860
@cindex i860 machine directives
@table @code
@cindex @code{dual} directive, i860
@item .dual
Enter dual instruction mode. While this directive is supported, the
preferred way to use dual instruction mode is to explicitly code
the dual bit with the @code{d.} prefix.
@end table
@table @code
@cindex @code{enddual} directive, i860
@item .enddual
Exit dual instruction mode. While this directive is supported, the
preferred way to use dual instruction mode is to explicitly code
the dual bit with the @code{d.} prefix.
@end table
@table @code
@cindex @code{atmp} directive, i860
@item .atmp
Change the temporary register used when expanding pseudo operations. The
default register is @code{r31}.
@end table
The @code{.dual}, @code{.enddual}, and @code{.atmp} directives are available only in the Intel syntax mode.
Both syntaxes allow for the standard @code{.align} directive. However,
the Intel syntax additionally allows keywords for the alignment
parameter: "@code{.align type}", where `type' is one of @code{.short}, @code{.long},
@code{.quad}, @code{.single}, @code{.double} representing alignments of 2, 4,
16, 4, and 8, respectively.
@node Opcodes for i860
@section i860 Opcodes
@cindex opcodes, i860
@cindex i860 opcodes
All of the Intel i860XR and i860XP machine instructions are supported. Please see
either @emph{i860 Microprocessor Programmer's Reference Manual} or @emph{i860 Microprocessor Architecture} for more information.
@subsection Other instruction support (pseudo-instructions)
For compatibility with some other i860 assemblers, a number of
pseudo-instructions are supported. While these are supported, they are
a very undesirable feature that should be avoided -- in particular, when
they result in an expansion to multiple actual i860 instructions. Below
are the pseudo-instructions that result in expansions.
@itemize @bullet
@item Load large immediate into general register:
The pseudo-instruction @code{mov imm,%rn} (where the immediate does
not fit within a signed 16-bit field) will be expanded into:
@smallexample
orh large_imm@@h,%r0,%rn
or large_imm@@l,%rn,%rn
@end smallexample
@item Load/store with relocatable address expression:
For example, the pseudo-instruction @code{ld.b addr_exp(%rx),%rn}
will be expanded into:
@smallexample
orh addr_exp@@ha,%rx,%r31
ld.l addr_exp@@l(%r31),%rn
@end smallexample
The analogous expansions apply to @code{ld.x, st.x, fld.x, pfld.x, fst.x}, and @code{pst.x} as well.
@item Signed large immediate with add/subtract:
If any of the arithmetic operations @code{adds, addu, subs, subu} are used
with an immediate larger than 16-bits (signed), then they will be expanded.
For instance, the pseudo-instruction @code{adds large_imm,%rx,%rn} expands to:
@smallexample
orh large_imm@@h,%r0,%r31
or large_imm@@l,%r31,%r31
adds %r31,%rx,%rn
@end smallexample
@item Unsigned large immediate with logical operations:
Logical operations (@code{or, andnot, or, xor}) also result in expansions.
The pseudo-instruction @code{or large_imm,%rx,%rn} results in:
@smallexample
orh large_imm@@h,%rx,%r31
or large_imm@@l,%r31,%rn
@end smallexample
Similarly for the others, except for @code{and} which expands to:
@smallexample
andnot (-1 - large_imm)@@h,%rx,%r31
andnot (-1 - large_imm)@@l,%r31,%rn
@end smallexample
@end itemize
@node Syntax of i860
@section i860 Syntax
@menu
* i860-Chars:: Special Characters
@end menu
@node i860-Chars
@subsection Special Characters
@cindex line comment character, i860
@cindex i860 line comment character
The presence of a @samp{#} appearing anywhere on a line indicates the
start of a comment that extends to the end of that line.
If a @samp{#} appears as the first character of a line then the whole
line is treated as a comment, but in this case the line can also be a
logical line number directive (@pxref{Comments}) or a preprocessor
control command (@pxref{Preprocessing}).
@cindex line separator, i860
@cindex statement separator, i860
@cindex i860 line separator
The @samp{;} character can be used to separate statements on the same
line.

324
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@ -1,324 +0,0 @@
@c Copyright (C) 1991-2018 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@ifset GENERIC
@page
@node i960-Dependent
@chapter Intel 80960 Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter Intel 80960 Dependent Features
@end ifclear
@cindex i960 support
@menu
* Options-i960:: i960 Command-line Options
* Floating Point-i960:: Floating Point
* Directives-i960:: i960 Machine Directives
* Opcodes for i960:: i960 Opcodes
* Syntax of i960:: i960 Syntax
@end menu
@c FIXME! Add Syntax sec with discussion of bitfields here, at least so
@c long as they're not turned on for other machines than 960.
@node Options-i960
@section i960 Command-line Options
@cindex i960 options
@cindex options, i960
@table @code
@cindex i960 architecture options
@cindex architecture options, i960
@cindex @code{-A} options, i960
@item -ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC
Select the 80960 architecture. Instructions or features not supported
by the selected architecture cause fatal errors.
@samp{-ACA} is equivalent to @samp{-ACA_A}; @samp{-AKC} is equivalent to
@samp{-AMC}. Synonyms are provided for compatibility with other tools.
If you do not specify any of these options, @code{@value{AS}} generates code
for any instruction or feature that is supported by @emph{some} version of the
960 (even if this means mixing architectures!). In principle,
@code{@value{AS}} attempts to deduce the minimal sufficient processor type if
none is specified; depending on the object code format, the processor type may
be recorded in the object file. If it is critical that the @code{@value{AS}}
output match a specific architecture, specify that architecture explicitly.
@cindex @code{-b} option, i960
@cindex branch recording, i960
@cindex i960 branch recording
@item -b
Add code to collect information about conditional branches taken, for
later optimization using branch prediction bits. (The conditional branch
instructions have branch prediction bits in the CA, CB, and CC
architectures.) If @var{BR} represents a conditional branch instruction,
the following represents the code generated by the assembler when
@samp{-b} is specified:
@smallexample
call @var{increment routine}
.word 0 # pre-counter
Label: @var{BR}
call @var{increment routine}
.word 0 # post-counter
@end smallexample
The counter following a branch records the number of times that branch
was @emph{not} taken; the difference between the two counters is the
number of times the branch @emph{was} taken.
@cindex @code{gbr960}, i960 postprocessor
@cindex branch statistics table, i960
A table of every such @code{Label} is also generated, so that the
external postprocessor @code{gbr960} (supplied by Intel) can locate all
the counters. This table is always labeled @samp{__BRANCH_TABLE__};
this is a local symbol to permit collecting statistics for many separate
object files. The table is word aligned, and begins with a two-word
header. The first word, initialized to 0, is used in maintaining linked
lists of branch tables. The second word is a count of the number of
entries in the table, which follow immediately: each is a word, pointing
to one of the labels illustrated above.
@c TEXI2ROFF-KILL
@ifinfo
@c END TEXI2ROFF-KILL
@example
+------------+------------+------------+ ... +------------+
| | | | | |
| *NEXT | COUNT: N | *BRLAB 1 | | *BRLAB N |
| | | | | |
+------------+------------+------------+ ... +------------+
__BRANCH_TABLE__ layout
@end example
@c TEXI2ROFF-KILL
@end ifinfo
@need 2000
@tex
\vskip 1pc
\line{\leftskip=0pt\hskip\tableindent
\boxit{2cm}{\tt *NEXT}\boxit{2cm}{\tt COUNT: \it N}\boxit{2cm}{\tt
*BRLAB 1}\ibox{1cm}{\quad\dots}\boxit{2cm}{\tt *BRLAB \it N}\hfil}
\centerline{\it {\tt \_\_BRANCH\_TABLE\_\_} layout}
@end tex
@c END TEXI2ROFF-KILL
The first word of the header is used to locate multiple branch tables,
since each object file may contain one. Normally the links are
maintained with a call to an initialization routine, placed at the
beginning of each function in the file. The @sc{gnu} C compiler
generates these calls automatically when you give it a @samp{-b} option.
For further details, see the documentation of @samp{gbr960}.
@cindex @code{-no-relax} option, i960
@item -no-relax
Normally, Compare-and-Branch instructions with targets that require
displacements greater than 13 bits (or that have external targets) are
replaced with the corresponding compare (or @samp{chkbit}) and branch
instructions. You can use the @samp{-no-relax} option to specify that
@code{@value{AS}} should generate errors instead, if the target displacement
is larger than 13 bits.
This option does not affect the Compare-and-Jump instructions; the code
emitted for them is @emph{always} adjusted when necessary (depending on
displacement size), regardless of whether you use @samp{-no-relax}.
@end table
@node Floating Point-i960
@section Floating Point
@cindex floating point, i960 (@sc{ieee})
@cindex i960 floating point (@sc{ieee})
@code{@value{AS}} generates @sc{ieee} floating-point numbers for the directives
@samp{.float}, @samp{.double}, @samp{.extended}, and @samp{.single}.
@node Directives-i960
@section i960 Machine Directives
@cindex machine directives, i960
@cindex i960 machine directives
@table @code
@cindex @code{bss} directive, i960
@item .bss @var{symbol}, @var{length}, @var{align}
Reserve @var{length} bytes in the bss section for a local @var{symbol},
aligned to the power of two specified by @var{align}. @var{length} and
@var{align} must be positive absolute expressions. This directive
differs from @samp{.lcomm} only in that it permits you to specify
an alignment. @xref{Lcomm,,@code{.lcomm}}.
@end table
@table @code
@cindex @code{extended} directive, i960
@item .extended @var{flonums}
@code{.extended} expects zero or more flonums, separated by commas; for
each flonum, @samp{.extended} emits an @sc{ieee} extended-format (80-bit)
floating-point number.
@cindex @code{leafproc} directive, i960
@item .leafproc @var{call-lab}, @var{bal-lab}
You can use the @samp{.leafproc} directive in conjunction with the
optimized @code{callj} instruction to enable faster calls of leaf
procedures. If a procedure is known to call no other procedures, you
may define an entry point that skips procedure prolog code (and that does
not depend on system-supplied saved context), and declare it as the
@var{bal-lab} using @samp{.leafproc}. If the procedure also has an
entry point that goes through the normal prolog, you can specify that
entry point as @var{call-lab}.
A @samp{.leafproc} declaration is meant for use in conjunction with the
optimized call instruction @samp{callj}; the directive records the data
needed later to choose between converting the @samp{callj} into a
@code{bal} or a @code{call}.
@var{call-lab} is optional; if only one argument is present, or if the
two arguments are identical, the single argument is assumed to be the
@code{bal} entry point.
@cindex @code{sysproc} directive, i960
@item .sysproc @var{name}, @var{index}
The @samp{.sysproc} directive defines a name for a system procedure.
After you define it using @samp{.sysproc}, you can use @var{name} to
refer to the system procedure identified by @var{index} when calling
procedures with the optimized call instruction @samp{callj}.
Both arguments are required; @var{index} must be between 0 and 31
(inclusive).
@end table
@node Opcodes for i960
@section i960 Opcodes
@cindex opcodes, i960
@cindex i960 opcodes
All Intel 960 machine instructions are supported;
@pxref{Options-i960,,i960 Command-line Options} for a discussion of
selecting the instruction subset for a particular 960
architecture.@refill
Some opcodes are processed beyond simply emitting a single corresponding
instruction: @samp{callj}, and Compare-and-Branch or Compare-and-Jump
instructions with target displacements larger than 13 bits.
@menu
* callj-i960:: @code{callj}
* Compare-and-branch-i960:: Compare-and-Branch
@end menu
@node callj-i960
@subsection @code{callj}
@cindex @code{callj}, i960 pseudo-opcode
@cindex i960 @code{callj} pseudo-opcode
You can write @code{callj} to have the assembler or the linker determine
the most appropriate form of subroutine call: @samp{call},
@samp{bal}, or @samp{calls}. If the assembly source contains
enough information---a @samp{.leafproc} or @samp{.sysproc} directive
defining the operand---then @code{@value{AS}} translates the
@code{callj}; if not, it simply emits the @code{callj}, leaving it
for the linker to resolve.
@node Compare-and-branch-i960
@subsection Compare-and-Branch
@cindex i960 compare/branch instructions
@cindex compare/branch instructions, i960
The 960 architectures provide combined Compare-and-Branch instructions
that permit you to store the branch target in the lower 13 bits of the
instruction word itself. However, if you specify a branch target far
enough away that its address won't fit in 13 bits, the assembler can
either issue an error, or convert your Compare-and-Branch instruction
into separate instructions to do the compare and the branch.
@cindex compare and jump expansions, i960
@cindex i960 compare and jump expansions
Whether @code{@value{AS}} gives an error or expands the instruction depends
on two choices you can make: whether you use the @samp{-no-relax} option,
and whether you use a ``Compare and Branch'' instruction or a ``Compare
and Jump'' instruction. The ``Jump'' instructions are @emph{always}
expanded if necessary; the ``Branch'' instructions are expanded when
necessary @emph{unless} you specify @code{-no-relax}---in which case
@code{@value{AS}} gives an error instead.
These are the Compare-and-Branch instructions, their ``Jump'' variants,
and the instruction pairs they may expand into:
@c TEXI2ROFF-KILL
@ifinfo
@c END TEXI2ROFF-KILL
@example
Compare and
Branch Jump Expanded to
------ ------ ------------
bbc chkbit; bno
bbs chkbit; bo
cmpibe cmpije cmpi; be
cmpibg cmpijg cmpi; bg
cmpibge cmpijge cmpi; bge
cmpibl cmpijl cmpi; bl
cmpible cmpijle cmpi; ble
cmpibno cmpijno cmpi; bno
cmpibne cmpijne cmpi; bne
cmpibo cmpijo cmpi; bo
cmpobe cmpoje cmpo; be
cmpobg cmpojg cmpo; bg
cmpobge cmpojge cmpo; bge
cmpobl cmpojl cmpo; bl
cmpoble cmpojle cmpo; ble
cmpobne cmpojne cmpo; bne
@end example
@c TEXI2ROFF-KILL
@end ifinfo
@tex
\hskip\tableindent
\halign{\hfil {\tt #}\quad&\hfil {\tt #}\qquad&{\tt #}\hfil\cr
\omit{\hfil\it Compare and\hfil}\span\omit&\cr
{\it Branch}&{\it Jump}&{\it Expanded to}\cr
bbc& & chkbit; bno\cr
bbs& & chkbit; bo\cr
cmpibe& cmpije& cmpi; be\cr
cmpibg& cmpijg& cmpi; bg\cr
cmpibge& cmpijge& cmpi; bge\cr
cmpibl& cmpijl& cmpi; bl\cr
cmpible& cmpijle& cmpi; ble\cr
cmpibno& cmpijno& cmpi; bno\cr
cmpibne& cmpijne& cmpi; bne\cr
cmpibo& cmpijo& cmpi; bo\cr
cmpobe& cmpoje& cmpo; be\cr
cmpobg& cmpojg& cmpo; bg\cr
cmpobge& cmpojge& cmpo; bge\cr
cmpobl& cmpojl& cmpo; bl\cr
cmpoble& cmpojle& cmpo; ble\cr
cmpobne& cmpojne& cmpo; bne\cr}
@end tex
@c END TEXI2ROFF-KILL
@node Syntax of i960
@section Syntax for the i960
@menu
* i960-Chars:: Special Characters
@end menu
@node i960-Chars
@subsection Special Characters
@cindex line comment character, i960
@cindex i960 line comment character
The presence of a @samp{#} on a line indicates the start of a comment
that extends to the end of the current line.
If a @samp{#} appears as the first character of a line, the whole line
is treated as a comment, but in this case the line can also be a
logical line number directive (@pxref{Comments}) or a
preprocessor control command (@pxref{Preprocessing}).
@cindex line separator, i960
@cindex statement separator, i960
@cindex i960 line separator
The @samp{;} character can be used to separate statements on the same
line.

1
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@ -7,7 +7,6 @@
@clear INTERNALS
@clear MULTI-OBJ
@clear AOUT
@clear BOUT
@set COFF
@clear ELF
@set Renesas-all

11
gas/doc/internals.texi
View File

@ -1096,11 +1096,6 @@ You may define this macro to parse an expression used in a data allocation
pseudo-op such as @code{.word}. You can use this to recognize relocation
directives that may appear in such directives.
@item BITFIELD_CONS_EXPRESSION
@cindex BITFIELD_CONS_EXPRESSION
If you define this macro, GAS will recognize bitfield instructions in data
allocation pseudo-ops, as used on the i960.
@item REPEAT_CONS_EXPRESSION
@cindex REPEAT_CONS_EXPRESSION
If you define this macro, GAS will recognize repeat counts in data allocation
@ -1753,12 +1748,6 @@ no-op instructions, it must be able to expand or shrink the section contents
while still preserving intra-section references and meeting alignment
requirements.
For the i960 using b.out format, no expansion is done; instead, each
@samp{.align} directive causes extra space to be allocated, enough that when
the linker is relaxing a section and removing unneeded space, it can discard
some or all of this extra padding and cause the following data to be correctly
aligned.
For the H8/300, I think the linker expands calls that can't reach, and doesn't
worry about alignment issues; the cpu probably never needs any significant
alignment beyond the instruction size.

42
gas/expr.c
View File

@ -1302,48 +1302,6 @@ operand (expressionS *expressionP, enum expr_mode mode)
}
#endif
#ifdef TC_I960
/* The MRI i960 assembler permits
lda sizeof code,g13
FIXME: This should use md_parse_name. */
if (flag_mri
&& (strcasecmp (name, "sizeof") == 0
|| strcasecmp (name, "startof") == 0))
{
int start;
char *buf;
start = (name[1] == 't'
|| name[1] == 'T');
*input_line_pointer = c;
SKIP_WHITESPACE_AFTER_NAME ();
c = get_symbol_name (& name);
if (! *name)
{
as_bad (_("expected symbol name"));
expressionP->X_op = O_absent;
(void) restore_line_pointer (c);
ignore_rest_of_line ();
break;
}
buf = concat (start ? ".startof." : ".sizeof.", name,
(char *) NULL);
symbolP = symbol_make (buf);
free (buf);
expressionP->X_op = O_symbol;
expressionP->X_add_symbol = symbolP;
expressionP->X_add_number = 0;
*input_line_pointer = c;
SKIP_WHITESPACE_AFTER_NAME ();
break;
}
#endif
symbolP = symbol_find_or_make (name);
/* If we have an absolute symbol or a reg, then we know its

4
gas/po/POTFILES.in
View File

@ -76,10 +76,6 @@ config/tc-i370.c
config/tc-i370.h
config/tc-i386.c
config/tc-i386.h
config/tc-i860.c
config/tc-i860.h
config/tc-i960.c
config/tc-i960.h
config/tc-ia64.c
config/tc-ia64.h
config/tc-ip2k.c

208
gas/read.c
View File

@ -2972,81 +2972,10 @@ s_mri_sect (char *type ATTRIBUTE_UNUSED)
demand_empty_rest_of_line ();
#else /* ! TC_M68K */
#ifdef TC_I960
char *name;
char c;
segT seg;
SKIP_WHITESPACE ();
c = get_symbol_name (& name);
name = xstrdup (name);
c = restore_line_pointer (c);
seg = subseg_new (name, 0);
if (c != ',')
*type = 'C';
else
{
char *sectype;
++input_line_pointer;
SKIP_WHITESPACE ();
c = get_symbol_name (& sectype);
if (*sectype == '\0')
*type = 'C';
else if (strcasecmp (sectype, "text") == 0)
*type = 'C';
else if (strcasecmp (sectype, "data") == 0)
*type = 'D';
else if (strcasecmp (sectype, "romdata") == 0)
*type = 'R';
else
as_warn (_("unrecognized section type `%s'"), sectype);
(void) restore_line_pointer (c);
}
if (*input_line_pointer == ',')
{
char *seccmd;
++input_line_pointer;
SKIP_WHITESPACE ();
c = get_symbol_name (& seccmd);
if (strcasecmp (seccmd, "absolute") == 0)
{
as_bad (_("absolute sections are not supported"));
*input_line_pointer = c;
ignore_rest_of_line ();
return;
}
else if (strcasecmp (seccmd, "align") == 0)
{
unsigned int align;
(void) restore_line_pointer (c);
align = get_absolute_expression ();
record_alignment (seg, align);
}
else
{
as_warn (_("unrecognized section command `%s'"), seccmd);
(void) restore_line_pointer (c);
}
}
demand_empty_rest_of_line ();
#else /* ! TC_I960 */
/* The MRI assembler seems to use different forms of .sect for
different targets. */
as_bad ("MRI mode not supported for this target");
ignore_rest_of_line ();
#endif /* ! TC_I960 */
#endif /* ! TC_M68K */
}
@ -3978,7 +3907,6 @@ pseudo_set (symbolS *symbolP)
/* Some targets need to parse the expression in various fancy ways.
You can define TC_PARSE_CONS_EXPRESSION to do whatever you like
(for example, the HPPA does this). Otherwise, you can define
BITFIELD_CONS_EXPRESSIONS to permit bitfields to be specified, or
REPEAT_CONS_EXPRESSIONS to permit repeat counts. If none of these
are defined, which is the normal case, then only simple expressions
are permitted. */
@ -3989,12 +3917,6 @@ parse_mri_cons (expressionS *exp, unsigned int nbytes);
#endif
#ifndef TC_PARSE_CONS_EXPRESSION
#ifdef BITFIELD_CONS_EXPRESSIONS
#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) \
(parse_bitfield_cons (EXP, NBYTES), TC_PARSE_CONS_RETURN_NONE)
static void
parse_bitfield_cons (expressionS *exp, unsigned int nbytes);
#endif
#ifdef REPEAT_CONS_EXPRESSIONS
#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) \
(parse_repeat_cons (EXP, NBYTES), TC_PARSE_CONS_RETURN_NONE)
@ -4658,136 +4580,6 @@ emit_expr_fix (expressionS *exp, unsigned int nbytes, fragS *frag, char *p,
#endif
}
#ifdef BITFIELD_CONS_EXPRESSIONS
/* i960 assemblers, (eg, asm960), allow bitfields after ".byte" as
w:x,y:z, where w and y are bitwidths and x and y are values. They
then pack them all together. We do a little better in that we allow
them in words, longs, etc. and we'll pack them in target byte order
for you.
The rules are: pack least significant bit first, if a field doesn't
entirely fit, put it in the next unit. Overflowing the bitfield is
explicitly *not* even a warning. The bitwidth should be considered
a "mask".
To use this function the tc-XXX.h file should define
BITFIELD_CONS_EXPRESSIONS. */
static void
parse_bitfield_cons (expressionS *exp, unsigned int nbytes)
{
unsigned int bits_available = BITS_PER_CHAR * nbytes;
char *hold = input_line_pointer;
(void) expression (exp);
if (*input_line_pointer == ':')
{
/* Bitfields. */
long value = 0;
for (;;)
{
unsigned long width;
if (*input_line_pointer != ':')
{
input_line_pointer = hold;
break;
} /* Next piece is not a bitfield. */
/* In the general case, we can't allow
full expressions with symbol
differences and such. The relocation
entries for symbols not defined in this
assembly would require arbitrary field
widths, positions, and masks which most
of our current object formats don't
support.
In the specific case where a symbol
*is* defined in this assembly, we
*could* build fixups and track it, but
this could lead to confusion for the
backends. I'm lazy. I'll take any
SEG_ABSOLUTE. I think that means that
you can use a previous .set or
.equ type symbol. xoxorich. */
if (exp->X_op == O_absent)
{
as_warn (_("using a bit field width of zero"));
exp->X_add_number = 0;
exp->X_op = O_constant;
} /* Implied zero width bitfield. */
if (exp->X_op != O_constant)
{
*input_line_pointer = '\0';
as_bad (_("field width \"%s\" too complex for a bitfield"), hold);
*input_line_pointer = ':';
demand_empty_rest_of_line ();
return;
} /* Too complex. */
if ((width = exp->X_add_number) > (BITS_PER_CHAR * nbytes))
{
as_warn (ngettext ("field width %lu too big to fit in %d byte:"
" truncated to %d bits",
"field width %lu too big to fit in %d bytes:"
" truncated to %d bits",
nbytes),
width, nbytes, (BITS_PER_CHAR * nbytes));
width = BITS_PER_CHAR * nbytes;
} /* Too big. */
if (width > bits_available)
{
/* FIXME-SOMEDAY: backing up and reparsing is wasteful. */
input_line_pointer = hold;
exp->X_add_number = value;
break;
} /* Won't fit. */
/* Skip ':'. */
hold = ++input_line_pointer;
(void) expression (exp);
if (exp->X_op != O_constant)
{
char cache = *input_line_pointer;
*input_line_pointer = '\0';
as_bad (_("field value \"%s\" too complex for a bitfield"), hold);
*input_line_pointer = cache;
demand_empty_rest_of_line ();
return;
} /* Too complex. */
value |= ((~(-(1 << width)) & exp->X_add_number)
<< ((BITS_PER_CHAR * nbytes) - bits_available));
if ((bits_available -= width) == 0
|| is_it_end_of_statement ()
|| *input_line_pointer != ',')
{
break;
} /* All the bitfields we're gonna get. */
hold = ++input_line_pointer;
(void) expression (exp);
}
exp->X_add_number = value;
exp->X_op = O_constant;
exp->X_unsigned = 1;
exp->X_extrabit = 0;
}
}
#endif /* BITFIELD_CONS_EXPRESSIONS */
/* Handle an MRI style string expression. */
#ifdef TC_M68K

3
gas/symbols.c
View File

@ -407,8 +407,7 @@ colon (/* Just seen "x:" - rattle symbols & frags. */
}
else
{
#if (!defined (OBJ_AOUT) && !defined (OBJ_MAYBE_AOUT) \
&& !defined (OBJ_BOUT) && !defined (OBJ_MAYBE_BOUT))
#if (!defined (OBJ_AOUT) && !defined (OBJ_MAYBE_AOUT))
static const char *od_buf = "";
#else
char od_buf[100];

13
gas/testsuite/gas/all/gas.exp
View File

@ -106,7 +106,7 @@ case $target_triplet in {
default {
# Some targets don't manage to resolve BFD_RELOC_8 for constants.
setup_xfail "alpha*-*-*" "*c30*-*-*" "*c4x*-*-*" \
"d\[13\]0v*-*-*" "i860-*-*" \
"d\[13\]0v*-*-*" \
"nds32*-*-*" "pdp11-*-*" "xtensa*-*-*"
run_dump_test forward
}
@ -335,8 +335,7 @@ if { ([istarget *-*-coff*] && ![istarget arm*-*-coff] && ![istarget *c4x*-*-co
|| [istarget i*86-*-cygwin*] \
|| [istarget x86_64-*-mingw*] \
|| [istarget i*86-*-*nt] \
|| [istarget i*86-*-interix*] \
|| ([istarget i960-*-vxworks5.*] && ![istarget i960-*-vxworks5.0*]) } {
|| [istarget i*86-*-interix*] } {
run_dump_test cofftag
}
@ -413,10 +412,7 @@ if { ![istarget "powerpc*-*-*"] && ![istarget "rs6000*-*-*"] && ![istarget "s390
run_dump_test byte
}
# .quad is 16 bytes on i960.
if { ![istarget "i960-*-*"] } {
run_dump_test quad
}
run_dump_test quad
# som doesn't use .data section.
case $target_triplet in {
@ -467,9 +463,6 @@ case $target_triplet in {
{ "mmix-*-*" } {
set nop_type 5
}
{ "i960-*-*" } {
set nop_type 4
}
{ "i370-*-*" } {
set nop_type 3
}

39
gas/testsuite/gas/i860/README.i860
View File

@ -1,39 +0,0 @@
Testsuite for the i860 version of the GNU assembler
---------------------------------------------------
This is a simple testsuite for the i860 assembler. It currently
consists mostly of testcases for checking that every instruction is
parsed correctly and that correct object code is generated (these
are called "blah.s"). The files called "blah-err.s" test for error
conditions.
The suite includes testcases for the base i860XR instruction set as well
as the enhanced i860XP instructions and control registers.
The expected results files were generated using the UNIX System V/i860
Release 4 vendor assembler (/usr/ccs/bin/as -V reports version
"Standard C Development Environment (SCDE) 5.0 12/08/89"). This
way GAS/i860 is tested against a known good assembler.
TODO:
- Relocation testing is basically non-existent.
- pst.d (pixel store) is the only instruction with no testcase.
- Some pseudo instructions need testcases (mov, all pfmov, etc.).
- More tests for dual instruction mode: check that dual mode has a
proper pair (FLOP/core) of instructions, and other error conditions.
- Most current testcases use the default AT&T/SVR4 syntax; a few simple
tests of the Intel syntax should be added to prevent bitrot (including
relocatable expression syntax, etc). Test file dual03.s uses Intel
syntax lightly (i.e., register names without '%' prefix).
Contact me (Jason Eckhardt, jle@rice.edu) if you'd like to help.
Known testsuite failures:
- none.
Copyright (C) 2012-2018 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.

141
gas/testsuite/gas/i860/bitwise.d
View File

@ -1,141 +0,0 @@
#as:
#objdump: -dr
#name: i860 bitwise
.*: +file format .*
Disassembly of section \.text:
00000000 <\.text>:
0: 00 00 22 c0 and %r0,%r1,%sp
4: 00 18 85 c0 and %fp,%r4,%r5
8: 00 30 e8 c0 and %r6,%r7,%r8
c: 00 48 4b c1 and %r9,%r10,%r11
10: 00 60 ae c1 and %r12,%r13,%r14
14: 00 78 11 c2 and %r15,%r16,%r17
18: 00 90 74 c2 and %r18,%r19,%r20
1c: 00 a8 d7 c2 and %r21,%r22,%r23
20: 00 c0 3a c3 and %r24,%r25,%r26
24: 00 d8 9d c3 and %r27,%r28,%r29
28: 00 f0 e0 c3 and %r30,%r31,%r0
2c: 00 00 22 d0 andnot %r0,%r1,%sp
30: 00 18 85 d0 andnot %fp,%r4,%r5
34: 00 30 e8 d0 andnot %r6,%r7,%r8
38: 00 48 4b d1 andnot %r9,%r10,%r11
3c: 00 60 ae d1 andnot %r12,%r13,%r14
40: 00 78 11 d2 andnot %r15,%r16,%r17
44: 00 90 74 d2 andnot %r18,%r19,%r20
48: 00 a8 d7 d2 andnot %r21,%r22,%r23
4c: 00 c0 3a d3 andnot %r24,%r25,%r26
50: 00 d8 9d d3 andnot %r27,%r28,%r29
54: 00 f0 e0 d3 andnot %r30,%r31,%r0
58: 00 00 22 e0 or %r0,%r1,%sp
5c: 00 18 85 e0 or %fp,%r4,%r5
60: 00 30 e8 e0 or %r6,%r7,%r8
64: 00 48 4b e1 or %r9,%r10,%r11
68: 00 60 ae e1 or %r12,%r13,%r14
6c: 00 78 11 e2 or %r15,%r16,%r17
70: 00 90 74 e2 or %r18,%r19,%r20
74: 00 a8 d7 e2 or %r21,%r22,%r23
78: 00 c0 3a e3 or %r24,%r25,%r26
7c: 00 d8 9d e3 or %r27,%r28,%r29
80: 00 f0 e0 e3 or %r30,%r31,%r0
84: 00 00 22 f0 xor %r0,%r1,%sp
88: 00 18 85 f0 xor %fp,%r4,%r5
8c: 00 30 e8 f0 xor %r6,%r7,%r8
90: 00 48 4b f1 xor %r9,%r10,%r11
94: 00 60 ae f1 xor %r12,%r13,%r14
98: 00 78 11 f2 xor %r15,%r16,%r17
9c: 00 90 74 f2 xor %r18,%r19,%r20
a0: 00 a8 d7 f2 xor %r21,%r22,%r23
a4: 00 c0 3a f3 xor %r24,%r25,%r26
a8: 00 d8 9d f3 xor %r27,%r28,%r29
ac: 00 f0 e0 f3 xor %r30,%r31,%r0
b0: 00 00 22 c4 and 0x0000,%r1,%sp
b4: 00 20 85 c4 and 0x2000,%r4,%r5
b8: f5 13 e8 c4 and 0x13f5,%r7,%r8
bc: 00 80 4b c5 and 0x8000,%r10,%r11
c0: e8 fd ae c5 and 0xfde8,%r13,%r14
c4: ff ff 11 c6 and 0xffff,%r16,%r17
c8: ff ff 74 c6 and 0xffff,%r19,%r20
cc: cd ab d7 c6 and 0xabcd,%r22,%r23
d0: 34 12 3a c7 and 0x1234,%r25,%r26
d4: 00 00 9d c7 and 0x0000,%r28,%r29
d8: 03 00 e0 c7 and 0x0003,%r31,%r0
dc: 01 00 22 cc andh 0x0001,%r1,%sp
e0: 01 20 85 cc andh 0x2001,%r4,%r5
e4: f6 13 e8 cc andh 0x13f6,%r7,%r8
e8: 01 80 4b cd andh 0x8001,%r10,%r11
ec: e9 fd ae cd andh 0xfde9,%r13,%r14
f0: ff ff 11 ce andh 0xffff,%r16,%r17
f4: ff ff 74 ce andh 0xffff,%r19,%r20
f8: cd ab d7 ce andh 0xabcd,%r22,%r23
fc: 34 12 3a cf andh 0x1234,%r25,%r26
100: 00 00 9d cf andh 0x0000,%r28,%r29
104: 03 00 e0 cf andh 0x0003,%r31,%r0
108: 00 00 22 d4 andnot 0x0000,%r1,%sp
10c: 00 20 85 d4 andnot 0x2000,%r4,%r5
110: f5 13 e8 d4 andnot 0x13f5,%r7,%r8
114: 00 80 4b d5 andnot 0x8000,%r10,%r11
118: e8 fd ae d5 andnot 0xfde8,%r13,%r14
11c: ff ff 11 d6 andnot 0xffff,%r16,%r17
120: ff ff 74 d6 andnot 0xffff,%r19,%r20
124: cd ab d7 d6 andnot 0xabcd,%r22,%r23
128: 34 12 3a d7 andnot 0x1234,%r25,%r26
12c: 00 00 9d d7 andnot 0x0000,%r28,%r29
130: 03 00 e0 d7 andnot 0x0003,%r31,%r0
134: 01 00 22 dc andnoth 0x0001,%r1,%sp
138: 01 20 85 dc andnoth 0x2001,%r4,%r5
13c: f6 13 e8 dc andnoth 0x13f6,%r7,%r8
140: 01 80 4b dd andnoth 0x8001,%r10,%r11
144: e9 fd ae dd andnoth 0xfde9,%r13,%r14
148: ff ff 11 de andnoth 0xffff,%r16,%r17
14c: ff ff 74 de andnoth 0xffff,%r19,%r20
150: cd ab d7 de andnoth 0xabcd,%r22,%r23
154: 34 12 3a df andnoth 0x1234,%r25,%r26
158: 00 00 9d df andnoth 0x0000,%r28,%r29
15c: 03 00 e0 df andnoth 0x0003,%r31,%r0
160: 00 00 22 e4 or 0x0000,%r1,%sp
164: 01 00 85 e4 or 0x0001,%r4,%r5
168: 02 00 e8 e4 or 0x0002,%r7,%r8
16c: 03 00 4b e5 or 0x0003,%r10,%r11
170: e8 fd ae e5 or 0xfde8,%r13,%r14
174: ff ff 11 e6 or 0xffff,%r16,%r17
178: ff ff 74 e6 or 0xffff,%r19,%r20
17c: cd ab d7 e6 or 0xabcd,%r22,%r23
180: 34 12 3a e7 or 0x1234,%r25,%r26
184: 00 00 9d e7 or 0x0000,%r28,%r29
188: 03 00 e0 e7 or 0x0003,%r31,%r0
18c: 00 00 22 ec orh 0x0000,%r1,%sp
190: 01 00 85 ec orh 0x0001,%r4,%r5
194: 02 00 e8 ec orh 0x0002,%r7,%r8
198: 03 00 4b ed orh 0x0003,%r10,%r11
19c: e8 fd ae ed orh 0xfde8,%r13,%r14
1a0: ff ff 11 ee orh 0xffff,%r16,%r17
1a4: ff ff 74 ee orh 0xffff,%r19,%r20
1a8: cd ab d7 ee orh 0xabcd,%r22,%r23
1ac: 34 12 3a ef orh 0x1234,%r25,%r26
1b0: 00 00 9d ef orh 0x0000,%r28,%r29
1b4: 03 00 e0 ef orh 0x0003,%r31,%r0
1b8: 00 00 22 f4 xor 0x0000,%r1,%sp
1bc: 01 00 85 f4 xor 0x0001,%r4,%r5
1c0: 02 00 e8 f4 xor 0x0002,%r7,%r8
1c4: 03 00 4b f5 xor 0x0003,%r10,%r11
1c8: e8 fd ae f5 xor 0xfde8,%r13,%r14
1cc: ff ff 11 f6 xor 0xffff,%r16,%r17
1d0: ff ff 74 f6 xor 0xffff,%r19,%r20
1d4: cd ab d7 f6 xor 0xabcd,%r22,%r23
1d8: 34 12 3a f7 xor 0x1234,%r25,%r26
1dc: 00 00 9d f7 xor 0x0000,%r28,%r29
1e0: 03 00 e0 f7 xor 0x0003,%r31,%r0
1e4: 00 00 22 fc xorh 0x0000,%r1,%sp
1e8: 01 00 85 fc xorh 0x0001,%r4,%r5
1ec: 02 00 e8 fc xorh 0x0002,%r7,%r8
1f0: 03 00 4b fd xorh 0x0003,%r10,%r11
1f4: e8 fd ae fd xorh 0xfde8,%r13,%r14
1f8: ff ff 11 fe xorh 0xffff,%r16,%r17
1fc: ff ff 74 fe xorh 0xffff,%r19,%r20
200: cd ab d7 fe xorh 0xabcd,%r22,%r23
204: 34 12 3a ff xorh 0x1234,%r25,%r26
208: 00 00 9d ff xorh 0x0000,%r28,%r29
20c: 03 00 e0 ff xorh 0x0003,%r31,%r0

150
gas/testsuite/gas/i860/bitwise.s
View File

@ -1,150 +0,0 @@
# and, andh, andnot, andnoth, or, orh, xor, xorh
.text
# Register forms (high variants do not have register forms).
and %r0,%r1,%r2
and %r3,%r4,%r5
and %r6,%r7,%r8
and %r9,%r10,%r11
and %r12,%r13,%r14
and %r15,%r16,%r17
and %r18,%r19,%r20
and %r21,%r22,%r23
and %r24,%r25,%r26
and %r27,%r28,%r29
and %r30,%r31,%r0
andnot %r0,%r1,%r2
andnot %r3,%r4,%r5
andnot %r6,%r7,%r8
andnot %r9,%r10,%r11
andnot %r12,%r13,%r14
andnot %r15,%r16,%r17
andnot %r18,%r19,%r20
andnot %r21,%r22,%r23
andnot %r24,%r25,%r26
andnot %r27,%r28,%r29
andnot %r30,%r31,%r0
or %r0,%r1,%r2
or %r3,%r4,%r5
or %r6,%r7,%r8
or %r9,%r10,%r11
or %r12,%r13,%r14
or %r15,%r16,%r17
or %r18,%r19,%r20
or %r21,%r22,%r23
or %r24,%r25,%r26
or %r27,%r28,%r29
or %r30,%r31,%r0
xor %r0,%r1,%r2
xor %r3,%r4,%r5
xor %r6,%r7,%r8
xor %r9,%r10,%r11
xor %r12,%r13,%r14
xor %r15,%r16,%r17
xor %r18,%r19,%r20
xor %r21,%r22,%r23
xor %r24,%r25,%r26
xor %r27,%r28,%r29
xor %r30,%r31,%r0
# Immediate forms (all)
and 0,%r1,%r2
and 8192,%r4,%r5
and 5109,%r7,%r8
and 32768,%r10,%r11
and 65000,%r13,%r14
and 65535,%r16,%r17
and 0xffff,%r19,%r20
and 0xabcd,%r22,%r23
and 0x1234,%r25,%r26
and 0x0,%r28,%r29
and 0x3,%r31,%r0
andh 1,%r1,%r2
andh 8193,%r4,%r5
andh 5110,%r7,%r8
andh 32769,%r10,%r11
andh 65001,%r13,%r14
andh 65535,%r16,%r17
andh 0xffff,%r19,%r20
andh 0xabcd,%r22,%r23
andh 0x1234,%r25,%r26
andh 0x0,%r28,%r29
andh 0x3,%r31,%r0
andnot 0,%r1,%r2
andnot 8192,%r4,%r5
andnot 5109,%r7,%r8
andnot 32768,%r10,%r11
andnot 65000,%r13,%r14
andnot 65535,%r16,%r17
andnot 0xffff,%r19,%r20
andnot 0xabcd,%r22,%r23
andnot 0x1234,%r25,%r26
andnot 0x0,%r28,%r29
andnot 0x3,%r31,%r0
andnoth 1,%r1,%r2
andnoth 8193,%r4,%r5
andnoth 5110,%r7,%r8
andnoth 32769,%r10,%r11
andnoth 65001,%r13,%r14
andnoth 65535,%r16,%r17
andnoth 0xffff,%r19,%r20
andnoth 0xabcd,%r22,%r23
andnoth 0x1234,%r25,%r26
andnoth 0x0,%r28,%r29
andnoth 0x3,%r31,%r0
or 0,%r1,%r2
or 1,%r4,%r5
or 2,%r7,%r8
or 3,%r10,%r11
or 65000,%r13,%r14
or 65535,%r16,%r17
or 0xffff,%r19,%r20
or 0xabcd,%r22,%r23
or 0x1234,%r25,%r26
or 0x0,%r28,%r29
or 0x3,%r31,%r0
orh 0,%r1,%r2
orh 1,%r4,%r5
orh 2,%r7,%r8
orh 3,%r10,%r11
orh 65000,%r13,%r14
orh 65535,%r16,%r17
orh 0xffff,%r19,%r20
orh 0xabcd,%r22,%r23
orh 0x1234,%r25,%r26
orh 0x0,%r28,%r29
orh 0x3,%r31,%r0
xor 0,%r1,%r2
xor 1,%r4,%r5
xor 2,%r7,%r8
xor 3,%r10,%r11
xor 65000,%r13,%r14
xor 65535,%r16,%r17
xor 0xffff,%r19,%r20
xor 0xabcd,%r22,%r23
xor 0x1234,%r25,%r26
xor 0x0,%r28,%r29
xor 0x3,%r31,%r0
xorh 0,%r1,%r2
xorh 1,%r4,%r5
xorh 2,%r7,%r8
xorh 3,%r10,%r11
xorh 65000,%r13,%r14
xorh 65535,%r16,%r17
xorh 0xffff,%r19,%r20
xorh 0xabcd,%r22,%r23
xorh 0x1234,%r25,%r26
xorh 0x0,%r28,%r29
xorh 0x3,%r31,%r0

81
gas/testsuite/gas/i860/branch.d
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@ -1,81 +0,0 @@
#as:
#objdump: -dr
#name: i860 branch
.*: +file format .*
Disassembly of section .text:
00000000 <.text>:
0: 3d 00 20 b4 bla %r0,%r1,0x000000f8 // 0xf8
4: 00 00 00 a0 shl %r0,%r0,%r0
8: 3d 28 e0 b7 bla %r5,%r31,0x00000100 // 0x100
c: 00 00 00 a0 shl %r0,%r0,%r0
10: 39 b8 00 b6 bla %r23,%r16,0x000000f8 // 0xf8
14: 00 00 00 a0 shl %r0,%r0,%r0
18: 39 20 60 b6 bla %r4,%r19,0x00000100 // 0x100
1c: 00 00 00 a0 shl %r0,%r0,%r0
20: 00 00 00 40 bri %r0
24: 00 00 00 a0 shl %r0,%r0,%r0
28: 00 08 00 40 bri %r1
2c: 00 00 00 a0 shl %r0,%r0,%r0
30: 00 f8 00 40 bri %r31
34: 00 00 00 a0 shl %r0,%r0,%r0
38: 00 08 00 40 bri %r1
3c: 00 00 00 a0 shl %r0,%r0,%r0
40: 00 60 00 40 bri %r12
44: 00 00 00 a0 shl %r0,%r0,%r0
48: 00 98 00 40 bri %r19
4c: 00 00 00 a0 shl %r0,%r0,%r0
50: 02 00 00 4c calli %r0
54: 00 00 00 a0 shl %r0,%r0,%r0
58: 02 08 00 4c calli %r1
5c: 00 00 00 a0 shl %r0,%r0,%r0
60: 02 f8 00 4c calli %r31
64: 00 00 00 a0 shl %r0,%r0,%r0
68: 02 28 00 4c calli %r5
6c: 00 00 00 a0 shl %r0,%r0,%r0
70: 02 b0 00 4c calli %r22
74: 00 00 00 a0 shl %r0,%r0,%r0
78: 02 48 00 4c calli %r9
7c: 00 00 00 a0 shl %r0,%r0,%r0
80: 1d 00 00 68 br 0x000000f8 // 0xf8
84: 00 00 00 a0 shl %r0,%r0,%r0
88: 1d 00 00 68 br 0x00000100 // 0x100
8c: 00 00 00 a0 shl %r0,%r0,%r0
90: 00 00 00 68 br 0x00000094 // 0x94
90: R_860_PC26 some_fake_extern
94: 00 00 00 a0 shl %r0,%r0,%r0
98: 17 00 00 6c call 0x000000f8 // 0xf8
9c: 00 00 00 a0 shl %r0,%r0,%r0
a0: 17 00 00 6c call 0x00000100 // 0x100
a4: 00 00 00 a0 shl %r0,%r0,%r0
a8: 00 00 00 6c call 0x000000ac // 0xac
a8: R_860_PC26 some_fake_extern
ac: 00 00 00 a0 shl %r0,%r0,%r0
b0: 02 00 00 70 bc 0x000000bc // 0xbc
b4: 10 00 00 70 bc 0x000000f8 // 0xf8
b8: 00 00 00 70 bc 0x000000bc // 0xbc
b8: R_860_PC26 some_fake_extern
bc: ff ff ff 77 bc.t 0x000000bc // 0xbc
c0: 00 00 00 a0 shl %r0,%r0,%r0
c4: 0c 00 00 74 bc.t 0x000000f8 // 0xf8
c8: 00 00 00 a0 shl %r0,%r0,%r0
cc: 00 00 00 74 bc.t 0x000000d0 // 0xd0
cc: R_860_PC26 some_fake_extern
d0: 00 00 00 a0 shl %r0,%r0,%r0
d4: 02 00 00 78 bnc 0x000000e0 // 0xe0
d8: 07 00 00 78 bnc 0x000000f8 // 0xf8
dc: 00 00 00 78 bnc 0x000000e0 // 0xe0
dc: R_860_PC26 some_fake_extern
e0: ff ff ff 7f bnc.t 0x000000e0 // 0xe0
e4: 00 00 00 a0 shl %r0,%r0,%r0
e8: 03 00 00 7c bnc.t 0x000000f8 // 0xf8
ec: 00 00 00 a0 shl %r0,%r0,%r0
f0: 00 00 00 7c bnc.t 0x000000f4 // 0xf4
f0: R_860_PC26 some_fake_extern
f4: 00 00 00 a0 shl %r0,%r0,%r0
f8: 00 00 00 a0 shl %r0,%r0,%r0
fc: 00 00 00 a0 shl %r0,%r0,%r0
100: 00 00 00 a0 shl %r0,%r0,%r0
104: 00 00 00 a0 shl %r0,%r0,%r0

85
gas/testsuite/gas/i860/branch.s
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@ -1,85 +0,0 @@
# Branches and calls
.text
bla %r0,%r1,.Lsome_label1
nop
bla %r5,%r31,.Lsome_label2
nop
bla %r23,%r16,.Lsome_label1
nop
bla %r4,%r19,.Lsome_label2
nop
bri %r0
nop
bri %r1
nop
bri %r31
nop
bri %r1
nop
bri %r12
nop
bri %r19
nop
calli %r0
nop
calli %r1
nop
calli %r31
nop
calli %r5
nop
calli %r22
nop
calli %r9
nop
br .Lsome_label1
nop
br .Lsome_label2
nop
br some_fake_extern
nop
call .Lcall_me_now
nop
call .Lcall_me_anytime
nop
call some_fake_extern
nop
bc .+12
bc .Lsome_label1
bc some_fake_extern
bc.t .+0
nop
bc.t .Lsome_label1
nop
bc.t some_fake_extern
nop
bnc .+12
bnc .Lsome_label1
bnc some_fake_extern
bnc.t .+0
nop
bnc.t .Lsome_label1
nop
bnc.t some_fake_extern
nop
.Lsome_label1:
.Lcall_me_now:
nop
nop
.Lsome_label2:
.Lcall_me_anytime:
nop
nop

62
gas/testsuite/gas/i860/bte.d
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@ -1,62 +0,0 @@
#as:
#objdump: -dr
#name: i860 bte/btne
.*: +file format .*
Disassembly of section \.text:
00000000 <some_label-0xb8>:
0: 2d 00 e0 57 btne 0,%r31,0x000000b8 // b8 <some_label>
4: 2c 08 a0 57 btne 1,%r29,0x000000b8 // b8 <some_label>
8: 2b 10 60 57 btne 2,%r27,0x000000b8 // b8 <some_label>
c: 2a 18 20 57 btne 3,%r25,0x000000b8 // b8 <some_label>
10: 29 50 e0 56 btne 10,%r23,0x000000b8 // b8 <some_label>
14: 28 58 a0 56 btne 11,%r21,0x000000b8 // b8 <some_label>
18: 27 60 60 56 btne 12,%r19,0x000000b8 // b8 <some_label>
1c: 26 e8 20 56 btne 29,%r17,0x000000b8 // b8 <some_label>
20: 25 f0 00 56 btne 30,%r16,0x000000b8 // b8 <some_label>
24: 24 f8 00 55 btne 31,%r8,0x000000b8 // b8 <some_label>
28: 00 78 00 54 btne 15,%r0,0x0000002c // 2c <some_label-0x8c>
28: R_860_PC16 some_fake_extern
2c: 22 00 e0 5f bte 0,%r31,0x000000b8 // b8 <some_label>
30: 21 08 a0 5f bte 1,%r29,0x000000b8 // b8 <some_label>
34: 20 10 60 5f bte 2,%r27,0x000000b8 // b8 <some_label>
38: 1f 18 20 5f bte 3,%r25,0x000000b8 // b8 <some_label>
3c: 1e 50 e0 5e bte 10,%r23,0x000000b8 // b8 <some_label>
40: 1d 58 a0 5e bte 11,%r21,0x000000b8 // b8 <some_label>
44: 1c 60 60 5e bte 12,%r19,0x000000b8 // b8 <some_label>
48: 1b e8 20 5e bte 29,%r17,0x000000b8 // b8 <some_label>
4c: 1a f0 00 5e bte 30,%r16,0x000000b8 // b8 <some_label>
50: 19 f8 00 5d bte 31,%r8,0x000000b8 // b8 <some_label>
54: 00 78 00 5c bte 15,%r0,0x00000058 // 58 <some_label-0x60>
54: R_860_PC16 some_fake_extern
58: 17 00 e0 53 btne %r0,%r31,0x000000b8 // b8 <some_label>
5c: 16 08 a0 53 btne %r1,%r29,0x000000b8 // b8 <some_label>
60: 15 10 60 53 btne %sp,%r27,0x000000b8 // b8 <some_label>
64: 14 18 20 53 btne %fp,%r25,0x000000b8 // b8 <some_label>
68: 13 50 e0 52 btne %r10,%r23,0x000000b8 // b8 <some_label>
6c: 12 58 a0 52 btne %r11,%r21,0x000000b8 // b8 <some_label>
70: 11 60 60 52 btne %r12,%r19,0x000000b8 // b8 <some_label>
74: 10 e8 20 52 btne %r29,%r17,0x000000b8 // b8 <some_label>
78: 0f f0 00 52 btne %r30,%r16,0x000000b8 // b8 <some_label>
7c: 0e f8 00 51 btne %r31,%r8,0x000000b8 // b8 <some_label>
80: 00 78 00 50 btne %r15,%r0,0x00000084 // 84 <some_label-0x34>
80: R_860_PC16 some_fake_extern
84: 0c 00 e0 5b bte %r0,%r31,0x000000b8 // b8 <some_label>
88: 0b 08 a0 5b bte %r1,%r29,0x000000b8 // b8 <some_label>
8c: 0a 10 60 5b bte %sp,%r27,0x000000b8 // b8 <some_label>
90: 09 18 20 5b bte %fp,%r25,0x000000b8 // b8 <some_label>
94: 08 50 e0 5a bte %r10,%r23,0x000000b8 // b8 <some_label>
98: 07 58 a0 5a bte %r11,%r21,0x000000b8 // b8 <some_label>
9c: 06 60 60 5a bte %r12,%r19,0x000000b8 // b8 <some_label>
a0: 05 e8 20 5a bte %r29,%r17,0x000000b8 // b8 <some_label>
a4: 04 f0 00 5a bte %r30,%r16,0x000000b8 // b8 <some_label>
a8: 03 f8 00 59 bte %r31,%r8,0x000000b8 // b8 <some_label>
ac: 00 78 00 58 bte %r15,%r0,0x000000b0 // b0 <some_label-0x8>
ac: R_860_PC16 some_fake_extern
b0: 00 00 00 a0 shl %r0,%r0,%r0
b4: 00 00 00 a0 shl %r0,%r0,%r0
000000b8 <some_label>:
b8: 00 00 00 a0 shl %r0,%r0,%r0

55
gas/testsuite/gas/i860/bte.s
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@ -1,55 +0,0 @@
# bte, btne
.text
btne 0,%r31,some_label
btne 1,%r29,some_label
btne 2,%r27,some_label
btne 3,%r25,some_label
btne 10,%r23,some_label
btne 11,%r21,some_label
btne 12,%r19,some_label
btne 29,%r17,some_label
btne 30,%r16,some_label
btne 31,%r8,some_label
btne 15,%r0,some_fake_extern
bte 0,%r31,some_label
bte 1,%r29,some_label
bte 2,%r27,some_label
bte 3,%r25,some_label
bte 10,%r23,some_label
bte 11,%r21,some_label
bte 12,%r19,some_label
bte 29,%r17,some_label
bte 30,%r16,some_label
bte 31,%r8,some_label
bte 15,%r0,some_fake_extern
btne %r0,%r31,some_label
btne %r1,%r29,some_label
btne %r2,%r27,some_label
btne %r3,%r25,some_label
btne %r10,%r23,some_label
btne %r11,%r21,some_label
btne %r12,%r19,some_label
btne %r29,%r17,some_label
btne %r30,%r16,some_label
btne %r31,%r8,some_label
btne %r15,%r0,some_fake_extern
bte %r0,%r31,some_label
bte %r1,%r29,some_label
bte %r2,%r27,some_label
bte %r3,%r25,some_label
bte %r10,%r23,some_label
bte %r11,%r21,some_label
bte %r12,%r19,some_label
bte %r29,%r17,some_label
bte %r30,%r16,some_label
bte %r31,%r8,some_label
bte %r15,%r0,some_fake_extern
nop
nop
some_label:
nop

17
gas/testsuite/gas/i860/dir-align01.d
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@ -1,17 +0,0 @@
#as:
#objdump: -d
#name: i860 dir-align01
.*: +file format .*
Disassembly of section \.text:
00000000 <\.text>:
0: 00 20 a6 90 adds %r4,%r5,%r6
4: 00 00 00 a0 shl %r0,%r0,%r0
8: 00 00 00 a0 shl %r0,%r0,%r0
c: 00 00 00 a0 shl %r0,%r0,%r0
10: 00 50 6c 91 adds %r10,%r11,%r12
14: a1 b1 1a 4b fmlow.dd %f22,%f24,%f26
18: 30 74 f0 49 pfadd.ss %f14,%f15,%f16
1c: b0 8c 54 4a pfadd.sd %f17,%f18,%f20

11
gas/testsuite/gas/i860/dir-align01.s
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@ -1,11 +0,0 @@
# Test that .text section alignments use nops (0xA0000000) to fill
# rather than 0.
.text
adds %r4,%r5,%r6
.align 16
adds %r10,%r11,%r12
fmlow.dd %f22,%f24,%f26
pfadd.ss %f14,%f15,%f16
pfadd.sd %f17,%f18,%f20

19
gas/testsuite/gas/i860/dir-intel01.d
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@ -1,19 +0,0 @@
#as: -mintel-syntax
#objdump: -d
#name: i860 dir-intel01
.*: +file format .*
Disassembly of section \.text:
00000000 <\.text>:
0: 00 00 00 a0 shl %r0,%r0,%r0
4: 00 00 00 a0 shl %r0,%r0,%r0
8: 30 02 22 48 d.fadd.ss %f0,%f1,%f2
c: 00 00 00 a0 shl %r0,%r0,%r0
10: b0 12 64 48 d.fadd.sd %f2,%f3,%f4
14: 00 00 00 a0 shl %r0,%r0,%r0
18: b0 33 0a 49 d.fadd.dd %f6,%f8,%f10
1c: 00 00 00 a0 shl %r0,%r0,%r0
20: 00 00 00 a0 shl %r0,%r0,%r0
24: 00 00 00 a0 shl %r0,%r0,%r0

19
gas/testsuite/gas/i860/dir-intel01.s
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@ -1,19 +0,0 @@
// Intel assembler directives:
// Test that the .dual and .enddual directives are recognized and
// function (i.e., that the dual bits are set properly).
.text
nop
nop
.dual
fadd.ss f0,f1,f2
nop
fadd.sd f2,f3,f4
nop
fadd.dd f6,f8,f10
nop
.enddual
nop
nop

15
gas/testsuite/gas/i860/dir-intel02.d
View File

@ -1,15 +0,0 @@
#as: -mintel-syntax
#objdump: -d
#name: i860 dir-intel02
.*: +file format .*
Disassembly of section \.text:
00000000 <\.text>:
0: 34 12 1f ec orh 0x1234,%r0,%r31
4: 78 56 f8 e7 or 0x5678,%r31,%r24
8: 00 c0 28 91 adds %r24,%r9,%r8
c: f0 f0 05 ec orh 0xf0f0,%r0,%r5
10: 5a 5a b8 e4 or 0x5a5a,%r5,%r24
14: 00 c0 28 91 adds %r24,%r9,%r8

13
gas/testsuite/gas/i860/dir-intel02.s
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@ -1,13 +0,0 @@
// Intel assembler directives:
// Test that the .atmp directive is recognized and functions.
.text
.atmp r31
or 0x12345678,r0,r24
adds r24,r9,r8
.atmp r5
or 0xf0f05a5a,r0,r24
adds r24,r9,r8

5
gas/testsuite/gas/i860/dir-intel03-err.l
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@ -1,5 +0,0 @@
.*: Assembler messages:
.*:8: Error: Directive .atmp available only with -mintel-syntax option
.*:8: Error: junk at end of line, first unrecognized character is `r'
.*:10: Error: Directive .dual available only with -mintel-syntax option
.*:13: Error: Directive .enddual available only with -mintel-syntax option

14
gas/testsuite/gas/i860/dir-intel03-err.s
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@ -1,14 +0,0 @@
# Intel assembler directives:
# The .dual, .enddual, and .atmp directives are valid only
# in Intel syntax mode. Check that we issue an error if in
# AT&T/SVR4 mode.
.text
.atmp r31
.dual
fsub.ss %f22,%f21,%f13
nop
.enddual

21
gas/testsuite/gas/i860/dual01.d
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@ -1,21 +0,0 @@
#as:
#objdump: -d
#name: i860 dual01
.*: +file format .*
Disassembly of section \.text:
00000000 <\.text>:
0: 00 00 00 a0 shl %r0,%r0,%r0
4: 00 00 00 a0 shl %r0,%r0,%r0
8: b0 47 4c 49 d.pfadd.dd %f8,%f10,%f12
c: 00 28 c6 90 adds %r5,%r6,%r6
10: b0 47 4c 49 d.pfadd.dd %f8,%f10,%f12
14: 10 00 58 25 fld.d 16\(%r10\),%f24
18: 00 02 00 b0 d.shrd %r0,%r0,%r0
1c: 08 00 48 25 fld.d 8\(%r10\),%f8
20: 00 02 00 b0 d.shrd %r0,%r0,%r0
24: 00 00 50 25 fld.d 0\(%r10\),%f16
28: 00 00 00 a0 shl %r0,%r0,%r0
2c: 00 00 00 a0 shl %r0,%r0,%r0

17
gas/testsuite/gas/i860/dual01.s
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@ -1,17 +0,0 @@
# Test fnop's dual bit (all other floating point operations have their dual
# bit tested in their individual test files).
.text
.align 8
nop
nop
d.pfadd.dd %f8,%f10,%f12
adds %r5,%r6,%r6
d.pfadd.dd %f8,%f10,%f12
fld.d 16(%r10),%f24
d.fnop
fld.d 8(%r10),%f8
d.fnop
fld.d 0(%r10),%f16
nop
nop

2
gas/testsuite/gas/i860/dual02-err.l
View File

@ -1,2 +0,0 @@
.*: Assembler messages:
.*:7: Error: 'd\.fadd\.ss' must be 8-byte aligned

9
gas/testsuite/gas/i860/dual02-err.s
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@ -1,9 +0,0 @@
# Dual-mode pairs must be aligned on an 8-byte boundary. This tests
# that an error is reported if not properly aligned.
.text
.align 8
nop
d.fadd.ss %f3,%f5,%f7
addu %r4,%r5,%r6

53
gas/testsuite/gas/i860/dual03.d
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@ -1,53 +0,0 @@
#as: -mintel-syntax
#objdump: -d
#name: i860 dual03
.*: +file format .*
Disassembly of section \.text:
00000000 <L1-0x20>:
0: 00 00 14 22 fld.d %r0\(%r16\),%f20
4: fe ff 15 94 adds -2,%r0,%r21
8: 30 06 00 48 d.pfadd.ss %f0,%f0,%f0
c: fa ff 31 96 adds -6,%r17,%r17
10: 30 06 00 48 d.pfadd.ss %f0,%f0,%f0
14: 02 a8 20 b6 bla %r21,%r17,0x00000020 // 20 <L1>
18: 30 06 00 48 d.pfadd.ss %f0,%f0,%f0
1c: 09 00 16 26 fld.d 8\(%r16\)\+\+,%f22
00000020 <L1>:
20: 30 a6 de 4b d.pfadd.ss %f20,%f30,%f30
24: 06 a8 20 b6 bla %r21,%r17,0x00000040 // 40 <L2>
28: 30 ae ff 4b d.pfadd.ss %f21,%f31,%f31
2c: 09 00 14 26 fld.d 8\(%r16\)\+\+,%f20
30: 30 a6 de 4b d.pfadd.ss %f20,%f30,%f30
34: 0a 00 00 68 br 0x00000060 // 60 <S>
38: 30 ae ff 4b d.pfadd.ss %f21,%f31,%f31
3c: 00 00 00 a0 shl %r0,%r0,%r0
00000040 <L2>:
40: 30 b6 de 4b d.pfadd.ss %f22,%f30,%f30
44: f6 af 3f b6 bla %r21,%r17,0x00000020 // 20 <L1>
48: 30 be ff 4b d.pfadd.ss %f23,%f31,%f31
4c: 09 00 16 26 fld.d 8\(%r16\)\+\+,%f22
50: 30 a6 de 4b d.pfadd.ss %f20,%f30,%f30
54: 00 00 00 a0 shl %r0,%r0,%r0
58: 30 ae ff 4b d.pfadd.ss %f21,%f31,%f31
5c: 00 00 00 a0 shl %r0,%r0,%r0
00000060 <S>:
60: 30 b4 de 4b pfadd.ss %f22,%f30,%f30
64: fc ff 15 94 adds -4,%r0,%r21
68: 30 bc ff 4b pfadd.ss %f23,%f31,%f31
6c: 02 a8 20 5a bte %r21,%r17,0x00000078 // 78 <DONE>
70: 0b 00 14 26 fld.l 8\(%r16\)\+\+,%f20
74: 30 a4 de 4b pfadd.ss %f20,%f30,%f30
00000078 <DONE>:
78: 30 04 1e 48 pfadd.ss %f0,%f0,%f30
7c: 30 f4 ff 4b pfadd.ss %f30,%f31,%f31
80: 30 04 1e 48 pfadd.ss %f0,%f0,%f30
84: 30 04 00 48 pfadd.ss %f0,%f0,%f0
88: 30 04 1f 48 pfadd.ss %f0,%f0,%f31
8c: 30 f0 f0 4b fadd.ss %f30,%f31,%f16

46
gas/testsuite/gas/i860/dual03.s
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@ -1,46 +0,0 @@
// A larger dual-mode test, from the programmer's reference manual.
// This uses Intel syntax, as in the manual.
// Single-precision vector sum
fld.d r0(r16),f20
mov -2,r21
d.pfadd.ss f0,f0,f0
adds -6,r17,r17
d.pfadd.ss f0,f0,f0
bla r21,r17,L1
d.pfadd.ss f0,f0,f0
fld.d 8(r16)++,f22
L1:
d.pfadd.ss f20,f30,f30
bla r21,r17,L2
d.pfadd.ss f21,f31,f31
fld.d 8(r16)++,f20
d.pfadd.ss f20,f30,f30
br S
d.pfadd.ss f21,f31,f31
nop
L2:
d.pfadd.ss f22,f30,f30
bla r21,r17,L1
d.pfadd.ss f23,f31,f31
fld.d 8(r16)++,f22
d.pfadd.ss f20,f30,f30
nop
d.pfadd.ss f21,f31,f31
nop
S:
pfadd.ss f22,f30,f30
mov -4,r21
pfadd.ss f23,f31,f31
bte r21,r17,DONE
fld.l 8(r16)++,f20
pfadd.ss f20,f30,f30
DONE:
pfadd.ss f0,f0,f30
pfadd.ss f30,f31,f31
pfadd.ss f0,f0,f30
pfadd.ss f0,f0,f0
pfadd.ss f0,f0,f31
fadd.ss f30,f31,f16

73
gas/testsuite/gas/i860/fldst01.d
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@ -1,73 +0,0 @@
#as:
#objdump: -dr
#name: i860 fldst01 (fld.l)
.*: +file format .*
Disassembly of section \.text:
00000000 <\.text>:
0: 02 00 00 24 fld.l 0\(%r0\),%f0
4: 7e 00 3f 24 fld.l 124\(%r1\),%f31
8: 02 01 5e 24 fld.l 256\(%sp\),%f30
c: 02 02 7d 24 fld.l 512\(%fp\),%f29
10: 02 04 9c 24 fld.l 1024\(%r4\),%f28
14: 02 10 bb 24 fld.l 4096\(%r5\),%f27
18: 02 20 da 24 fld.l 8192\(%r6\),%f26
1c: 02 40 f9 24 fld.l 16384\(%r7\),%f25
20: fe 7f f9 24 fld.l 32764\(%r7\),%f25
24: 02 80 f7 24 fld.l -32768\(%r7\),%f23
28: 02 c0 02 25 fld.l -16384\(%r8\),%f2
2c: 02 e0 23 25 fld.l -8192\(%r9\),%f3
30: 02 f0 48 25 fld.l -4096\(%r10\),%f8
34: 02 fc 69 25 fld.l -1024\(%r11\),%f9
38: 06 fe 8c 25 fld.l -508\(%r12\),%f12
3c: 0a ff b3 25 fld.l -248\(%r13\),%f19
40: fe ff d5 25 fld.l -4\(%r14\),%f21
44: 03 00 00 24 fld.l 0\(%r0\)\+\+,%f0
48: 7f 00 21 24 fld.l 124\(%r1\)\+\+,%f1
4c: 03 01 42 24 fld.l 256\(%sp\)\+\+,%f2
50: 03 02 63 24 fld.l 512\(%fp\)\+\+,%f3
54: 03 04 84 24 fld.l 1024\(%r4\)\+\+,%f4
58: 03 10 a5 24 fld.l 4096\(%r5\)\+\+,%f5
5c: 03 20 c6 24 fld.l 8192\(%r6\)\+\+,%f6
60: 03 40 e7 24 fld.l 16384\(%r7\)\+\+,%f7
64: ff 7f e8 24 fld.l 32764\(%r7\)\+\+,%f8
68: 03 80 e9 24 fld.l -32768\(%r7\)\+\+,%f9
6c: 03 c0 0a 25 fld.l -16384\(%r8\)\+\+,%f10
70: 03 e0 2b 25 fld.l -8192\(%r9\)\+\+,%f11
74: 03 f0 4c 25 fld.l -4096\(%r10\)\+\+,%f12
78: 03 fc 6d 25 fld.l -1024\(%r11\)\+\+,%f13
7c: 07 fe 8e 25 fld.l -508\(%r12\)\+\+,%f14
80: 0b ff af 25 fld.l -248\(%r13\)\+\+,%f15
84: ff ff d0 25 fld.l -4\(%r14\)\+\+,%f16
88: 02 28 00 20 fld.l %r5\(%r0\),%f0
8c: 02 30 3f 20 fld.l %r6\(%r1\),%f31
90: 02 38 5e 20 fld.l %r7\(%sp\),%f30
94: 02 40 7d 20 fld.l %r8\(%fp\),%f29
98: 02 48 9c 20 fld.l %r9\(%r4\),%f28
9c: 02 00 bb 20 fld.l %r0\(%r5\),%f27
a0: 02 08 da 20 fld.l %r1\(%r6\),%f26
a4: 02 60 f9 20 fld.l %r12\(%r7\),%f25
a8: 02 68 18 21 fld.l %r13\(%r8\),%f24
ac: 02 70 37 21 fld.l %r14\(%r9\),%f23
b0: 02 78 56 21 fld.l %r15\(%r10\),%f22
b4: 02 80 75 21 fld.l %r16\(%r11\),%f21
b8: 02 88 94 21 fld.l %r17\(%r12\),%f20
bc: 02 e0 b3 21 fld.l %r28\(%r13\),%f19
c0: 02 f8 d2 21 fld.l %r31\(%r14\),%f18
c4: 03 28 00 20 fld.l %r5\(%r0\)\+\+,%f0
c8: 03 30 21 20 fld.l %r6\(%r1\)\+\+,%f1
cc: 03 38 42 20 fld.l %r7\(%sp\)\+\+,%f2
d0: 03 40 63 20 fld.l %r8\(%fp\)\+\+,%f3
d4: 03 48 84 20 fld.l %r9\(%r4\)\+\+,%f4
d8: 03 00 a5 20 fld.l %r0\(%r5\)\+\+,%f5
dc: 03 08 c6 20 fld.l %r1\(%r6\)\+\+,%f6
e0: 03 60 e7 20 fld.l %r12\(%r7\)\+\+,%f7
e4: 03 68 08 21 fld.l %r13\(%r8\)\+\+,%f8
e8: 03 70 29 21 fld.l %r14\(%r9\)\+\+,%f9
ec: 03 78 4a 21 fld.l %r15\(%r10\)\+\+,%f10
f0: 03 80 6b 21 fld.l %r16\(%r11\)\+\+,%f11
f4: 03 88 8c 21 fld.l %r17\(%r12\)\+\+,%f12
f8: 03 e0 ad 21 fld.l %r28\(%r13\)\+\+,%f13
fc: 03 f8 ce 21 fld.l %r31\(%r14\)\+\+,%f14

75
gas/testsuite/gas/i860/fldst01.s
View File

@ -1,75 +0,0 @@
# fld.l (no relocations here)
.text
# Immediate form, no auto-increment.
fld.l 0(%r0),%f0
fld.l 124(%r1),%f31
fld.l 256(%r2),%f30
fld.l 512(%r3),%f29
fld.l 1024(%r4),%f28
fld.l 4096(%r5),%f27
fld.l 8192(%r6),%f26
fld.l 16384(%r7),%f25
fld.l 32764(%r7),%f25
fld.l -32768(%r7),%f23
fld.l -16384(%r8),%f2
fld.l -8192(%r9),%f3
fld.l -4096(%r10),%f8
fld.l -1024(%r11),%f9
fld.l -508(%r12),%f12
fld.l -248(%r13),%f19
fld.l -4(%r14),%f21
# Immediate form, with auto-increment.
fld.l 0(%r0)++,%f0
fld.l 124(%r1)++,%f1
fld.l 256(%r2)++,%f2
fld.l 512(%r3)++,%f3
fld.l 1024(%r4)++,%f4
fld.l 4096(%r5)++,%f5
fld.l 8192(%r6)++,%f6
fld.l 16384(%r7)++,%f7
fld.l 32764(%r7)++,%f8
fld.l -32768(%r7)++,%f9
fld.l -16384(%r8)++,%f10
fld.l -8192(%r9)++,%f11
fld.l -4096(%r10)++,%f12
fld.l -1024(%r11)++,%f13
fld.l -508(%r12)++,%f14
fld.l -248(%r13)++,%f15
fld.l -4(%r14)++,%f16
# Index form, no auto-increment.
fld.l %r5(%r0),%f0
fld.l %r6(%r1),%f31
fld.l %r7(%r2),%f30
fld.l %r8(%r3),%f29
fld.l %r9(%r4),%f28
fld.l %r0(%r5),%f27
fld.l %r1(%r6),%f26
fld.l %r12(%r7),%f25
fld.l %r13(%r8),%f24
fld.l %r14(%r9),%f23
fld.l %r15(%r10),%f22
fld.l %r16(%r11),%f21
fld.l %r17(%r12),%f20
fld.l %r28(%r13),%f19
fld.l %r31(%r14),%f18
# Index form, with auto-increment.
fld.l %r5(%r0)++,%f0
fld.l %r6(%r1)++,%f1
fld.l %r7(%r2)++,%f2
fld.l %r8(%r3)++,%f3
fld.l %r9(%r4)++,%f4
fld.l %r0(%r5)++,%f5
fld.l %r1(%r6)++,%f6
fld.l %r12(%r7)++,%f7
fld.l %r13(%r8)++,%f8
fld.l %r14(%r9)++,%f9
fld.l %r15(%r10)++,%f10
fld.l %r16(%r11)++,%f11
fld.l %r17(%r12)++,%f12
fld.l %r28(%r13)++,%f13
fld.l %r31(%r14)++,%f14

73
gas/testsuite/gas/i860/fldst02.d
View File

@ -1,73 +0,0 @@
#as:
#objdump: -dr
#name: i860 fldst02 (fld.d)
.*: +file format .*
Disassembly of section \.text:
00000000 <\.text>:
0: 00 00 00 24 fld.d 0\(%r0\),%f0
4: 80 00 3e 24 fld.d 128\(%r1\),%f30
8: 00 01 5c 24 fld.d 256\(%sp\),%f28
c: 00 02 7a 24 fld.d 512\(%fp\),%f26
10: 00 04 98 24 fld.d 1024\(%r4\),%f24
14: 00 10 b6 24 fld.d 4096\(%r5\),%f22
18: 00 20 d4 24 fld.d 8192\(%r6\),%f20
1c: 00 40 f2 24 fld.d 16384\(%r7\),%f18
20: f8 7f f0 24 fld.d 32760\(%r7\),%f16
24: 00 80 ee 24 fld.d -32768\(%r7\),%f14
28: 00 c0 0c 25 fld.d -16384\(%r8\),%f12
2c: 00 e0 2a 25 fld.d -8192\(%r9\),%f10
30: 00 f0 48 25 fld.d -4096\(%r10\),%f8
34: 00 fc 66 25 fld.d -1024\(%r11\),%f6
38: 00 fe 84 25 fld.d -512\(%r12\),%f4
3c: 08 ff a2 25 fld.d -248\(%r13\),%f2
40: f8 ff c0 25 fld.d -8\(%r14\),%f0
44: 01 00 00 24 fld.d 0\(%r0\)\+\+,%f0
48: 81 00 22 24 fld.d 128\(%r1\)\+\+,%f2
4c: 01 01 44 24 fld.d 256\(%sp\)\+\+,%f4
50: 01 02 66 24 fld.d 512\(%fp\)\+\+,%f6
54: 01 04 88 24 fld.d 1024\(%r4\)\+\+,%f8
58: 01 10 aa 24 fld.d 4096\(%r5\)\+\+,%f10
5c: 01 20 cc 24 fld.d 8192\(%r6\)\+\+,%f12
60: 01 40 ee 24 fld.d 16384\(%r7\)\+\+,%f14
64: f9 7f f0 24 fld.d 32760\(%r7\)\+\+,%f16
68: 01 80 f2 24 fld.d -32768\(%r7\)\+\+,%f18
6c: 01 c0 14 25 fld.d -16384\(%r8\)\+\+,%f20
70: 01 e0 36 25 fld.d -8192\(%r9\)\+\+,%f22
74: 01 f0 58 25 fld.d -4096\(%r10\)\+\+,%f24
78: 01 fc 7a 25 fld.d -1024\(%r11\)\+\+,%f26
7c: 01 fe 9c 25 fld.d -512\(%r12\)\+\+,%f28
80: 09 ff be 25 fld.d -248\(%r13\)\+\+,%f30
84: f9 ff d0 25 fld.d -8\(%r14\)\+\+,%f16
88: 00 28 00 20 fld.d %r5\(%r0\),%f0
8c: 00 30 3e 20 fld.d %r6\(%r1\),%f30
90: 00 38 5c 20 fld.d %r7\(%sp\),%f28
94: 00 40 7a 20 fld.d %r8\(%fp\),%f26
98: 00 48 98 20 fld.d %r9\(%r4\),%f24
9c: 00 00 b6 20 fld.d %r0\(%r5\),%f22
a0: 00 08 d4 20 fld.d %r1\(%r6\),%f20
a4: 00 60 f2 20 fld.d %r12\(%r7\),%f18
a8: 00 68 10 21 fld.d %r13\(%r8\),%f16
ac: 00 70 2e 21 fld.d %r14\(%r9\),%f14
b0: 00 78 4c 21 fld.d %r15\(%r10\),%f12
b4: 00 80 6a 21 fld.d %r16\(%r11\),%f10
b8: 00 88 88 21 fld.d %r17\(%r12\),%f8
bc: 00 e0 a6 21 fld.d %r28\(%r13\),%f6
c0: 00 f8 c4 21 fld.d %r31\(%r14\),%f4
c4: 01 28 00 20 fld.d %r5\(%r0\)\+\+,%f0
c8: 01 30 22 20 fld.d %r6\(%r1\)\+\+,%f2
cc: 01 38 44 20 fld.d %r7\(%sp\)\+\+,%f4
d0: 01 40 66 20 fld.d %r8\(%fp\)\+\+,%f6
d4: 01 48 88 20 fld.d %r9\(%r4\)\+\+,%f8
d8: 01 00 aa 20 fld.d %r0\(%r5\)\+\+,%f10
dc: 01 08 cc 20 fld.d %r1\(%r6\)\+\+,%f12
e0: 01 60 ee 20 fld.d %r12\(%r7\)\+\+,%f14
e4: 01 68 10 21 fld.d %r13\(%r8\)\+\+,%f16
e8: 01 70 32 21 fld.d %r14\(%r9\)\+\+,%f18
ec: 01 78 54 21 fld.d %r15\(%r10\)\+\+,%f20
f0: 01 80 76 21 fld.d %r16\(%r11\)\+\+,%f22
f4: 01 88 98 21 fld.d %r17\(%r12\)\+\+,%f24
f8: 01 e0 ba 21 fld.d %r28\(%r13\)\+\+,%f26
fc: 01 f8 de 21 fld.d %r31\(%r14\)\+\+,%f30

75
gas/testsuite/gas/i860/fldst02.s
View File

@ -1,75 +0,0 @@
# fld.d (no relocations here)
.text
# Immediate form, no auto-increment.
fld.d 0(%r0),%f0
fld.d 128(%r1),%f30
fld.d 256(%r2),%f28
fld.d 512(%r3),%f26
fld.d 1024(%r4),%f24
fld.d 4096(%r5),%f22
fld.d 8192(%r6),%f20
fld.d 16384(%r7),%f18
fld.d 32760(%r7),%f16
fld.d -32768(%r7),%f14
fld.d -16384(%r8),%f12
fld.d -8192(%r9),%f10
fld.d -4096(%r10),%f8
fld.d -1024(%r11),%f6
fld.d -512(%r12),%f4
fld.d -248(%r13),%f2
fld.d -8(%r14),%f0
# Immediate form, with auto-increment.
fld.d 0(%r0)++,%f0
fld.d 128(%r1)++,%f2
fld.d 256(%r2)++,%f4
fld.d 512(%r3)++,%f6
fld.d 1024(%r4)++,%f8
fld.d 4096(%r5)++,%f10
fld.d 8192(%r6)++,%f12
fld.d 16384(%r7)++,%f14
fld.d 32760(%r7)++,%f16
fld.d -32768(%r7)++,%f18
fld.d -16384(%r8)++,%f20
fld.d -8192(%r9)++,%f22
fld.d -4096(%r10)++,%f24
fld.d -1024(%r11)++,%f26
fld.d -512(%r12)++,%f28
fld.d -248(%r13)++,%f30
fld.d -8(%r14)++,%f16
# Index form, no auto-increment.
fld.d %r5(%r0),%f0
fld.d %r6(%r1),%f30
fld.d %r7(%r2),%f28
fld.d %r8(%r3),%f26
fld.d %r9(%r4),%f24
fld.d %r0(%r5),%f22
fld.d %r1(%r6),%f20
fld.d %r12(%r7),%f18
fld.d %r13(%r8),%f16
fld.d %r14(%r9),%f14
fld.d %r15(%r10),%f12
fld.d %r16(%r11),%f10
fld.d %r17(%r12),%f8
fld.d %r28(%r13),%f6
fld.d %r31(%r14),%f4
# Index form, with auto-increment.
fld.d %r5(%r0)++,%f0
fld.d %r6(%r1)++,%f2
fld.d %r7(%r2)++,%f4
fld.d %r8(%r3)++,%f6
fld.d %r9(%r4)++,%f8
fld.d %r0(%r5)++,%f10
fld.d %r1(%r6)++,%f12
fld.d %r12(%r7)++,%f14
fld.d %r13(%r8)++,%f16
fld.d %r14(%r9)++,%f18
fld.d %r15(%r10)++,%f20
fld.d %r16(%r11)++,%f22
fld.d %r17(%r12)++,%f24
fld.d %r28(%r13)++,%f26
fld.d %r31(%r14)++,%f30

73
gas/testsuite/gas/i860/fldst03.d
View File

@ -1,73 +0,0 @@
#as:
#objdump: -dr
#name: i860 fldst03 (fld.q)
.*: +file format .*
Disassembly of section \.text:
00000000 <\.text>:
0: 04 00 00 24 fld.q 0\(%r0\),%f0
4: 84 00 3c 24 fld.q 128\(%r1\),%f28
8: 04 01 58 24 fld.q 256\(%sp\),%f24
c: 04 02 74 24 fld.q 512\(%fp\),%f20
10: 04 04 90 24 fld.q 1024\(%r4\),%f16
14: 04 10 ac 24 fld.q 4096\(%r5\),%f12
18: 04 20 c8 24 fld.q 8192\(%r6\),%f8
1c: 04 40 e4 24 fld.q 16384\(%r7\),%f4
20: f4 7f e0 24 fld.q 32752\(%r7\),%f0
24: 04 80 fc 24 fld.q -32768\(%r7\),%f28
28: 04 c0 18 25 fld.q -16384\(%r8\),%f24
2c: 04 e0 34 25 fld.q -8192\(%r9\),%f20
30: 04 f0 50 25 fld.q -4096\(%r10\),%f16
34: 04 fc 6c 25 fld.q -1024\(%r11\),%f12
38: 04 fe 88 25 fld.q -512\(%r12\),%f8
3c: 04 ff a4 25 fld.q -256\(%r13\),%f4
40: f4 ff c0 25 fld.q -16\(%r14\),%f0
44: 05 00 00 24 fld.q 0\(%r0\)\+\+,%f0
48: 85 00 24 24 fld.q 128\(%r1\)\+\+,%f4
4c: 05 01 48 24 fld.q 256\(%sp\)\+\+,%f8
50: 05 02 6c 24 fld.q 512\(%fp\)\+\+,%f12
54: 05 04 90 24 fld.q 1024\(%r4\)\+\+,%f16
58: 05 10 b4 24 fld.q 4096\(%r5\)\+\+,%f20
5c: 05 20 d8 24 fld.q 8192\(%r6\)\+\+,%f24
60: 05 40 fc 24 fld.q 16384\(%r7\)\+\+,%f28
64: f5 7f e0 24 fld.q 32752\(%r7\)\+\+,%f0
68: 05 80 e4 24 fld.q -32768\(%r7\)\+\+,%f4
6c: 05 c0 08 25 fld.q -16384\(%r8\)\+\+,%f8
70: 05 e0 2c 25 fld.q -8192\(%r9\)\+\+,%f12
74: 05 f0 50 25 fld.q -4096\(%r10\)\+\+,%f16
78: 05 fc 74 25 fld.q -1024\(%r11\)\+\+,%f20
7c: 05 fe 98 25 fld.q -512\(%r12\)\+\+,%f24
80: 05 ff bc 25 fld.q -256\(%r13\)\+\+,%f28
84: f5 ff d0 25 fld.q -16\(%r14\)\+\+,%f16
88: 04 28 00 20 fld.q %r5\(%r0\),%f0
8c: 04 30 34 20 fld.q %r6\(%r1\),%f20
90: 04 38 50 20 fld.q %r7\(%sp\),%f16
94: 04 40 6c 20 fld.q %r8\(%fp\),%f12
98: 04 48 88 20 fld.q %r9\(%r4\),%f8
9c: 04 00 a4 20 fld.q %r0\(%r5\),%f4
a0: 04 08 c0 20 fld.q %r1\(%r6\),%f0
a4: 04 60 fc 20 fld.q %r12\(%r7\),%f28
a8: 04 68 18 21 fld.q %r13\(%r8\),%f24
ac: 04 70 34 21 fld.q %r14\(%r9\),%f20
b0: 04 78 50 21 fld.q %r15\(%r10\),%f16
b4: 04 80 6c 21 fld.q %r16\(%r11\),%f12
b8: 04 88 88 21 fld.q %r17\(%r12\),%f8
bc: 04 e0 a4 21 fld.q %r28\(%r13\),%f4
c0: 04 f8 c0 21 fld.q %r31\(%r14\),%f0
c4: 05 28 00 20 fld.q %r5\(%r0\)\+\+,%f0
c8: 05 30 24 20 fld.q %r6\(%r1\)\+\+,%f4
cc: 05 38 48 20 fld.q %r7\(%sp\)\+\+,%f8
d0: 05 40 6c 20 fld.q %r8\(%fp\)\+\+,%f12
d4: 05 48 90 20 fld.q %r9\(%r4\)\+\+,%f16
d8: 05 00 b4 20 fld.q %r0\(%r5\)\+\+,%f20
dc: 05 08 d8 20 fld.q %r1\(%r6\)\+\+,%f24
e0: 05 60 fc 20 fld.q %r12\(%r7\)\+\+,%f28
e4: 05 68 00 21 fld.q %r13\(%r8\)\+\+,%f0
e8: 05 70 24 21 fld.q %r14\(%r9\)\+\+,%f4
ec: 05 78 48 21 fld.q %r15\(%r10\)\+\+,%f8
f0: 05 80 6c 21 fld.q %r16\(%r11\)\+\+,%f12
f4: 05 88 90 21 fld.q %r17\(%r12\)\+\+,%f16
f8: 05 e0 b4 21 fld.q %r28\(%r13\)\+\+,%f20
fc: 05 f8 d8 21 fld.q %r31\(%r14\)\+\+,%f24

75
gas/testsuite/gas/i860/fldst03.s
View File

@ -1,75 +0,0 @@
# fld.q (no relocations here)
.text
# Immediate form, no auto-increment.
fld.q 0(%r0),%f0
fld.q 128(%r1),%f28
fld.q 256(%r2),%f24
fld.q 512(%r3),%f20
fld.q 1024(%r4),%f16
fld.q 4096(%r5),%f12
fld.q 8192(%r6),%f8
fld.q 16384(%r7),%f4
fld.q 32752(%r7),%f0
fld.q -32768(%r7),%f28
fld.q -16384(%r8),%f24
fld.q -8192(%r9),%f20
fld.q -4096(%r10),%f16
fld.q -1024(%r11),%f12
fld.q -512(%r12),%f8
fld.q -256(%r13),%f4
fld.q -16(%r14),%f0
# Immediate form, with auto-increment.
fld.q 0(%r0)++,%f0
fld.q 128(%r1)++,%f4
fld.q 256(%r2)++,%f8
fld.q 512(%r3)++,%f12
fld.q 1024(%r4)++,%f16
fld.q 4096(%r5)++,%f20
fld.q 8192(%r6)++,%f24
fld.q 16384(%r7)++,%f28
fld.q 32752(%r7)++,%f0
fld.q -32768(%r7)++,%f4
fld.q -16384(%r8)++,%f8
fld.q -8192(%r9)++,%f12
fld.q -4096(%r10)++,%f16
fld.q -1024(%r11)++,%f20
fld.q -512(%r12)++,%f24
fld.q -256(%r13)++,%f28
fld.q -16(%r14)++,%f16
# Index form, no auto-increment.
fld.q %r5(%r0),%f0
fld.q %r6(%r1),%f20
fld.q %r7(%r2),%f16
fld.q %r8(%r3),%f12
fld.q %r9(%r4),%f8
fld.q %r0(%r5),%f4
fld.q %r1(%r6),%f0
fld.q %r12(%r7),%f28
fld.q %r13(%r8),%f24
fld.q %r14(%r9),%f20
fld.q %r15(%r10),%f16
fld.q %r16(%r11),%f12
fld.q %r17(%r12),%f8
fld.q %r28(%r13),%f4
fld.q %r31(%r14),%f0
# Index form, with auto-increment.
fld.q %r5(%r0)++,%f0
fld.q %r6(%r1)++,%f4
fld.q %r7(%r2)++,%f8
fld.q %r8(%r3)++,%f12
fld.q %r9(%r4)++,%f16
fld.q %r0(%r5)++,%f20
fld.q %r1(%r6)++,%f24
fld.q %r12(%r7)++,%f28
fld.q %r13(%r8)++,%f0
fld.q %r14(%r9)++,%f4
fld.q %r15(%r10)++,%f8
fld.q %r16(%r11)++,%f12
fld.q %r17(%r12)++,%f16
fld.q %r28(%r13)++,%f20
fld.q %r31(%r14)++,%f24

73
gas/testsuite/gas/i860/fldst04.d
View File

@ -1,73 +0,0 @@
#as:
#objdump: -dr
#name: i860 fldst04 (fst.l)
.*: +file format .*
Disassembly of section \.text:
00000000 <\.text>:
0: 02 00 00 2c fst.l %f0,0\(%r0\)
4: 7e 00 3f 2c fst.l %f31,124\(%r1\)
8: 02 01 5e 2c fst.l %f30,256\(%sp\)
c: 02 02 7d 2c fst.l %f29,512\(%fp\)
10: 02 04 9c 2c fst.l %f28,1024\(%r4\)
14: 02 10 bb 2c fst.l %f27,4096\(%r5\)
18: 02 20 da 2c fst.l %f26,8192\(%r6\)
1c: 02 40 f9 2c fst.l %f25,16384\(%r7\)
20: fe 7f f9 2c fst.l %f25,32764\(%r7\)
24: 02 80 f7 2c fst.l %f23,-32768\(%r7\)
28: 02 c0 02 2d fst.l %f2,-16384\(%r8\)
2c: 02 e0 23 2d fst.l %f3,-8192\(%r9\)
30: 02 f0 48 2d fst.l %f8,-4096\(%r10\)
34: 02 fc 69 2d fst.l %f9,-1024\(%r11\)
38: 06 fe 8c 2d fst.l %f12,-508\(%r12\)
3c: 0a ff b3 2d fst.l %f19,-248\(%r13\)
40: fe ff d5 2d fst.l %f21,-4\(%r14\)
44: 03 00 00 2c fst.l %f0,0\(%r0\)\+\+
48: 7f 00 21 2c fst.l %f1,124\(%r1\)\+\+
4c: 03 01 42 2c fst.l %f2,256\(%sp\)\+\+
50: 03 02 63 2c fst.l %f3,512\(%fp\)\+\+
54: 03 04 84 2c fst.l %f4,1024\(%r4\)\+\+
58: 03 10 a5 2c fst.l %f5,4096\(%r5\)\+\+
5c: 03 20 c6 2c fst.l %f6,8192\(%r6\)\+\+
60: 03 40 e7 2c fst.l %f7,16384\(%r7\)\+\+
64: ff 7f e8 2c fst.l %f8,32764\(%r7\)\+\+
68: 03 80 e9 2c fst.l %f9,-32768\(%r7\)\+\+
6c: 03 c0 0a 2d fst.l %f10,-16384\(%r8\)\+\+
70: 03 e0 2b 2d fst.l %f11,-8192\(%r9\)\+\+
74: 03 f0 4c 2d fst.l %f12,-4096\(%r10\)\+\+
78: 03 fc 6d 2d fst.l %f13,-1024\(%r11\)\+\+
7c: 07 fe 8e 2d fst.l %f14,-508\(%r12\)\+\+
80: 0b ff af 2d fst.l %f15,-248\(%r13\)\+\+
84: ff ff d0 2d fst.l %f16,-4\(%r14\)\+\+
88: 02 28 00 28 fst.l %f0,%r5\(%r0\)
8c: 02 30 3f 28 fst.l %f31,%r6\(%r1\)
90: 02 38 5e 28 fst.l %f30,%r7\(%sp\)
94: 02 40 7d 28 fst.l %f29,%r8\(%fp\)
98: 02 48 9c 28 fst.l %f28,%r9\(%r4\)
9c: 02 00 bb 28 fst.l %f27,%r0\(%r5\)
a0: 02 08 da 28 fst.l %f26,%r1\(%r6\)
a4: 02 60 f9 28 fst.l %f25,%r12\(%r7\)
a8: 02 68 18 29 fst.l %f24,%r13\(%r8\)
ac: 02 70 37 29 fst.l %f23,%r14\(%r9\)
b0: 02 78 56 29 fst.l %f22,%r15\(%r10\)
b4: 02 80 75 29 fst.l %f21,%r16\(%r11\)
b8: 02 88 94 29 fst.l %f20,%r17\(%r12\)
bc: 02 e0 b3 29 fst.l %f19,%r28\(%r13\)
c0: 02 f8 d2 29 fst.l %f18,%r31\(%r14\)
c4: 03 28 00 28 fst.l %f0,%r5\(%r0\)\+\+
c8: 03 30 21 28 fst.l %f1,%r6\(%r1\)\+\+
cc: 03 38 42 28 fst.l %f2,%r7\(%sp\)\+\+
d0: 03 40 63 28 fst.l %f3,%r8\(%fp\)\+\+
d4: 03 48 84 28 fst.l %f4,%r9\(%r4\)\+\+
d8: 03 00 a5 28 fst.l %f5,%r0\(%r5\)\+\+
dc: 03 08 c6 28 fst.l %f6,%r1\(%r6\)\+\+
e0: 03 60 e7 28 fst.l %f7,%r12\(%r7\)\+\+
e4: 03 68 08 29 fst.l %f8,%r13\(%r8\)\+\+
e8: 03 70 29 29 fst.l %f9,%r14\(%r9\)\+\+
ec: 03 78 4a 29 fst.l %f10,%r15\(%r10\)\+\+
f0: 03 80 6b 29 fst.l %f11,%r16\(%r11\)\+\+
f4: 03 88 8c 29 fst.l %f12,%r17\(%r12\)\+\+
f8: 03 e0 ad 29 fst.l %f13,%r28\(%r13\)\+\+
fc: 03 f8 ce 29 fst.l %f14,%r31\(%r14\)\+\+

75
gas/testsuite/gas/i860/fldst04.s
View File

@ -1,75 +0,0 @@
# fst.l (no relocations here)
.text
# Immediate form, no auto-increment.
fst.l %f0,0(%r0)
fst.l %f31,124(%r1)
fst.l %f30,256(%r2)
fst.l %f29,512(%r3)
fst.l %f28,1024(%r4)
fst.l %f27,4096(%r5)
fst.l %f26,8192(%r6)
fst.l %f25,16384(%r7)
fst.l %f25,32764(%r7)
fst.l %f23,-32768(%r7)
fst.l %f2,-16384(%r8)
fst.l %f3,-8192(%r9)
fst.l %f8,-4096(%r10)
fst.l %f9,-1024(%r11)
fst.l %f12,-508(%r12)
fst.l %f19,-248(%r13)
fst.l %f21,-4(%r14)
# Immediate form, with auto-increment.
fst.l %f0,0(%r0)++
fst.l %f1,124(%r1)++
fst.l %f2,256(%r2)++
fst.l %f3,512(%r3)++
fst.l %f4,1024(%r4)++
fst.l %f5,4096(%r5)++
fst.l %f6,8192(%r6)++
fst.l %f7,16384(%r7)++
fst.l %f8,32764(%r7)++
fst.l %f9,-32768(%r7)++
fst.l %f10,-16384(%r8)++
fst.l %f11,-8192(%r9)++
fst.l %f12,-4096(%r10)++
fst.l %f13,-1024(%r11)++
fst.l %f14,-508(%r12)++
fst.l %f15,-248(%r13)++
fst.l %f16,-4(%r14)++
# Index form, no auto-increment.
fst.l %f0,%r5(%r0)
fst.l %f31,%r6(%r1)
fst.l %f30,%r7(%r2)
fst.l %f29,%r8(%r3)
fst.l %f28,%r9(%r4)
fst.l %f27,%r0(%r5)
fst.l %f26,%r1(%r6)
fst.l %f25,%r12(%r7)
fst.l %f24,%r13(%r8)
fst.l %f23,%r14(%r9)
fst.l %f22,%r15(%r10)
fst.l %f21,%r16(%r11)
fst.l %f20,%r17(%r12)
fst.l %f19,%r28(%r13)
fst.l %f18,%r31(%r14)
# Index form, with auto-increment.
fst.l %f0,%r5(%r0)++
fst.l %f1,%r6(%r1)++
fst.l %f2,%r7(%r2)++
fst.l %f3,%r8(%r3)++
fst.l %f4,%r9(%r4)++
fst.l %f5,%r0(%r5)++
fst.l %f6,%r1(%r6)++
fst.l %f7,%r12(%r7)++
fst.l %f8,%r13(%r8)++
fst.l %f9,%r14(%r9)++
fst.l %f10,%r15(%r10)++
fst.l %f11,%r16(%r11)++
fst.l %f12,%r17(%r12)++
fst.l %f13,%r28(%r13)++
fst.l %f14,%r31(%r14)++

73
gas/testsuite/gas/i860/fldst05.d
View File

@ -1,73 +0,0 @@
#as:
#objdump: -dr
#name: i860 fldst05 (fst.d)
.*: +file format .*
Disassembly of section \.text:
00000000 <\.text>:
0: 00 00 00 2c fst.d %f0,0\(%r0\)
4: 80 00 3e 2c fst.d %f30,128\(%r1\)
8: 00 01 5c 2c fst.d %f28,256\(%sp\)
c: 00 02 7a 2c fst.d %f26,512\(%fp\)
10: 00 04 98 2c fst.d %f24,1024\(%r4\)
14: 00 10 b6 2c fst.d %f22,4096\(%r5\)
18: 00 20 d4 2c fst.d %f20,8192\(%r6\)
1c: 00 40 f2 2c fst.d %f18,16384\(%r7\)
20: f8 7f f0 2c fst.d %f16,32760\(%r7\)
24: 00 80 ee 2c fst.d %f14,-32768\(%r7\)
28: 00 c0 0c 2d fst.d %f12,-16384\(%r8\)
2c: 00 e0 2a 2d fst.d %f10,-8192\(%r9\)
30: 00 f0 48 2d fst.d %f8,-4096\(%r10\)
34: 00 fc 66 2d fst.d %f6,-1024\(%r11\)
38: 00 fe 84 2d fst.d %f4,-512\(%r12\)
3c: 08 ff a2 2d fst.d %f2,-248\(%r13\)
40: f8 ff c0 2d fst.d %f0,-8\(%r14\)
44: 01 00 00 2c fst.d %f0,0\(%r0\)\+\+
48: 81 00 22 2c fst.d %f2,128\(%r1\)\+\+
4c: 01 01 44 2c fst.d %f4,256\(%sp\)\+\+
50: 01 02 66 2c fst.d %f6,512\(%fp\)\+\+
54: 01 04 88 2c fst.d %f8,1024\(%r4\)\+\+
58: 01 10 aa 2c fst.d %f10,4096\(%r5\)\+\+
5c: 01 20 cc 2c fst.d %f12,8192\(%r6\)\+\+
60: 01 40 ee 2c fst.d %f14,16384\(%r7\)\+\+
64: f9 7f f0 2c fst.d %f16,32760\(%r7\)\+\+
68: 01 80 f2 2c fst.d %f18,-32768\(%r7\)\+\+
6c: 01 c0 14 2d fst.d %f20,-16384\(%r8\)\+\+
70: 01 e0 36 2d fst.d %f22,-8192\(%r9\)\+\+
74: 01 f0 58 2d fst.d %f24,-4096\(%r10\)\+\+
78: 01 fc 7a 2d fst.d %f26,-1024\(%r11\)\+\+
7c: 01 fe 9c 2d fst.d %f28,-512\(%r12\)\+\+
80: 09 ff be 2d fst.d %f30,-248\(%r13\)\+\+
84: f9 ff d0 2d fst.d %f16,-8\(%r14\)\+\+
88: 00 28 00 28 fst.d %f0,%r5\(%r0\)
8c: 00 30 3e 28 fst.d %f30,%r6\(%r1\)
90: 00 38 5c 28 fst.d %f28,%r7\(%sp\)
94: 00 40 7a 28 fst.d %f26,%r8\(%fp\)
98: 00 48 98 28 fst.d %f24,%r9\(%r4\)
9c: 00 00 b6 28 fst.d %f22,%r0\(%r5\)
a0: 00 08 d4 28 fst.d %f20,%r1\(%r6\)
a4: 00 60 f2 28 fst.d %f18,%r12\(%r7\)
a8: 00 68 10 29 fst.d %f16,%r13\(%r8\)
ac: 00 70 2e 29 fst.d %f14,%r14\(%r9\)
b0: 00 78 4c 29 fst.d %f12,%r15\(%r10\)
b4: 00 80 6a 29 fst.d %f10,%r16\(%r11\)
b8: 00 88 88 29 fst.d %f8,%r17\(%r12\)
bc: 00 e0 a6 29 fst.d %f6,%r28\(%r13\)
c0: 00 f8 c4 29 fst.d %f4,%r31\(%r14\)
c4: 01 28 00 28 fst.d %f0,%r5\(%r0\)\+\+
c8: 01 30 22 28 fst.d %f2,%r6\(%r1\)\+\+
cc: 01 38 44 28 fst.d %f4,%r7\(%sp\)\+\+
d0: 01 40 66 28 fst.d %f6,%r8\(%fp\)\+\+
d4: 01 48 88 28 fst.d %f8,%r9\(%r4\)\+\+
d8: 01 00 aa 28 fst.d %f10,%r0\(%r5\)\+\+
dc: 01 08 cc 28 fst.d %f12,%r1\(%r6\)\+\+
e0: 01 60 ee 28 fst.d %f14,%r12\(%r7\)\+\+
e4: 01 68 10 29 fst.d %f16,%r13\(%r8\)\+\+
e8: 01 70 32 29 fst.d %f18,%r14\(%r9\)\+\+
ec: 01 78 54 29 fst.d %f20,%r15\(%r10\)\+\+
f0: 01 80 76 29 fst.d %f22,%r16\(%r11\)\+\+
f4: 01 88 98 29 fst.d %f24,%r17\(%r12\)\+\+
f8: 01 e0 ba 29 fst.d %f26,%r28\(%r13\)\+\+
fc: 01 f8 de 29 fst.d %f30,%r31\(%r14\)\+\+

75
gas/testsuite/gas/i860/fldst05.s
View File

@ -1,75 +0,0 @@
# fst.d (no relocations here)
.text
# Immediate form, no auto-increment.
fst.d %f0,0(%r0)
fst.d %f30,128(%r1)
fst.d %f28,256(%r2)
fst.d %f26,512(%r3)
fst.d %f24,1024(%r4)
fst.d %f22,4096(%r5)
fst.d %f20,8192(%r6)
fst.d %f18,16384(%r7)
fst.d %f16,32760(%r7)
fst.d %f14,-32768(%r7)
fst.d %f12,-16384(%r8)
fst.d %f10,-8192(%r9)
fst.d %f8,-4096(%r10)
fst.d %f6,-1024(%r11)
fst.d %f4,-512(%r12)
fst.d %f2,-248(%r13)
fst.d %f0,-8(%r14)
# Immediate form, with auto-increment.
fst.d %f0,0(%r0)++
fst.d %f2,128(%r1)++
fst.d %f4,256(%r2)++
fst.d %f6,512(%r3)++
fst.d %f8,1024(%r4)++
fst.d %f10,4096(%r5)++
fst.d %f12,8192(%r6)++
fst.d %f14,16384(%r7)++
fst.d %f16,32760(%r7)++
fst.d %f18,-32768(%r7)++
fst.d %f20,-16384(%r8)++
fst.d %f22,-8192(%r9)++
fst.d %f24,-4096(%r10)++
fst.d %f26,-1024(%r11)++
fst.d %f28,-512(%r12)++
fst.d %f30,-248(%r13)++
fst.d %f16,-8(%r14)++
# Index form, no auto-increment.
fst.d %f0,%r5(%r0)
fst.d %f30,%r6(%r1)
fst.d %f28,%r7(%r2)
fst.d %f26,%r8(%r3)
fst.d %f24,%r9(%r4)
fst.d %f22,%r0(%r5)
fst.d %f20,%r1(%r6)
fst.d %f18,%r12(%r7)
fst.d %f16,%r13(%r8)
fst.d %f14,%r14(%r9)
fst.d %f12,%r15(%r10)
fst.d %f10,%r16(%r11)
fst.d %f8,%r17(%r12)
fst.d %f6,%r28(%r13)
fst.d %f4,%r31(%r14)
# Index form, with auto-increment.
fst.d %f0,%r5(%r0)++
fst.d %f2,%r6(%r1)++
fst.d %f4,%r7(%r2)++
fst.d %f6,%r8(%r3)++
fst.d %f8,%r9(%r4)++
fst.d %f10,%r0(%r5)++
fst.d %f12,%r1(%r6)++
fst.d %f14,%r12(%r7)++
fst.d %f16,%r13(%r8)++
fst.d %f18,%r14(%r9)++
fst.d %f20,%r15(%r10)++
fst.d %f22,%r16(%r11)++
fst.d %f24,%r17(%r12)++
fst.d %f26,%r28(%r13)++
fst.d %f30,%r31(%r14)++

73
gas/testsuite/gas/i860/fldst06.d
View File

@ -1,73 +0,0 @@
#as:
#objdump: -dr
#name: i860 fldst06 (fst.q)
.*: +file format .*
Disassembly of section \.text:
00000000 <\.text>:
0: 04 00 00 2c fst.q %f0,0\(%r0\)
4: 84 00 3c 2c fst.q %f28,128\(%r1\)
8: 04 01 58 2c fst.q %f24,256\(%sp\)
c: 04 02 74 2c fst.q %f20,512\(%fp\)
10: 04 04 90 2c fst.q %f16,1024\(%r4\)
14: 04 10 ac 2c fst.q %f12,4096\(%r5\)
18: 04 20 c8 2c fst.q %f8,8192\(%r6\)
1c: 04 40 e4 2c fst.q %f4,16384\(%r7\)
20: f4 7f e0 2c fst.q %f0,32752\(%r7\)
24: 04 80 fc 2c fst.q %f28,-32768\(%r7\)
28: 04 c0 18 2d fst.q %f24,-16384\(%r8\)
2c: 04 e0 34 2d fst.q %f20,-8192\(%r9\)
30: 04 f0 50 2d fst.q %f16,-4096\(%r10\)
34: 04 fc 6c 2d fst.q %f12,-1024\(%r11\)
38: 04 fe 88 2d fst.q %f8,-512\(%r12\)
3c: 04 ff a4 2d fst.q %f4,-256\(%r13\)
40: f4 ff c0 2d fst.q %f0,-16\(%r14\)
44: 05 00 00 2c fst.q %f0,0\(%r0\)\+\+
48: 85 00 24 2c fst.q %f4,128\(%r1\)\+\+
4c: 05 01 48 2c fst.q %f8,256\(%sp\)\+\+
50: 05 02 6c 2c fst.q %f12,512\(%fp\)\+\+
54: 05 04 90 2c fst.q %f16,1024\(%r4\)\+\+
58: 05 10 b4 2c fst.q %f20,4096\(%r5\)\+\+
5c: 05 20 d8 2c fst.q %f24,8192\(%r6\)\+\+
60: 05 40 fc 2c fst.q %f28,16384\(%r7\)\+\+
64: f5 7f e0 2c fst.q %f0,32752\(%r7\)\+\+
68: 05 80 e4 2c fst.q %f4,-32768\(%r7\)\+\+
6c: 05 c0 08 2d fst.q %f8,-16384\(%r8\)\+\+
70: 05 e0 2c 2d fst.q %f12,-8192\(%r9\)\+\+
74: 05 f0 50 2d fst.q %f16,-4096\(%r10\)\+\+
78: 05 fc 74 2d fst.q %f20,-1024\(%r11\)\+\+
7c: 05 fe 98 2d fst.q %f24,-512\(%r12\)\+\+
80: 05 ff bc 2d fst.q %f28,-256\(%r13\)\+\+
84: f5 ff d0 2d fst.q %f16,-16\(%r14\)\+\+
88: 04 28 00 28 fst.q %f0,%r5\(%r0\)
8c: 04 30 34 28 fst.q %f20,%r6\(%r1\)
90: 04 38 50 28 fst.q %f16,%r7\(%sp\)
94: 04 40 6c 28 fst.q %f12,%r8\(%fp\)
98: 04 48 88 28 fst.q %f8,%r9\(%r4\)
9c: 04 00 a4 28 fst.q %f4,%r0\(%r5\)
a0: 04 08 c0 28 fst.q %f0,%r1\(%r6\)
a4: 04 60 fc 28 fst.q %f28,%r12\(%r7\)
a8: 04 68 18 29 fst.q %f24,%r13\(%r8\)
ac: 04 70 34 29 fst.q %f20,%r14\(%r9\)
b0: 04 78 50 29 fst.q %f16,%r15\(%r10\)
b4: 04 80 6c 29 fst.q %f12,%r16\(%r11\)
b8: 04 88 88 29 fst.q %f8,%r17\(%r12\)
bc: 04 e0 a4 29 fst.q %f4,%r28\(%r13\)
c0: 04 f8 c0 29 fst.q %f0,%r31\(%r14\)
c4: 05 28 00 28 fst.q %f0,%r5\(%r0\)\+\+
c8: 05 30 24 28 fst.q %f4,%r6\(%r1\)\+\+
cc: 05 38 48 28 fst.q %f8,%r7\(%sp\)\+\+
d0: 05 40 6c 28 fst.q %f12,%r8\(%fp\)\+\+
d4: 05 48 90 28 fst.q %f16,%r9\(%r4\)\+\+
d8: 05 00 b4 28 fst.q %f20,%r0\(%r5\)\+\+
dc: 05 08 d8 28 fst.q %f24,%r1\(%r6\)\+\+
e0: 05 60 fc 28 fst.q %f28,%r12\(%r7\)\+\+
e4: 05 68 00 29 fst.q %f0,%r13\(%r8\)\+\+
e8: 05 70 24 29 fst.q %f4,%r14\(%r9\)\+\+
ec: 05 78 48 29 fst.q %f8,%r15\(%r10\)\+\+
f0: 05 80 6c 29 fst.q %f12,%r16\(%r11\)\+\+
f4: 05 88 90 29 fst.q %f16,%r17\(%r12\)\+\+
f8: 05 e0 b4 29 fst.q %f20,%r28\(%r13\)\+\+
fc: 05 f8 d8 29 fst.q %f24,%r31\(%r14\)\+\+

75
gas/testsuite/gas/i860/fldst06.s
View File

@ -1,75 +0,0 @@
# fst.q (no relocations here)
.text
# Immediate form, no auto-increment.
fst.q %f0,0(%r0)
fst.q %f28,128(%r1)
fst.q %f24,256(%r2)
fst.q %f20,512(%r3)
fst.q %f16,1024(%r4)
fst.q %f12,4096(%r5)
fst.q %f8,8192(%r6)
fst.q %f4,16384(%r7)
fst.q %f0,32752(%r7)
fst.q %f28,-32768(%r7)
fst.q %f24,-16384(%r8)
fst.q %f20,-8192(%r9)
fst.q %f16,-4096(%r10)
fst.q %f12,-1024(%r11)
fst.q %f8,-512(%r12)
fst.q %f4,-256(%r13)
fst.q %f0,-16(%r14)
# Immediate form, with auto-increment.
fst.q %f0,0(%r0)++
fst.q %f4,128(%r1)++
fst.q %f8,256(%r2)++
fst.q %f12,512(%r3)++
fst.q %f16,1024(%r4)++
fst.q %f20,4096(%r5)++
fst.q %f24,8192(%r6)++
fst.q %f28,16384(%r7)++
fst.q %f0,32752(%r7)++
fst.q %f4,-32768(%r7)++
fst.q %f8,-16384(%r8)++
fst.q %f12,-8192(%r9)++
fst.q %f16,-4096(%r10)++
fst.q %f20,-1024(%r11)++
fst.q %f24,-512(%r12)++
fst.q %f28,-256(%r13)++
fst.q %f16,-16(%r14)++
# Index form, no auto-increment.
fst.q %f0,%r5(%r0)
fst.q %f20,%r6(%r1)
fst.q %f16,%r7(%r2)
fst.q %f12,%r8(%r3)
fst.q %f8,%r9(%r4)
fst.q %f4,%r0(%r5)
fst.q %f0,%r1(%r6)
fst.q %f28,%r12(%r7)
fst.q %f24,%r13(%r8)
fst.q %f20,%r14(%r9)
fst.q %f16,%r15(%r10)
fst.q %f12,%r16(%r11)
fst.q %f8,%r17(%r12)
fst.q %f4,%r28(%r13)
fst.q %f0,%r31(%r14)
# Index form, with auto-increment.
fst.q %f0,%r5(%r0)++
fst.q %f4,%r6(%r1)++
fst.q %f8,%r7(%r2)++
fst.q %f12,%r8(%r3)++
fst.q %f16,%r9(%r4)++
fst.q %f20,%r0(%r5)++
fst.q %f24,%r1(%r6)++
fst.q %f28,%r12(%r7)++
fst.q %f0,%r13(%r8)++
fst.q %f4,%r14(%r9)++
fst.q %f8,%r15(%r10)++
fst.q %f12,%r16(%r11)++
fst.q %f16,%r17(%r12)++
fst.q %f20,%r28(%r13)++
fst.q %f24,%r31(%r14)++

73
gas/testsuite/gas/i860/fldst07.d
View File

@ -1,73 +0,0 @@
#as:
#objdump: -dr
#name: i860 fldst07 (pfld.l)
.*: +file format .*
Disassembly of section \.text:
00000000 <\.text>:
0: 02 00 00 64 pfld.l 0\(%r0\),%f0
4: 7e 00 3f 64 pfld.l 124\(%r1\),%f31
8: 02 01 5e 64 pfld.l 256\(%sp\),%f30
c: 02 02 7d 64 pfld.l 512\(%fp\),%f29
10: 02 04 9c 64 pfld.l 1024\(%r4\),%f28
14: 02 10 bb 64 pfld.l 4096\(%r5\),%f27
18: 02 20 da 64 pfld.l 8192\(%r6\),%f26
1c: 02 40 f9 64 pfld.l 16384\(%r7\),%f25
20: fe 7f f9 64 pfld.l 32764\(%r7\),%f25
24: 02 80 f7 64 pfld.l -32768\(%r7\),%f23
28: 02 c0 02 65 pfld.l -16384\(%r8\),%f2
2c: 02 e0 23 65 pfld.l -8192\(%r9\),%f3
30: 02 f0 48 65 pfld.l -4096\(%r10\),%f8
34: 02 fc 69 65 pfld.l -1024\(%r11\),%f9
38: 06 fe 8c 65 pfld.l -508\(%r12\),%f12
3c: 0a ff b3 65 pfld.l -248\(%r13\),%f19
40: fe ff d5 65 pfld.l -4\(%r14\),%f21
44: 03 00 00 64 pfld.l 0\(%r0\)\+\+,%f0
48: 7f 00 21 64 pfld.l 124\(%r1\)\+\+,%f1
4c: 03 01 42 64 pfld.l 256\(%sp\)\+\+,%f2
50: 03 02 63 64 pfld.l 512\(%fp\)\+\+,%f3
54: 03 04 84 64 pfld.l 1024\(%r4\)\+\+,%f4
58: 03 10 a5 64 pfld.l 4096\(%r5\)\+\+,%f5
5c: 03 20 c6 64 pfld.l 8192\(%r6\)\+\+,%f6
60: 03 40 e7 64 pfld.l 16384\(%r7\)\+\+,%f7
64: ff 7f e8 64 pfld.l 32764\(%r7\)\+\+,%f8
68: 03 80 e9 64 pfld.l -32768\(%r7\)\+\+,%f9
6c: 03 c0 0a 65 pfld.l -16384\(%r8\)\+\+,%f10
70: 03 e0 2b 65 pfld.l -8192\(%r9\)\+\+,%f11
74: 03 f0 4c 65 pfld.l -4096\(%r10\)\+\+,%f12
78: 03 fc 6d 65 pfld.l -1024\(%r11\)\+\+,%f13
7c: 07 fe 8e 65 pfld.l -508\(%r12\)\+\+,%f14
80: 0b ff af 65 pfld.l -248\(%r13\)\+\+,%f15
84: ff ff d0 65 pfld.l -4\(%r14\)\+\+,%f16
88: 02 28 00 60 pfld.l %r5\(%r0\),%f0
8c: 02 30 3f 60 pfld.l %r6\(%r1\),%f31
90: 02 38 5e 60 pfld.l %r7\(%sp\),%f30
94: 02 40 7d 60 pfld.l %r8\(%fp\),%f29
98: 02 48 9c 60 pfld.l %r9\(%r4\),%f28
9c: 02 00 bb 60 pfld.l %r0\(%r5\),%f27
a0: 02 08 da 60 pfld.l %r1\(%r6\),%f26
a4: 02 60 f9 60 pfld.l %r12\(%r7\),%f25
a8: 02 68 18 61 pfld.l %r13\(%r8\),%f24
ac: 02 70 37 61 pfld.l %r14\(%r9\),%f23
b0: 02 78 56 61 pfld.l %r15\(%r10\),%f22
b4: 02 80 75 61 pfld.l %r16\(%r11\),%f21
b8: 02 88 94 61 pfld.l %r17\(%r12\),%f20
bc: 02 e0 b3 61 pfld.l %r28\(%r13\),%f19
c0: 02 f8 d2 61 pfld.l %r31\(%r14\),%f18
c4: 03 28 00 60 pfld.l %r5\(%r0\)\+\+,%f0
c8: 03 30 21 60 pfld.l %r6\(%r1\)\+\+,%f1
cc: 03 38 42 60 pfld.l %r7\(%sp\)\+\+,%f2
d0: 03 40 63 60 pfld.l %r8\(%fp\)\+\+,%f3
d4: 03 48 84 60 pfld.l %r9\(%r4\)\+\+,%f4
d8: 03 00 a5 60 pfld.l %r0\(%r5\)\+\+,%f5
dc: 03 08 c6 60 pfld.l %r1\(%r6\)\+\+,%f6
e0: 03 60 e7 60 pfld.l %r12\(%r7\)\+\+,%f7
e4: 03 68 08 61 pfld.l %r13\(%r8\)\+\+,%f8
e8: 03 70 29 61 pfld.l %r14\(%r9\)\+\+,%f9
ec: 03 78 4a 61 pfld.l %r15\(%r10\)\+\+,%f10
f0: 03 80 6b 61 pfld.l %r16\(%r11\)\+\+,%f11
f4: 03 88 8c 61 pfld.l %r17\(%r12\)\+\+,%f12
f8: 03 e0 ad 61 pfld.l %r28\(%r13\)\+\+,%f13
fc: 03 f8 ce 61 pfld.l %r31\(%r14\)\+\+,%f14

75
gas/testsuite/gas/i860/fldst07.s
View File

@ -1,75 +0,0 @@
# pfld.l (no relocations here)
.text
# Immediate form, no auto-increment.
pfld.l 0(%r0),%f0
pfld.l 124(%r1),%f31
pfld.l 256(%r2),%f30
pfld.l 512(%r3),%f29
pfld.l 1024(%r4),%f28
pfld.l 4096(%r5),%f27
pfld.l 8192(%r6),%f26
pfld.l 16384(%r7),%f25
pfld.l 32764(%r7),%f25
pfld.l -32768(%r7),%f23
pfld.l -16384(%r8),%f2
pfld.l -8192(%r9),%f3
pfld.l -4096(%r10),%f8
pfld.l -1024(%r11),%f9
pfld.l -508(%r12),%f12
pfld.l -248(%r13),%f19
pfld.l -4(%r14),%f21
# Immediate form, with auto-increment.
pfld.l 0(%r0)++,%f0
pfld.l 124(%r1)++,%f1
pfld.l 256(%r2)++,%f2
pfld.l 512(%r3)++,%f3
pfld.l 1024(%r4)++,%f4
pfld.l 4096(%r5)++,%f5
pfld.l 8192(%r6)++,%f6
pfld.l 16384(%r7)++,%f7
pfld.l 32764(%r7)++,%f8
pfld.l -32768(%r7)++,%f9
pfld.l -16384(%r8)++,%f10
pfld.l -8192(%r9)++,%f11
pfld.l -4096(%r10)++,%f12
pfld.l -1024(%r11)++,%f13
pfld.l -508(%r12)++,%f14
pfld.l -248(%r13)++,%f15
pfld.l -4(%r14)++,%f16
# Index form, no auto-increment.
pfld.l %r5(%r0),%f0
pfld.l %r6(%r1),%f31
pfld.l %r7(%r2),%f30
pfld.l %r8(%r3),%f29
pfld.l %r9(%r4),%f28
pfld.l %r0(%r5),%f27
pfld.l %r1(%r6),%f26
pfld.l %r12(%r7),%f25
pfld.l %r13(%r8),%f24
pfld.l %r14(%r9),%f23
pfld.l %r15(%r10),%f22
pfld.l %r16(%r11),%f21
pfld.l %r17(%r12),%f20
pfld.l %r28(%r13),%f19
pfld.l %r31(%r14),%f18
# Index form, with auto-increment.
pfld.l %r5(%r0)++,%f0
pfld.l %r6(%r1)++,%f1
pfld.l %r7(%r2)++,%f2
pfld.l %r8(%r3)++,%f3
pfld.l %r9(%r4)++,%f4
pfld.l %r0(%r5)++,%f5
pfld.l %r1(%r6)++,%f6
pfld.l %r12(%r7)++,%f7
pfld.l %r13(%r8)++,%f8
pfld.l %r14(%r9)++,%f9
pfld.l %r15(%r10)++,%f10
pfld.l %r16(%r11)++,%f11
pfld.l %r17(%r12)++,%f12
pfld.l %r28(%r13)++,%f13
pfld.l %r31(%r14)++,%f14

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