[ARC] Sync cpu names with the ones accepted by GCC.
gas/ 2016-12-02 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/cpu-em-err.s: New file. * testsuite/gas/arc/cpu-em4-err.s: Likewise. * testsuite/gas/arc/cpu-fpuda-err.s: Likewise. * testsuite/gas/arc/cpu-hs-err.s: Likewise. * testsuite/gas/arc/cpu-quarkse-err.s: Likewise. * testsuite/gas/arc/noargs_a7.s: Add .cpu. * config/tc-arc.c (ARC_CPU_TYPE_A6xx): Define. (ARC_CPU_TYPE_A7xx): Likewise. (ARC_CPU_TYPE_AV2EM): Likewise. (ARC_CPU_TYPE_AV2HS): Likewise. (cpu_types): Update list of known CPU names. (arc_show_cpu_list): New function. (md_show_usage): Print accepted CPU names. (cl_features): New variable. (arc_select_cpu): Use cl_features. (arc_option): Allow various .cpu names. (md_parse_option): Set cl_features. * doc/c-arc.texi: Update -mcpu and .cpu documentation.
This commit is contained in:
Claudiu Zissulescu
parent
e5a873b707
commit
a9752fdf83
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@ -1,3 +1,24 @@
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2016-12-02 Claudiu Zissulescu <claziss@synopsys.com>
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* testsuite/gas/arc/cpu-em-err.s: New file.
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* testsuite/gas/arc/cpu-em4-err.s: Likewise.
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* testsuite/gas/arc/cpu-fpuda-err.s: Likewise.
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* testsuite/gas/arc/cpu-hs-err.s: Likewise.
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* testsuite/gas/arc/cpu-quarkse-err.s: Likewise.
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* testsuite/gas/arc/noargs_a7.s: Add .cpu.
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* config/tc-arc.c (ARC_CPU_TYPE_A6xx): Define.
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(ARC_CPU_TYPE_A7xx): Likewise.
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(ARC_CPU_TYPE_AV2EM): Likewise.
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(ARC_CPU_TYPE_AV2HS): Likewise.
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(cpu_types): Update list of known CPU names.
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(arc_show_cpu_list): New function.
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(md_show_usage): Print accepted CPU names.
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(cl_features): New variable.
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(arc_select_cpu): Use cl_features.
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(arc_option): Allow various .cpu names.
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(md_parse_option): Set cl_features.
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* doc/c-arc.texi: Update -mcpu and .cpu documentation.
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2016-12-02 Josh Conner <joshconner@google.com>
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* configure.tgt: Add support for fuchsia (OS).
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@ -426,6 +426,19 @@ static struct hash_control *arc_aux_hash;
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/* The hash table of address types. */
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static struct hash_control *arc_addrtype_hash;
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#define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \
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{ #NAME, ARC_OPCODE_ARC600, bfd_mach_arc_arc600, \
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E_ARC_MACH_ARC600, EXTRA}
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#define ARC_CPU_TYPE_A7xx(NAME,EXTRA) \
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{ #NAME, ARC_OPCODE_ARC700, bfd_mach_arc_arc700, \
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E_ARC_MACH_ARC700, EXTRA}
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#define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) \
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{ #NAME, ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2, \
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EF_ARC_CPU_ARCV2EM, EXTRA}
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#define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \
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{ #NAME, ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2, \
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EF_ARC_CPU_ARCV2HS, EXTRA}
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/* A table of CPU names and opcode sets. */
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static const struct cpu_type
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{
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@ -437,16 +450,31 @@ static const struct cpu_type
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}
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cpu_types[] =
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{
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{ "arc600", ARC_OPCODE_ARC600, bfd_mach_arc_arc600,
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E_ARC_MACH_ARC600, 0x00},
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{ "arc700", ARC_OPCODE_ARC700, bfd_mach_arc_arc700,
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E_ARC_MACH_ARC700, 0x00},
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{ "nps400", ARC_OPCODE_ARC700 , bfd_mach_arc_arc700,
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E_ARC_MACH_ARC700, ARC_NPS400},
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{ "arcem", ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2,
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EF_ARC_CPU_ARCV2EM, 0x00},
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{ "archs", ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2,
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EF_ARC_CPU_ARCV2HS, ARC_CD},
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ARC_CPU_TYPE_A7xx (arc700, 0x00),
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ARC_CPU_TYPE_A7xx (nps400, ARC_NPS400),
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ARC_CPU_TYPE_AV2EM (arcem, 0x00),
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ARC_CPU_TYPE_AV2EM (em, 0x00),
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ARC_CPU_TYPE_AV2EM (em4, ARC_CD),
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ARC_CPU_TYPE_AV2EM (em4_dmips, ARC_CD),
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ARC_CPU_TYPE_AV2EM (em4_fpus, ARC_CD),
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ARC_CPU_TYPE_AV2EM (em4_fpuda, ARC_CD | ARC_FPUDA),
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ARC_CPU_TYPE_AV2EM (quarkse_em, ARC_CD | ARC_SPFP | ARC_DPFP),
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ARC_CPU_TYPE_AV2HS (archs, ARC_CD),
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ARC_CPU_TYPE_AV2HS (hs, ARC_CD),
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ARC_CPU_TYPE_AV2HS (hs34, ARC_CD),
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ARC_CPU_TYPE_AV2HS (hs38, ARC_CD),
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ARC_CPU_TYPE_AV2HS (hs38_linux, ARC_CD),
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ARC_CPU_TYPE_A6xx (arc600, 0x00),
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ARC_CPU_TYPE_A6xx (arc600_norm, 0x00),
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ARC_CPU_TYPE_A6xx (arc600_mul64, 0x00),
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ARC_CPU_TYPE_A6xx (arc600_mul32x16, 0x00),
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ARC_CPU_TYPE_A6xx (arc601, 0x00),
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ARC_CPU_TYPE_A6xx (arc601_norm, 0x00),
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ARC_CPU_TYPE_A6xx (arc601_mul64, 0x00),
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ARC_CPU_TYPE_A6xx (arc601_mul32x16, 0x00),
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{ 0, 0, 0, 0, 0 }
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};
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@ -469,6 +497,9 @@ static const struct feature_type
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{ ARC_FPUDA, ARC_OPCODE_ARCv2EM, "double assist FP" }
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};
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/* Command line given features. */
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static unsigned cl_features = 0;
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/* Used by the arc_reloc_op table. Order is important. */
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#define O_gotoff O_md1 /* @gotoff relocation. */
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#define O_gotpc O_md2 /* @gotpc relocation. */
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@ -855,7 +886,7 @@ arc_select_cpu (const char *arg, enum mach_selection_type sel)
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/* Initialise static global data about selected machine type. */
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selected_cpu.flags = cpu_types[i].flags;
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selected_cpu.name = cpu_types[i].name;
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selected_cpu.features |= cpu_types[i].features;
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selected_cpu.features = cpu_types[i].features | cl_features;
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selected_cpu.mach = cpu_types[i].mach;
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cpu_flags = cpu_types[i].eflags;
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break;
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@ -978,6 +1009,7 @@ arc_option (int ignore ATTRIBUTE_UNUSED)
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c = get_symbol_name (&cpu);
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cpu_name = cpu;
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if ((!strcmp ("ARC600", cpu))
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|| (!strcmp ("ARC601", cpu))
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|| (!strcmp ("A6", cpu)))
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@ -991,13 +1023,8 @@ arc_option (int ignore ATTRIBUTE_UNUSED)
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cpu_name = "archs";
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else if (!strcmp ("NPS400", cpu))
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cpu_name = "nps400";
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else
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cpu_name = NULL;
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if (cpu_name != NULL)
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arc_select_cpu (cpu_name, MACH_SELECTION_FROM_CPU_DIRECTIVE);
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else
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as_fatal (_("invalid architecture `%s' in .cpu directive"), cpu);
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arc_select_cpu (cpu_name, MACH_SELECTION_FROM_CPU_DIRECTIVE);
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if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
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as_fatal (_("could not set architecture and machine"));
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@ -3354,6 +3381,7 @@ md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
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case OPTION_CD:
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selected_cpu.features |= ARC_CD;
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cl_features |= ARC_CD;
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arc_check_feature ();
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break;
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@ -3363,21 +3391,25 @@ md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
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case OPTION_NPS400:
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selected_cpu.features |= ARC_NPS400;
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cl_features |= ARC_NPS400;
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arc_check_feature ();
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break;
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case OPTION_SPFP:
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selected_cpu.features |= ARC_SPFP;
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cl_features |= ARC_SPFP;
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arc_check_feature ();
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break;
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case OPTION_DPFP:
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selected_cpu.features |= ARC_DPFP;
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cl_features |= ARC_DPFP;
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arc_check_feature ();
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break;
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case OPTION_FPUDA:
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selected_cpu.features |= ARC_FPUDA;
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cl_features |= ARC_FPUDA;
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arc_check_feature ();
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break;
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@ -3411,22 +3443,53 @@ md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
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return 1;
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}
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/* Display the list of cpu names for use in the help text. */
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static void
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arc_show_cpu_list (FILE *stream)
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{
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int i, offset;
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static const char *spaces = " ";
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fprintf (stream, "%s", spaces);
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offset = strlen (spaces);
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for (i = 0; cpu_types[i].name != NULL; ++i)
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{
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bfd_boolean last = (cpu_types[i + 1].name == NULL);
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/* If displaying the new cpu name string, and the ', ' (for all
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but the last one) will take us past a target width of 80
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characters, then it's time for a new line. */
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if (offset + strlen (cpu_types[i].name) + (last ? 0 : 2) > 80)
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{
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fprintf (stream, "\n%s", spaces);
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offset = strlen (spaces);
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}
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fprintf (stream, "%s%s", cpu_types[i].name, (last ? "\n" : ", "));
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offset += strlen (cpu_types [i].name) + (last ? 0 : 2);
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}
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}
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void
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md_show_usage (FILE *stream)
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{
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fprintf (stream, _("ARC-specific assembler options:\n"));
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fprintf (stream, " -mcpu=<cpu name>\t assemble for CPU <cpu name> "
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"(default: %s)\n", TARGET_WITH_CPU);
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fprintf (stream, " -mcpu=nps400\t\t same as -mcpu=arc700 -mnps400\n");
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fprintf (stream, " -mcpu=<cpu name>\t (default: %s), assemble for"
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" CPU <cpu name>, one of:\n", TARGET_WITH_CPU);
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arc_show_cpu_list (stream);
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fprintf (stream, "\n");
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fprintf (stream, " -mA6/-mARC600/-mARC601 same as -mcpu=arc600\n");
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fprintf (stream, " -mA7/-mARC700\t\t same as -mcpu=arc700\n");
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fprintf (stream, " -mEM\t\t\t same as -mcpu=arcem\n");
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fprintf (stream, " -mHS\t\t\t same as -mcpu=archs\n");
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fprintf (stream, " -mnps400\t\t enable NPS-400 extended instructions\n");
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fprintf (stream, " -mspfp\t\t enable single-precision floating point instructions\n");
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fprintf (stream, " -mdpfp\t\t enable double-precision floating point instructions\n");
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fprintf (stream, " -mspfp\t\t enable single-precision floating point"
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" instructions\n");
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fprintf (stream, " -mdpfp\t\t enable double-precision floating point"
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" instructions\n");
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fprintf (stream, " -mfpuda\t\t enable double-precision assist floating "
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"point\n\t\t\t instructions for ARC EM\n");
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@ -47,10 +47,28 @@ convenience. Supported values for @var{cpu} are
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@item arc600
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Assemble for ARC 600. Aliases: @code{-mA6}, @code{-mARC600}.
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@item arc600_norm
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Assemble for ARC 600 with norm instructions.
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@item arc600_mul64
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Assemble for ARC 600 with mul64 instructions.
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@item arc600_mul32x16
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Assemble for ARC 600 with mul32x16 instructions.
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@item arc601
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@cindex @code{mARC601} command line option, ARC
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Assemble for ARC 601. Alias: @code{-mARC601}.
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@item arc601_norm
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Assemble for ARC 601 with norm instructions.
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@item arc601_mul64
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Assemble for ARC 601 with mul64 instructions.
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@item arc601_mul32x16
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Assemble for ARC 601 with mul32x16 instructions.
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@item arc700
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@cindex @code{mA7} command line option, ARC
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@cindex @code{mARC700} command line option, ARC
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@ -60,10 +78,41 @@ Assemble for ARC 700. Aliases: @code{-mA7}, @code{-mARC700}.
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@cindex @code{mEM} command line option, ARC
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Assemble for ARC EM. Aliases: @code{-mEM}
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@item em
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Assemble for ARC EM, identical as arcem variant.
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@item em4
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Assemble for ARC EM with code-density instructions.
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@item em4_dmips
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Assemble for ARC EM with code-density instructions.
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@item em4_fpus
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Assemble for ARC EM with code-density instructions.
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@item em4_fpuda
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Assemble for ARC EM with code-density, and double-precision assist
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instructions.
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@item quarkse_em
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Assemble for QuarkSE-EM cpu.
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@item archs
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@cindex @code{mHS} command line option, ARC
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Assemble for ARC HS. Aliases: @code{-mHS}, @code{-mav2hs}.
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@item hs
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Assemble for ARC HS.
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@item hs34
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Assemble for ARC HS34.
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@item hs38
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Assemble for ARC HS38.
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@item hs38_linux
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Assemble for ARC HS38 with floating point support on.
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@item nps400
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@cindex @code{mnps400} command line option, ARC
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Assemble for ARC 700 with NPS-400 extended instructions.
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@ -368,6 +417,27 @@ version. Permitted values for CPU are:
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@item ARC600
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Assemble for the ARC600 instruction set.
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@item arc600_norm
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Assemble for ARC 600 with norm instructions.
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@item arc600_mul64
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Assemble for ARC 600 with mul64 instructions.
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@item arc600_mul32x16
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Assemble for ARC 600 with mul32x16 instructions.
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@item arc601
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Assemble for ARC 601 instruction set.
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@item arc601_norm
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Assemble for ARC 601 with norm instructions.
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@item arc601_mul64
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Assemble for ARC 601 with mul64 instructions.
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@item arc601_mul32x16
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Assemble for ARC 601 with mul32x16 instructions.
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@item ARC700
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Assemble for the ARC700 instruction set.
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@ -377,9 +447,43 @@ Assemble for the NPS400 instruction set.
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@item EM
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Assemble for the ARC EM instruction set.
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@item arcem
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Assemble for ARC EM instruction set
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@item em4
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Assemble for ARC EM with code-density instructions.
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@item em4_dmips
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Assemble for ARC EM with code-density instructions.
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@item em4_fpus
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Assemble for ARC EM with code-density instructions.
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@item em4_fpuda
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Assemble for ARC EM with code-density, and double-precision assist
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instructions.
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@item quarkse_em
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Assemble for QuarkSE-EM instruction set.
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@item HS
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Assemble for the ARC HS instruction set.
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@item archs
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Assemble for ARC HS instruction set.
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@item hs
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Assemble for ARC HS instruction set.
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@item hs34
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Assemble for ARC HS34 instruction set.
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@item hs38
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Assemble for ARC HS38 instruction set.
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@item hs38_linux
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Assemble for ARC HS38 with floating point support on.
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@end table
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Note: the @code{.cpu} directive overrides the command line option
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@ -0,0 +1,4 @@
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;;; Check if .cpu em doesn't have code-density ops.
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; { dg-do assemble { target arc*-*-* } }
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.cpu em
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sub_s r15,r2,r15 ; { dg-error "Error: inappropriate arguments for opcode 'sub_s'" }
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@ -0,0 +1,4 @@
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;;; Check if .cpu em4 has code-density ops.
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; { dg-do assemble { target arc*-*-* } }
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.cpu em4
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sub_s r15,r2,r15
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@ -0,0 +1,6 @@
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;;; Check if .cpu em4_fpuda has code-density and fpuda ops.
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; { dg-do assemble { target arc*-*-* } }
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.cpu em4_fpuda
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sub_s r15,r2,r15 ; code-density op
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dmulh11 r1,r2,r3 ; fpuda op
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fadd r1,r2,r3 ; { dg-error "Error: opcode 'fadd' not supported for target em4_fpuda" }
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@ -0,0 +1,5 @@
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;;; Check if .cpu hs has code-density
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; { dg-do assemble { target arc*-*-* } }
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.cpu hs
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sub_s r15,r2,r15 ; code-density op
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dmulh11 r1,r2,r3 ; { dg-error "Error: opcode 'dmulh11' not supported for target hs" }
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@ -0,0 +1,7 @@
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;;; Check if .cpu em4_quarkse has code-density, spfp and dpfp ops.
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; { dg-do assemble { target arc*-*-* } }
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.cpu quarkse_em
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sub_s r15,r2,r15 ; code-density op
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dmulh11 r1,r2,r3 ; dpfp op
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fadd r1,r2,r3 ; spfp op
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dsp_fp_div r2,r2,r3 ; QuarkSE-EM specific
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@ -1,4 +1,5 @@
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#Test if the following mnemonics are recognized for ARC700
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.cpu ARC700
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rtie
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sleep
|
||||
nop_s
|
||||
|
|
|
|||
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Reference in New Issue