OpenE2K
/
binutils-gdb
12
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Regernate cgen built files.

This commit is contained in:
Nick Clifton 2002-05-15 20:54:50 +00:00
parent c899585bc7
commit a978a3e5d8
13 changed files with 283 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
opcodes/ChangeLog
View File

@ -1,3 +1,18 @@
2002-05-15 Nick Clifton <nickc@cambridge.redhat.com>
* fr30-asm.c: Regenerate.
* fr30-desc.c: Regenerate.
* fr30-dis.c: Regenerate.
* m32r-asm.c: Regenerate.
* m32r-desc.c: Regenerate.
* m32r-dis.c: Regenerate.
* openrisc-asm.c: Regenerate.
* openrisc-desc.c: Regenerate.
* openrisc-dis.c: Regenerate.
* xstormy16-asm.c: Regenerate.
* xstormy16-desc.c: Regenerate.
* xstormy16-dis.c: Regenerate.
2002-05-15 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
* mips-dis.c (is_newabi): EABI is not a NewABI.

2
opcodes/fr30-asm.c
View File

@ -571,7 +571,7 @@ parse_insn_normal (cd, insn, strp, fields)
}
/* We have an operand of some sort. */
errmsg = fr30_cgen_parse_operand (cd, CGEN_SYNTAX_FIELD (*syn),
errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn),
&str, fields);
if (errmsg)
return errmsg;

33
opcodes/fr30-desc.c
View File

@ -1747,10 +1747,43 @@ void
fr30_cgen_cpu_close (cd)
CGEN_CPU_DESC cd;
{
unsigned int i;
CGEN_INSN *insns;
if (cd->macro_insn_table.init_entries)
{
insns = cd->macro_insn_table.init_entries;
for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX ((insns)))
regfree(CGEN_INSN_RX (insns));
}
}
if (cd->insn_table.init_entries)
{
insns = cd->insn_table.init_entries;
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX (insns))
regfree(CGEN_INSN_RX (insns));
}
}
if (cd->macro_insn_table.init_entries)
free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
if (cd->insn_table.init_entries)
free ((CGEN_INSN *) cd->insn_table.init_entries);
if (cd->hw_table.entries)
free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
if (cd->operand_table.entries)
free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
free (cd);
}

37
opcodes/fr30-dis.c
View File

@ -632,11 +632,21 @@ default_print_insn (cd, pc, info)
Print one instruction from PC on INFO->STREAM.
Return the size of the instruction (in bytes). */
typedef struct cpu_desc_list {
struct cpu_desc_list *next;
int isa;
int mach;
int endian;
CGEN_CPU_DESC cd;
} cpu_desc_list;
int
print_insn_fr30 (pc, info)
bfd_vma pc;
disassemble_info *info;
{
static cpu_desc_list *cd_list = 0;
cpu_desc_list *cl = 0;
static CGEN_CPU_DESC cd = 0;
static int prev_isa;
static int prev_mach;
@ -667,18 +677,27 @@ print_insn_fr30 (pc, info)
#ifdef CGEN_COMPUTE_ISA
isa = CGEN_COMPUTE_ISA (info);
#else
isa = 0;
isa = info->insn_sets;
#endif
/* If we've switched cpu's, close the current table and open a new one. */
/* If we've switched cpu's, try to find a handle we've used before */
if (cd
&& (isa != prev_isa
|| mach != prev_mach
|| endian != prev_endian))
{
fr30_cgen_cpu_close (cd);
cd = 0;
}
for (cl = cd_list; cl; cl = cl->next)
{
if (cl->isa == isa &&
cl->mach == mach &&
cl->endian == endian)
{
cd = cl->cd;
break;
}
}
}
/* If we haven't initialized yet, initialize the opcode table. */
if (! cd)
@ -699,6 +718,16 @@ print_insn_fr30 (pc, info)
CGEN_CPU_OPEN_END);
if (!cd)
abort ();
/* save this away for future reference */
cl = xmalloc (sizeof (struct cpu_desc_list));
cl->cd = cd;
cl->isa = isa;
cl->mach = mach;
cl->endian = endian;
cl->next = cd_list;
cd_list = cl;
fr30_cgen_init_dis (cd);
}

2
opcodes/m32r-asm.c
View File

@ -573,7 +573,7 @@ parse_insn_normal (cd, insn, strp, fields)
}
/* We have an operand of some sort. */
errmsg = m32r_cgen_parse_operand (cd, CGEN_SYNTAX_FIELD (*syn),
errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn),
&str, fields);
if (errmsg)
return errmsg;

33
opcodes/m32r-desc.c
View File

@ -1441,10 +1441,43 @@ void
m32r_cgen_cpu_close (cd)
CGEN_CPU_DESC cd;
{
unsigned int i;
CGEN_INSN *insns;
if (cd->macro_insn_table.init_entries)
{
insns = cd->macro_insn_table.init_entries;
for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX ((insns)))
regfree(CGEN_INSN_RX (insns));
}
}
if (cd->insn_table.init_entries)
{
insns = cd->insn_table.init_entries;
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX (insns))
regfree(CGEN_INSN_RX (insns));
}
}
if (cd->macro_insn_table.init_entries)
free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
if (cd->insn_table.init_entries)
free ((CGEN_INSN *) cd->insn_table.init_entries);
if (cd->hw_table.entries)
free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
if (cd->operand_table.entries)
free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
free (cd);
}

37
opcodes/m32r-dis.c
View File

@ -563,11 +563,21 @@ default_print_insn (cd, pc, info)
Print one instruction from PC on INFO->STREAM.
Return the size of the instruction (in bytes). */
typedef struct cpu_desc_list {
struct cpu_desc_list *next;
int isa;
int mach;
int endian;
CGEN_CPU_DESC cd;
} cpu_desc_list;
int
print_insn_m32r (pc, info)
bfd_vma pc;
disassemble_info *info;
{
static cpu_desc_list *cd_list = 0;
cpu_desc_list *cl = 0;
static CGEN_CPU_DESC cd = 0;
static int prev_isa;
static int prev_mach;
@ -598,18 +608,27 @@ print_insn_m32r (pc, info)
#ifdef CGEN_COMPUTE_ISA
isa = CGEN_COMPUTE_ISA (info);
#else
isa = 0;
isa = info->insn_sets;
#endif
/* If we've switched cpu's, close the current table and open a new one. */
/* If we've switched cpu's, try to find a handle we've used before */
if (cd
&& (isa != prev_isa
|| mach != prev_mach
|| endian != prev_endian))
{
m32r_cgen_cpu_close (cd);
cd = 0;
}
for (cl = cd_list; cl; cl = cl->next)
{
if (cl->isa == isa &&
cl->mach == mach &&
cl->endian == endian)
{
cd = cl->cd;
break;
}
}
}
/* If we haven't initialized yet, initialize the opcode table. */
if (! cd)
@ -630,6 +649,16 @@ print_insn_m32r (pc, info)
CGEN_CPU_OPEN_END);
if (!cd)
abort ();
/* save this away for future reference */
cl = xmalloc (sizeof (struct cpu_desc_list));
cl->cd = cd;
cl->isa = isa;
cl->mach = mach;
cl->endian = endian;
cl->next = cd_list;
cd_list = cl;
m32r_cgen_init_dis (cd);
}

2
opcodes/openrisc-asm.c
View File

@ -492,7 +492,7 @@ parse_insn_normal (cd, insn, strp, fields)
}
/* We have an operand of some sort. */
errmsg = openrisc_cgen_parse_operand (cd, CGEN_SYNTAX_FIELD (*syn),
errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn),
&str, fields);
if (errmsg)
return errmsg;

33
opcodes/openrisc-desc.c
View File

@ -1017,10 +1017,43 @@ void
openrisc_cgen_cpu_close (cd)
CGEN_CPU_DESC cd;
{
unsigned int i;
CGEN_INSN *insns;
if (cd->macro_insn_table.init_entries)
{
insns = cd->macro_insn_table.init_entries;
for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX ((insns)))
regfree(CGEN_INSN_RX (insns));
}
}
if (cd->insn_table.init_entries)
{
insns = cd->insn_table.init_entries;
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX (insns))
regfree(CGEN_INSN_RX (insns));
}
}
if (cd->macro_insn_table.init_entries)
free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
if (cd->insn_table.init_entries)
free ((CGEN_INSN *) cd->insn_table.init_entries);
if (cd->hw_table.entries)
free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
if (cd->operand_table.entries)
free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
free (cd);
}

37
opcodes/openrisc-dis.c
View File

@ -450,11 +450,21 @@ default_print_insn (cd, pc, info)
Print one instruction from PC on INFO->STREAM.
Return the size of the instruction (in bytes). */
typedef struct cpu_desc_list {
struct cpu_desc_list *next;
int isa;
int mach;
int endian;
CGEN_CPU_DESC cd;
} cpu_desc_list;
int
print_insn_openrisc (pc, info)
bfd_vma pc;
disassemble_info *info;
{
static cpu_desc_list *cd_list = 0;
cpu_desc_list *cl = 0;
static CGEN_CPU_DESC cd = 0;
static int prev_isa;
static int prev_mach;
@ -485,18 +495,27 @@ print_insn_openrisc (pc, info)
#ifdef CGEN_COMPUTE_ISA
isa = CGEN_COMPUTE_ISA (info);
#else
isa = 0;
isa = info->insn_sets;
#endif
/* If we've switched cpu's, close the current table and open a new one. */
/* If we've switched cpu's, try to find a handle we've used before */
if (cd
&& (isa != prev_isa
|| mach != prev_mach
|| endian != prev_endian))
{
openrisc_cgen_cpu_close (cd);
cd = 0;
}
for (cl = cd_list; cl; cl = cl->next)
{
if (cl->isa == isa &&
cl->mach == mach &&
cl->endian == endian)
{
cd = cl->cd;
break;
}
}
}
/* If we haven't initialized yet, initialize the opcode table. */
if (! cd)
@ -517,6 +536,16 @@ print_insn_openrisc (pc, info)
CGEN_CPU_OPEN_END);
if (!cd)
abort ();
/* save this away for future reference */
cl = xmalloc (sizeof (struct cpu_desc_list));
cl->cd = cd;
cl->isa = isa;
cl->mach = mach;
cl->endian = endian;
cl->next = cd_list;
cd_list = cl;
openrisc_cgen_init_dis (cd);
}

2
opcodes/xstormy16-asm.c
View File

@ -479,7 +479,7 @@ parse_insn_normal (cd, insn, strp, fields)
}
/* We have an operand of some sort. */
errmsg = xstormy16_cgen_parse_operand (cd, CGEN_SYNTAX_FIELD (*syn),
errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn),
&str, fields);
if (errmsg)
return errmsg;

33
opcodes/xstormy16-desc.c
View File

@ -1458,10 +1458,43 @@ void
xstormy16_cgen_cpu_close (cd)
CGEN_CPU_DESC cd;
{
unsigned int i;
CGEN_INSN *insns;
if (cd->macro_insn_table.init_entries)
{
insns = cd->macro_insn_table.init_entries;
for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX ((insns)))
regfree(CGEN_INSN_RX (insns));
}
}
if (cd->insn_table.init_entries)
{
insns = cd->insn_table.init_entries;
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX (insns))
regfree(CGEN_INSN_RX (insns));
}
}
if (cd->macro_insn_table.init_entries)
free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
if (cd->insn_table.init_entries)
free ((CGEN_INSN *) cd->insn_table.init_entries);
if (cd->hw_table.entries)
free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
if (cd->operand_table.entries)
free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
free (cd);
}

37
opcodes/xstormy16-dis.c
View File

@ -483,11 +483,21 @@ default_print_insn (cd, pc, info)
Print one instruction from PC on INFO->STREAM.
Return the size of the instruction (in bytes). */
typedef struct cpu_desc_list {
struct cpu_desc_list *next;
int isa;
int mach;
int endian;
CGEN_CPU_DESC cd;
} cpu_desc_list;
int
print_insn_xstormy16 (pc, info)
bfd_vma pc;
disassemble_info *info;
{
static cpu_desc_list *cd_list = 0;
cpu_desc_list *cl = 0;
static CGEN_CPU_DESC cd = 0;
static int prev_isa;
static int prev_mach;
@ -518,18 +528,27 @@ print_insn_xstormy16 (pc, info)
#ifdef CGEN_COMPUTE_ISA
isa = CGEN_COMPUTE_ISA (info);
#else
isa = 0;
isa = info->insn_sets;
#endif
/* If we've switched cpu's, close the current table and open a new one. */
/* If we've switched cpu's, try to find a handle we've used before */
if (cd
&& (isa != prev_isa
|| mach != prev_mach
|| endian != prev_endian))
{
xstormy16_cgen_cpu_close (cd);
cd = 0;
}
for (cl = cd_list; cl; cl = cl->next)
{
if (cl->isa == isa &&
cl->mach == mach &&
cl->endian == endian)
{
cd = cl->cd;
break;
}
}
}
/* If we haven't initialized yet, initialize the opcode table. */
if (! cd)
@ -550,6 +569,16 @@ print_insn_xstormy16 (pc, info)
CGEN_CPU_OPEN_END);
if (!cd)
abort ();
/* save this away for future reference */
cl = xmalloc (sizeof (struct cpu_desc_list));
cl->cd = cd;
cl->isa = isa;
cl->mach = mach;
cl->endian = endian;
cl->next = cd_list;
cd_list = cl;
xstormy16_cgen_init_dis (cd);
}