2000-08-10 Jason Eckhardt <jle@cygnus.com>
* doc/c-i860.texi: Flesh out the i860 section more.
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@ -1,3 +1,7 @@
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2000-08-10 Jason Eckhardt <jle@cygnus.com>
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* doc/c-i860.texi: Flesh out the i860 section more.
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2000-08-10 Kazu Hirata <kazu@hxi.com>
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2000-08-10 Kazu Hirata <kazu@hxi.com>
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* symbols.c: Fix formatting.
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* symbols.c: Fix formatting.
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@ -21,13 +21,22 @@ do ELF (it doesn't do anything, but you get the point).
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@cindex i860 support
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@cindex i860 support
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@menu
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@menu
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* Notes-i860:: i860 Notes
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* Options-i860:: i860 Command-line Options
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* Options-i860:: i860 Command-line Options
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* Directives-i860:: i860 Machine Directives
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* Directives-i860:: i860 Machine Directives
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* Opcodes for i860:: i860 Opcodes
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* Opcodes for i860:: i860 Opcodes
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@end menu
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@end menu
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@node Options-i860
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@node Notes-i860
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@section i860 Notes
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This is a fairly complete i860 assembler which is compatible with the
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UNIX System V/860 Release 4 assembler. However, it does not currently
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support SVR4 PIC (i.e., @code{@@GOT, @@GOTOFF, @@PLT}).
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Like the SVR4/860 assembler, the output object format is ELF32. Currently,
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this is the only supported object format. If there is sufficient interest,
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other formats such as COFF may be implemented.
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@node Options-i860
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@section i860 Command-line Options
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@section i860 Command-line Options
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@subsection SVR4 compatibility options
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@subsection SVR4 compatibility options
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@table @code
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@table @code
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@ -46,6 +55,13 @@ Select little endian output (this is the default).
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Select big endian output. Note that the i860 always reads instructions
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Select big endian output. Note that the i860 always reads instructions
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as little endian data, so this option only effects data and not
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as little endian data, so this option only effects data and not
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instructions.
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instructions.
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@item -mwarn-expand
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Emit a warning message if any pseudo-instruction expansions occurred.
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For example, a @code{or} instruction with an immediate larger than 16-bits
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will be expanded into two instructions. This is a very undesirable feature to
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rely on, so this flag can help detect any code where it happens. One
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use of it, for instance, has been to find and eliminate any place
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where @code{gcc} may emit these pseudo-instructions.
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@end table
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@end table
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@node Directives-i860
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@node Directives-i860
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@ -82,9 +98,54 @@ default register is @code{r31}.
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@cindex opcodes, i860
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@cindex opcodes, i860
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@cindex i860 opcodes
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@cindex i860 opcodes
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All of the Intel i860 machine instructions are supported.
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All of the Intel i860 machine instructions are supported. Please see
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either @emph{i860 Microprocessor Programmer's Reference Manual} or @emph{i860 Microprocessor Architecture} for more information.
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@subsection Other instruction support (pseudo-instructions)
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For compatibility with some other i860 assemblers, a number of
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pseudo-instructions are supported. While these are supported, they are
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a very undesirable feature that should be avoided -- in particular, when
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they result in an expansion to multiple actual i860 instructions. Below
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are the pseudo-instructions that result in expansions.
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@itemize @bullet
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@item {Load large immediate into general register:}
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Some opcodes are processed beyond simply emitting a single corresponding
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The pseudo-instruction @code{mov imm,%rn} (where the immediate does
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instruction. For example, @samp{mov} and other instructions with larg
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not fit within a signed 16-bit field) will be expanded into:
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displacements may be expanded into 2 or 3 instructions (FIXME: add details).
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@smallexample
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orh large_imm@@h,%r0,%rn
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or large_imm@@l,%rn,%rn
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@end smallexample
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@item {Load/store with relocatable address expression:}
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For example, the pseudo-instruction @code{ld.b addr,%rn}
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will be expanded into:
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@smallexample
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orh addr_exp@@ha,%r0,%r31
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ld.l addr_exp@@l(%r31),%rn
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@end smallexample
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The analogous expansions apply to @code{ld.x, st.x, fld.x, pfld.x, fst.x}, and @code{pst.x} as well.
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@item {Signed large immediate with add/subtract:}
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If any of the arithmetic operations @code{adds, addu, subs, subu} are used
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with an immediate larger than 16-bits (signed), then they will be expanded.
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For instance, the pseudo-instruction @code{adds large_imm,%rx,%rn} expands to:
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@smallexample
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orh large_imm@@h,%r0,%r31
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or large_imm@@l,%r31,%r31
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adds %r31,%rx,%rn
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@end smallexample
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@item {Unsigned large immediate with logical operations:}
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Logical operations (@code{or, andnot, or, xor}) also result in expansions.
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The pseudo-instruction @code{or large_imm,%rx,%rn} results in:
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@smallexample
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orh large_imm@@h,%rx,%r31
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or large_imm@@l,%r31,%rn
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@end smallexample
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Similarly for the others, except for @code{and} which expands to:
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@smallexample
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andnot (-1 - large_imm)@@h,%rx,%r31
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andnot (-1 - large_imm)@@l,%r31,%rn
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@end smallexample
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@end itemize
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