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[ gas/ChangeLog ] 

* config/tc-mips.c (macro_build): Use INSERT_OPERAND wherew
	appropriate.
	(mips16_macro_build): Use MIPS16_INSERT_OPERAND where appropriate.
	(mips_ip): Make overflowed/underflowed constant arguments in DSP
	and MT instructions a fatal error. Use INSERT_OPERAND where
	appropriate. Improve warnings for break and wait code overflows.
	Use symbolic constant of OP_MASK_COPZ.
	(mips16_ip): Use MIPS16_INSERT_OPERAND where appropriate.

	[ gas/testsuite/ChangeLog ]
	* gas/mips/mips32-dsp.d, gas/mips/mips32-dsp.s, gas/mips/mips32-mt.d,
	gas/mips/mips32-mt.s: Remove instructions with invalid arguments.
	* gas/mips/mips32-dsp.l, gas/mips/mips32-mt.l: Delete file.

	[ include/opcode/ChangeLog ]
	* mips.h: Improve description of MT flags.
This commit is contained in:
Thiemo Seufer 2006-06-05 16:28:36 +00:00
parent 2f0122dcdf
commit a9e2435482
11 changed files with 255 additions and 1002 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
gas/ChangeLog
View File

@ -1,3 +1,14 @@
2006-06-05 Thiemo Seufer <ths@mips.com>
* config/tc-mips.c (macro_build): Use INSERT_OPERAND wherew
appropriate.
(mips16_macro_build): Use MIPS16_INSERT_OPERAND where appropriate.
(mips_ip): Make overflowed/underflowed constant arguments in DSP
and MT instructions a fatal error. Use INSERT_OPERAND where
appropriate. Improve warnings for break and wait code overflows.
Use symbolic constant of OP_MASK_COPZ.
(mips16_ip): Use MIPS16_INSERT_OPERAND where appropriate.
2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
* po/Make-in (top_builddir): Define.

146
gas/config/tc-mips.c
View File

@ -3488,11 +3488,11 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
continue;
case 'C':
insn.insn_opcode |= va_arg (args, unsigned long);
INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long));
continue;
case 'k':
insn.insn_opcode |= va_arg (args, unsigned long) << OP_SH_CACHE;
INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long));
continue;
default:
@ -3576,7 +3576,7 @@ mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
regno = va_arg (args, int);
regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
MIPS16_INSERT_OPERAND (REG32R, insn, regno);
}
continue;
@ -8431,11 +8431,10 @@ mips_ip (char *str, struct mips_cl_insn *ip)
check_absolute_expr (ip, &imm_expr);
if (imm_expr.X_add_number & ~OP_MASK_SA3)
{
as_warn (_("DSP immediate not in range 0..%d (%lu)"),
OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
imm_expr.X_add_number &= OP_MASK_SA3;
as_bad (_("DSP immediate not in range 0..%d (%lu)"),
OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
}
ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SA3;
INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
@ -8445,11 +8444,10 @@ mips_ip (char *str, struct mips_cl_insn *ip)
check_absolute_expr (ip, &imm_expr);
if (imm_expr.X_add_number & ~OP_MASK_SA4)
{
as_warn (_("DSP immediate not in range 0..%d (%lu)"),
OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
imm_expr.X_add_number &= OP_MASK_SA4;
as_bad (_("DSP immediate not in range 0..%d (%lu)"),
OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
}
ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SA4;
INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
@ -8459,11 +8457,10 @@ mips_ip (char *str, struct mips_cl_insn *ip)
check_absolute_expr (ip, &imm_expr);
if (imm_expr.X_add_number & ~OP_MASK_IMM8)
{
as_warn (_("DSP immediate not in range 0..%d (%lu)"),
OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
imm_expr.X_add_number &= OP_MASK_IMM8;
as_bad (_("DSP immediate not in range 0..%d (%lu)"),
OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
}
ip->insn_opcode |= imm_expr.X_add_number << OP_SH_IMM8;
INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
@ -8473,11 +8470,10 @@ mips_ip (char *str, struct mips_cl_insn *ip)
check_absolute_expr (ip, &imm_expr);
if (imm_expr.X_add_number & ~OP_MASK_RS)
{
as_warn (_("DSP immediate not in range 0..%d (%lu)"),
OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
imm_expr.X_add_number &= OP_MASK_RS;
as_bad (_("DSP immediate not in range 0..%d (%lu)"),
OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
}
ip->insn_opcode |= imm_expr.X_add_number << OP_SH_RS;
INSERT_OPERAND (RS, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
@ -8488,7 +8484,7 @@ mips_ip (char *str, struct mips_cl_insn *ip)
{
regno = s[3] - '0';
s += 4;
ip->insn_opcode |= regno << OP_SH_DSPACC;
INSERT_OPERAND (DSPACC, *ip, regno);
continue;
}
else
@ -8500,12 +8496,11 @@ mips_ip (char *str, struct mips_cl_insn *ip)
check_absolute_expr (ip, &imm_expr);
if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
{
as_warn (_("DSP immediate not in range 0..%d (%lu)"),
OP_MASK_WRDSP,
(unsigned long) imm_expr.X_add_number);
imm_expr.X_add_number &= OP_MASK_WRDSP;
as_bad (_("DSP immediate not in range 0..%d (%lu)"),
OP_MASK_WRDSP,
(unsigned long) imm_expr.X_add_number);
}
ip->insn_opcode |= imm_expr.X_add_number << OP_SH_WRDSP;
INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
@ -8516,7 +8511,7 @@ mips_ip (char *str, struct mips_cl_insn *ip)
{
regno = s[3] - '0';
s += 4;
ip->insn_opcode |= regno << OP_SH_DSPACC_S;
INSERT_OPERAND (DSPACC_S, *ip, regno);
continue;
}
else
@ -8531,13 +8526,11 @@ mips_ip (char *str, struct mips_cl_insn *ip)
if (imm_expr.X_add_number < min_range ||
imm_expr.X_add_number > max_range)
{
as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
(long) min_range, (long) max_range,
(long) imm_expr.X_add_number);
as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
(long) min_range, (long) max_range,
(long) imm_expr.X_add_number);
}
imm_expr.X_add_number &= OP_MASK_DSPSFT;
ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
<< OP_SH_DSPSFT);
INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
@ -8547,12 +8540,11 @@ mips_ip (char *str, struct mips_cl_insn *ip)
check_absolute_expr (ip, &imm_expr);
if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
{
as_warn (_("DSP immediate not in range 0..%d (%lu)"),
OP_MASK_RDDSP,
(unsigned long) imm_expr.X_add_number);
imm_expr.X_add_number &= OP_MASK_RDDSP;
as_bad (_("DSP immediate not in range 0..%d (%lu)"),
OP_MASK_RDDSP,
(unsigned long) imm_expr.X_add_number);
}
ip->insn_opcode |= imm_expr.X_add_number << OP_SH_RDDSP;
INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
@ -8565,13 +8557,11 @@ mips_ip (char *str, struct mips_cl_insn *ip)
if (imm_expr.X_add_number < min_range ||
imm_expr.X_add_number > max_range)
{
as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
(long) min_range, (long) max_range,
(long) imm_expr.X_add_number);
as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
(long) min_range, (long) max_range,
(long) imm_expr.X_add_number);
}
imm_expr.X_add_number &= OP_MASK_DSPSFT_7;
ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
<< OP_SH_DSPSFT_7);
INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
@ -8584,41 +8574,33 @@ mips_ip (char *str, struct mips_cl_insn *ip)
if (imm_expr.X_add_number < min_range ||
imm_expr.X_add_number > max_range)
{
as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
(long) min_range, (long) max_range,
(long) imm_expr.X_add_number);
as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
(long) min_range, (long) max_range,
(long) imm_expr.X_add_number);
}
imm_expr.X_add_number &= OP_MASK_IMM10;
ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
<< OP_SH_IMM10);
INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
case '!': /* mt 1-bit unsigned immediate in bit 5 */
case '!': /* MT usermode flag bit. */
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if (imm_expr.X_add_number & ~OP_MASK_MT_U)
{
as_warn (_("MT immediate not in range 0..%d (%lu)"),
OP_MASK_MT_U, (unsigned long) imm_expr.X_add_number);
imm_expr.X_add_number &= OP_MASK_MT_U;
}
ip->insn_opcode |= imm_expr.X_add_number << OP_SH_MT_U;
as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
(unsigned long) imm_expr.X_add_number);
INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
case '$': /* mt 1-bit unsigned immediate in bit 4 */
case '$': /* MT load high flag bit. */
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if (imm_expr.X_add_number & ~OP_MASK_MT_H)
{
as_warn (_("MT immediate not in range 0..%d (%lu)"),
OP_MASK_MT_H, (unsigned long) imm_expr.X_add_number);
imm_expr.X_add_number &= OP_MASK_MT_H;
}
ip->insn_opcode |= imm_expr.X_add_number << OP_SH_MT_H;
as_bad (_("MT load high bit not 0 or 1 (%lu)"),
(unsigned long) imm_expr.X_add_number);
INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
@ -8629,7 +8611,7 @@ mips_ip (char *str, struct mips_cl_insn *ip)
{
regno = s[3] - '0';
s += 4;
ip->insn_opcode |= regno << OP_SH_MTACC_T;
INSERT_OPERAND (MTACC_T, *ip, regno);
continue;
}
else
@ -8642,7 +8624,7 @@ mips_ip (char *str, struct mips_cl_insn *ip)
{
regno = s[3] - '0';
s += 4;
ip->insn_opcode |= regno << OP_SH_MTACC_D;
INSERT_OPERAND (MTACC_D, *ip, regno);
continue;
}
else
@ -8849,7 +8831,7 @@ do_msbd:
as_bad (_("Invalid register number (%d)"), regno);
else
{
ip->insn_opcode |= regno << OP_SH_RT;
INSERT_OPERAND (RT, *ip, regno);
continue;
}
}
@ -8912,8 +8894,9 @@ do_msbd:
case 'c': /* break code */
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if ((unsigned long) imm_expr.X_add_number > 1023)
as_warn (_("Illegal break code (%lu)"),
if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE)
as_warn (_("Code for %s not in range 0..1023 (%lu)"),
ip->insn_mo->name,
(unsigned long) imm_expr.X_add_number);
INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
@ -8923,8 +8906,9 @@ do_msbd:
case 'q': /* lower break code */
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if ((unsigned long) imm_expr.X_add_number > 1023)
as_warn (_("Illegal lower break code (%lu)"),
if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2)
as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
ip->insn_mo->name,
(unsigned long) imm_expr.X_add_number);
INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
@ -8935,7 +8919,8 @@ do_msbd:
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
as_warn (_("Illegal 20-bit code (%lu)"),
as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
ip->insn_mo->name,
(unsigned long) imm_expr.X_add_number);
INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
@ -8945,13 +8930,13 @@ do_msbd:
case 'C': /* Coprocessor code */
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ)
{
as_warn (_("Coproccesor code > 25 bits (%lu)"),
(unsigned long) imm_expr.X_add_number);
imm_expr.X_add_number &= ((1 << 25) - 1);
imm_expr.X_add_number &= OP_MASK_COPZ;
}
ip->insn_opcode |= imm_expr.X_add_number;
INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
@ -8960,8 +8945,11 @@ do_msbd:
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
as_warn (_("Illegal 19-bit code (%lu)"),
(unsigned long) imm_expr.X_add_number);
{
as_warn (_("Illegal 19-bit code (%lu)"),
(unsigned long) imm_expr.X_add_number);
imm_expr.X_add_number &= OP_MASK_CODE19;
}
INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
@ -8983,7 +8971,7 @@ do_msbd:
ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, &regno);
else
ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &regno);
ip->insn_opcode |= regno << OP_SH_RD;
INSERT_OPERAND (RD, *ip, regno);
if (ok)
{
lastregno = regno;
@ -9857,9 +9845,9 @@ mips16_ip (char *str, struct mips_cl_insn *ip)
if (c == 'v' || c == 'w')
{
if (c == 'v')
ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
else
ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
++args;
continue;
}

6
gas/testsuite/ChangeLog
View File

@ -1,3 +1,9 @@
2006-06-05 Thiemo Seufer <ths@mips.com>
* gas/mips/mips32-dsp.d, gas/mips/mips32-dsp.s, gas/mips/mips32-mt.d,
gas/mips/mips32-mt.s: Remove instructions with invalid arguments.
* gas/mips/mips32-dsp.l, gas/mips/mips32-mt.l: Delete file.
2006-05-25 Richard Sandiford <richard@codesourcery.com>
* gas/m68k/mcf-fpu.s: Add fmovemd and fmovem instructions.

239
gas/testsuite/gas/mips/mips32-dsp.d
View File

@ -1,7 +1,6 @@
#objdump: -dr --prefix-addresses --show-raw-insn
#name: MIPS DSP ASE for MIPS32
#as: -mdsp
#stderr: mips32-dsp.l
# Check MIPS DSP ASE for MIPS32 Instruction Assembly
@ -38,141 +37,103 @@ Disassembly of section .text:
0+006c <[^>]*> 7c1cdf52 preceu\.ph\.qbr k1,gp
0+0070 <[^>]*> 7c1de792 preceu\.ph\.qbla gp,sp
0+0074 <[^>]*> 7c1eefd2 preceu\.ph\.qbra sp,s8
0+0078 <[^>]*> 7cfff013 shll\.qb s8,ra,0x7
0+007c <[^>]*> 7c1ff013 shll\.qb s8,ra,0x0
0+0080 <[^>]*> 7cfff013 shll\.qb s8,ra,0x7
0+0084 <[^>]*> 7c1ff013 shll\.qb s8,ra,0x0
0+0088 <[^>]*> 7c20f893 shllv\.qb ra,zero,at
0+008c <[^>]*> 7de10213 shll\.ph zero,at,0xf
0+0090 <[^>]*> 7c010213 shll\.ph zero,at,0x0
0+0094 <[^>]*> 7de10213 shll\.ph zero,at,0xf
0+0098 <[^>]*> 7c010213 shll\.ph zero,at,0x0
0+009c <[^>]*> 7c620a93 shllv\.ph at,v0,v1
0+00a0 <[^>]*> 7de31313 shll_s\.ph v0,v1,0xf
0+00a4 <[^>]*> 7c031313 shll_s\.ph v0,v1,0x0
0+00a8 <[^>]*> 7de31313 shll_s\.ph v0,v1,0xf
0+00ac <[^>]*> 7c031313 shll_s\.ph v0,v1,0x0
0+00b0 <[^>]*> 7ca41b93 shllv_s\.ph v1,a0,a1
0+00b4 <[^>]*> 7fe52513 shll_s\.w a0,a1,0x1f
0+00b8 <[^>]*> 7c052513 shll_s\.w a0,a1,0x0
0+00bc <[^>]*> 7fe52513 shll_s\.w a0,a1,0x1f
0+00c0 <[^>]*> 7c052513 shll_s\.w a0,a1,0x0
0+00c4 <[^>]*> 7ce62d93 shllv_s\.w a1,a2,a3
0+00c8 <[^>]*> 7ce73053 shrl\.qb a2,a3,0x7
0+00cc <[^>]*> 7c073053 shrl\.qb a2,a3,0x0
0+00d0 <[^>]*> 7ce73053 shrl\.qb a2,a3,0x7
0+00d4 <[^>]*> 7c073053 shrl\.qb a2,a3,0x0
0+00d8 <[^>]*> 7d2838d3 shrlv\.qb a3,t0,t1
0+00dc <[^>]*> 7de94253 shra\.ph t0,t1,0xf
0+00e0 <[^>]*> 7c094253 shra\.ph t0,t1,0x0
0+00e4 <[^>]*> 7de94253 shra\.ph t0,t1,0xf
0+00e8 <[^>]*> 7c094253 shra\.ph t0,t1,0x0
0+00ec <[^>]*> 7d6a4ad3 shrav\.ph t1,t2,t3
0+00f0 <[^>]*> 7deb5353 shra_r\.ph t2,t3,0xf
0+00f4 <[^>]*> 7c0b5353 shra_r\.ph t2,t3,0x0
0+00f8 <[^>]*> 7deb5353 shra_r\.ph t2,t3,0xf
0+00fc <[^>]*> 7c0b5353 shra_r\.ph t2,t3,0x0
0+0100 <[^>]*> 7dac5bd3 shrav_r\.ph t3,t4,t5
0+0104 <[^>]*> 7fed6553 shra_r\.w t4,t5,0x1f
0+0108 <[^>]*> 7c0d6553 shra_r\.w t4,t5,0x0
0+010c <[^>]*> 7fed6553 shra_r\.w t4,t5,0x1f
0+0110 <[^>]*> 7c0d6553 shra_r\.w t4,t5,0x0
0+0114 <[^>]*> 7dee6dd3 shrav_r\.w t5,t6,t7
0+0118 <[^>]*> 7df07190 muleu_s\.ph\.qbl t6,t7,s0
0+011c <[^>]*> 7e1179d0 muleu_s\.ph\.qbr t7,s0,s1
0+0120 <[^>]*> 7e3287d0 mulq_rs\.ph s0,s1,s2
0+0124 <[^>]*> 7e538f10 muleq_s\.w\.phl s1,s2,s3
0+0128 <[^>]*> 7e749750 muleq_s\.w\.phr s2,s3,s4
0+012c <[^>]*> 7e7400f0 dpau\.h\.qbl \$ac0,s3,s4
0+0130 <[^>]*> 7e9509f0 dpau\.h\.qbr \$ac1,s4,s5
0+0134 <[^>]*> 7eb612f0 dpsu\.h\.qbl \$ac2,s5,s6
0+0138 <[^>]*> 7ed71bf0 dpsu\.h\.qbr \$ac3,s6,s7
0+013c <[^>]*> 7ef80130 dpaq_s\.w\.ph \$ac0,s7,t8
0+0140 <[^>]*> 7f190970 dpsq_s\.w\.ph \$ac1,t8,t9
0+0144 <[^>]*> 7f3a11b0 mulsaq_s\.w\.ph \$ac2,t9,k0
0+0148 <[^>]*> 7f5b1b30 dpaq_sa\.l\.w \$ac3,k0,k1
0+014c <[^>]*> 7f7c0370 dpsq_sa\.l\.w \$ac0,k1,gp
0+0150 <[^>]*> 7f9d0d30 maq_s\.w\.phl \$ac1,gp,sp
0+0154 <[^>]*> 7fbe15b0 maq_s\.w\.phr \$ac2,sp,s8
0+0158 <[^>]*> 7fdf1c30 maq_sa\.w\.phl \$ac3,s8,ra
0+015c <[^>]*> 7fe004b0 maq_sa\.w\.phr \$ac0,ra,zero
0+0160 <[^>]*> 7c0106d2 bitrev zero,at
0+0164 <[^>]*> 7c41000c insv at,v0
0+0168 <[^>]*> 7cff1092 repl\.qb v0,0xff
0+016c <[^>]*> 7c001092 repl\.qb v0,0x0
0+0170 <[^>]*> 7cff1092 repl\.qb v0,0xff
0+0174 <[^>]*> 7c001092 repl\.qb v0,0x0
0+0178 <[^>]*> 7c0418d2 replv\.qb v1,a0
0+017c <[^>]*> 7dff2292 repl\.ph a0,511
0+0180 <[^>]*> 7e002292 repl\.ph a0,-512
0+0184 <[^>]*> 7dff2292 repl\.ph a0,511
0+0188 <[^>]*> 7e002292 repl\.ph a0,-512
0+018c <[^>]*> 7c062ad2 replv\.ph a1,a2
0+0190 <[^>]*> 7cc70011 cmpu\.eq\.qb a2,a3
0+0194 <[^>]*> 7ce80051 cmpu\.lt\.qb a3,t0
0+0198 <[^>]*> 7d090091 cmpu\.le\.qb t0,t1
0+019c <[^>]*> 7d4b4911 cmpgu\.eq\.qb t1,t2,t3
0+01a0 <[^>]*> 7d6c5151 cmpgu\.lt\.qb t2,t3,t4
0+01a4 <[^>]*> 7d8d5991 cmpgu\.le\.qb t3,t4,t5
0+01a8 <[^>]*> 7d8d0211 cmp\.eq\.ph t4,t5
0+01ac <[^>]*> 7dae0251 cmp\.lt\.ph t5,t6
0+01b0 <[^>]*> 7dcf0291 cmp\.le\.ph t6,t7
0+01b4 <[^>]*> 7e1178d1 pick\.qb t7,s0,s1
0+01b8 <[^>]*> 7e3282d1 pick\.ph s0,s1,s2
0+01bc <[^>]*> 7e538b91 packrl\.ph s1,s2,s3
0+01c0 <[^>]*> 7ff20838 extr\.w s2,\$ac1,0x1f
0+01c4 <[^>]*> 7c120838 extr\.w s2,\$ac1,0x0
0+01c8 <[^>]*> 7ff20838 extr\.w s2,\$ac1,0x1f
0+01cc <[^>]*> 7c120838 extr\.w s2,\$ac1,0x0
0+01d0 <[^>]*> 7ff31138 extr_r\.w s3,\$ac2,0x1f
0+01d4 <[^>]*> 7c131138 extr_r\.w s3,\$ac2,0x0
0+01d8 <[^>]*> 7ff31138 extr_r\.w s3,\$ac2,0x1f
0+01dc <[^>]*> 7c131138 extr_r\.w s3,\$ac2,0x0
0+01e0 <[^>]*> 7ff419b8 extr_rs\.w s4,\$ac3,0x1f
0+01e4 <[^>]*> 7c1419b8 extr_rs\.w s4,\$ac3,0x0
0+01e8 <[^>]*> 7ff419b8 extr_rs\.w s4,\$ac3,0x1f
0+01ec <[^>]*> 7c1419b8 extr_rs\.w s4,\$ac3,0x0
0+01f0 <[^>]*> 7ff503b8 extr_s\.h s5,\$ac0,0x1f
0+01f4 <[^>]*> 7c1503b8 extr_s\.h s5,\$ac0,0x0
0+01f8 <[^>]*> 7ff503b8 extr_s\.h s5,\$ac0,0x1f
0+01fc <[^>]*> 7c1503b8 extr_s\.h s5,\$ac0,0x0
0+0200 <[^>]*> 7ef60bf8 extrv_s\.h s6,\$ac1,s7
0+0204 <[^>]*> 7f171078 extrv\.w s7,\$ac2,t8
0+0208 <[^>]*> 7f381978 extrv_r\.w t8,\$ac3,t9
0+020c <[^>]*> 7f5901f8 extrv_rs\.w t9,\$ac0,k0
0+0210 <[^>]*> 7ffa08b8 extp k0,\$ac1,0x1f
0+0214 <[^>]*> 7c1a08b8 extp k0,\$ac1,0x0
0+0218 <[^>]*> 7ffa08b8 extp k0,\$ac1,0x1f
0+021c <[^>]*> 7c1a08b8 extp k0,\$ac1,0x0
0+0220 <[^>]*> 7f9b10f8 extpv k1,\$ac2,gp
0+0224 <[^>]*> 7ffc1ab8 extpdp gp,\$ac3,0x1f
0+0228 <[^>]*> 7c1c1ab8 extpdp gp,\$ac3,0x0
0+022c <[^>]*> 7ffc1ab8 extpdp gp,\$ac3,0x1f
0+0230 <[^>]*> 7c1c1ab8 extpdp gp,\$ac3,0x0
0+0234 <[^>]*> 7fdd02f8 extpdpv sp,\$ac0,s8
0+0238 <[^>]*> 7df00eb8 shilo \$ac1,31
0+023c <[^>]*> 7e000eb8 shilo \$ac1,-32
0+0240 <[^>]*> 7df00eb8 shilo \$ac1,31
0+0244 <[^>]*> 7e000eb8 shilo \$ac1,-32
0+0248 <[^>]*> 7fc016f8 shilov \$ac2,s8
0+024c <[^>]*> 7fe01ff8 mthlip ra,\$ac3
0+0250 <[^>]*> 00000010 mfhi zero
0+0254 <[^>]*> 00200812 mflo at,\$ac1
0+0258 <[^>]*> 00401011 mthi v0,\$ac2
0+025c <[^>]*> 00601813 mtlo v1,\$ac3
0+0260 <[^>]*> 7c81fcf8 wrdsp a0,0x3f
0+0264 <[^>]*> 7c8004f8 wrdsp a0,0x0
0+0268 <[^>]*> 7c81fcf8 wrdsp a0,0x3f
0+026c <[^>]*> 7c8004f8 wrdsp a0,0x0
0+0270 <[^>]*> 7cbffcf8 wrdsp a1
0+0274 <[^>]*> 7c3f34b8 rddsp a2,0x3f
0+0278 <[^>]*> 7c0034b8 rddsp a2,0x0
0+027c <[^>]*> 7c3f34b8 rddsp a2,0x3f
0+0280 <[^>]*> 7c0034b8 rddsp a2,0x0
0+0284 <[^>]*> 7fff3cb8 rddsp a3
0+0288 <[^>]*> 7d49418a lbux t0,t1\(t2\)
0+028c <[^>]*> 7d6a490a lhx t1,t2\(t3\)
0+0290 <[^>]*> 7d8b500a lwx t2,t3\(t4\)
0+0294 <[^>]*> 041cff5a bposge32 0+0000 <text_label>
0+0298 <[^>]*> 00000000 nop
...
0+0078 <[^>]*> 7c1ff013 shll\.qb s8,ra,0x0
0+007c <[^>]*> 7cfff013 shll\.qb s8,ra,0x7
0+0080 <[^>]*> 7c20f893 shllv\.qb ra,zero,at
0+0084 <[^>]*> 7c010213 shll\.ph zero,at,0x0
0+0088 <[^>]*> 7de10213 shll\.ph zero,at,0xf
0+008c <[^>]*> 7c620a93 shllv\.ph at,v0,v1
0+0090 <[^>]*> 7c031313 shll_s\.ph v0,v1,0x0
0+0094 <[^>]*> 7de31313 shll_s\.ph v0,v1,0xf
0+0098 <[^>]*> 7ca41b93 shllv_s\.ph v1,a0,a1
0+009c <[^>]*> 7c052513 shll_s\.w a0,a1,0x0
0+00a0 <[^>]*> 7fe52513 shll_s\.w a0,a1,0x1f
0+00a4 <[^>]*> 7ce62d93 shllv_s\.w a1,a2,a3
0+00a8 <[^>]*> 7c073053 shrl\.qb a2,a3,0x0
0+00ac <[^>]*> 7ce73053 shrl\.qb a2,a3,0x7
0+00b0 <[^>]*> 7d2838d3 shrlv\.qb a3,t0,t1
0+00b4 <[^>]*> 7c094253 shra\.ph t0,t1,0x0
0+00b8 <[^>]*> 7de94253 shra\.ph t0,t1,0xf
0+00bc <[^>]*> 7d6a4ad3 shrav\.ph t1,t2,t3
0+00c0 <[^>]*> 7c0b5353 shra_r\.ph t2,t3,0x0
0+00c4 <[^>]*> 7deb5353 shra_r\.ph t2,t3,0xf
0+00c8 <[^>]*> 7dac5bd3 shrav_r\.ph t3,t4,t5
0+00cc <[^>]*> 7c0d6553 shra_r\.w t4,t5,0x0
0+00d0 <[^>]*> 7fed6553 shra_r\.w t4,t5,0x1f
0+00d4 <[^>]*> 7dee6dd3 shrav_r\.w t5,t6,t7
0+00d8 <[^>]*> 7df07190 muleu_s\.ph\.qbl t6,t7,s0
0+00dc <[^>]*> 7e1179d0 muleu_s\.ph\.qbr t7,s0,s1
0+00e0 <[^>]*> 7e3287d0 mulq_rs\.ph s0,s1,s2
0+00e4 <[^>]*> 7e538f10 muleq_s\.w\.phl s1,s2,s3
0+00e8 <[^>]*> 7e749750 muleq_s\.w\.phr s2,s3,s4
0+00ec <[^>]*> 7e7400f0 dpau\.h\.qbl \$ac0,s3,s4
0+00f0 <[^>]*> 7e9509f0 dpau\.h\.qbr \$ac1,s4,s5
0+00f4 <[^>]*> 7eb612f0 dpsu\.h\.qbl \$ac2,s5,s6
0+00f8 <[^>]*> 7ed71bf0 dpsu\.h\.qbr \$ac3,s6,s7
0+00fc <[^>]*> 7ef80130 dpaq_s\.w\.ph \$ac0,s7,t8
0+0100 <[^>]*> 7f190970 dpsq_s\.w\.ph \$ac1,t8,t9
0+0104 <[^>]*> 7f3a11b0 mulsaq_s\.w\.ph \$ac2,t9,k0
0+0108 <[^>]*> 7f5b1b30 dpaq_sa\.l\.w \$ac3,k0,k1
0+010c <[^>]*> 7f7c0370 dpsq_sa\.l\.w \$ac0,k1,gp
0+0110 <[^>]*> 7f9d0d30 maq_s\.w\.phl \$ac1,gp,sp
0+0114 <[^>]*> 7fbe15b0 maq_s\.w\.phr \$ac2,sp,s8
0+0118 <[^>]*> 7fdf1c30 maq_sa\.w\.phl \$ac3,s8,ra
0+011c <[^>]*> 7fe004b0 maq_sa\.w\.phr \$ac0,ra,zero
0+0120 <[^>]*> 7c0106d2 bitrev zero,at
0+0124 <[^>]*> 7c41000c insv at,v0
0+0128 <[^>]*> 7c001092 repl\.qb v0,0x0
0+012c <[^>]*> 7cff1092 repl\.qb v0,0xff
0+0130 <[^>]*> 7c0418d2 replv\.qb v1,a0
0+0134 <[^>]*> 7e002292 repl\.ph a0,-512
0+0138 <[^>]*> 7dff2292 repl\.ph a0,511
0+013c <[^>]*> 7c062ad2 replv\.ph a1,a2
0+0140 <[^>]*> 7cc70011 cmpu\.eq\.qb a2,a3
0+0144 <[^>]*> 7ce80051 cmpu\.lt\.qb a3,t0
0+0148 <[^>]*> 7d090091 cmpu\.le\.qb t0,t1
0+014c <[^>]*> 7d4b4911 cmpgu\.eq\.qb t1,t2,t3
0+0150 <[^>]*> 7d6c5151 cmpgu\.lt\.qb t2,t3,t4
0+0154 <[^>]*> 7d8d5991 cmpgu\.le\.qb t3,t4,t5
0+0158 <[^>]*> 7d8d0211 cmp\.eq\.ph t4,t5
0+015c <[^>]*> 7dae0251 cmp\.lt\.ph t5,t6
0+0160 <[^>]*> 7dcf0291 cmp\.le\.ph t6,t7
0+0164 <[^>]*> 7e1178d1 pick\.qb t7,s0,s1
0+0168 <[^>]*> 7e3282d1 pick\.ph s0,s1,s2
0+016c <[^>]*> 7e538b91 packrl\.ph s1,s2,s3
0+0170 <[^>]*> 7c120838 extr\.w s2,\$ac1,0x0
0+0174 <[^>]*> 7ff20838 extr\.w s2,\$ac1,0x1f
0+0178 <[^>]*> 7c131138 extr_r\.w s3,\$ac2,0x0
0+017c <[^>]*> 7ff31138 extr_r\.w s3,\$ac2,0x1f
0+0180 <[^>]*> 7c1419b8 extr_rs\.w s4,\$ac3,0x0
0+0184 <[^>]*> 7ff419b8 extr_rs\.w s4,\$ac3,0x1f
0+0188 <[^>]*> 7c1503b8 extr_s\.h s5,\$ac0,0x0
0+018c <[^>]*> 7ff503b8 extr_s\.h s5,\$ac0,0x1f
0+0190 <[^>]*> 7ef60bf8 extrv_s\.h s6,\$ac1,s7
0+0194 <[^>]*> 7f171078 extrv\.w s7,\$ac2,t8
0+0198 <[^>]*> 7f381978 extrv_r\.w t8,\$ac3,t9
0+019c <[^>]*> 7f5901f8 extrv_rs\.w t9,\$ac0,k0
0+01a0 <[^>]*> 7c1a08b8 extp k0,\$ac1,0x0
0+01a4 <[^>]*> 7ffa08b8 extp k0,\$ac1,0x1f
0+01a8 <[^>]*> 7f9b10f8 extpv k1,\$ac2,gp
0+01ac <[^>]*> 7c1c1ab8 extpdp gp,\$ac3,0x0
0+01b0 <[^>]*> 7ffc1ab8 extpdp gp,\$ac3,0x1f
0+01b4 <[^>]*> 7fdd02f8 extpdpv sp,\$ac0,s8
0+01b8 <[^>]*> 7e000eb8 shilo \$ac1,-32
0+01bc <[^>]*> 7df00eb8 shilo \$ac1,31
0+01c0 <[^>]*> 7fc016f8 shilov \$ac2,s8
0+01c4 <[^>]*> 7fe01ff8 mthlip ra,\$ac3
0+01c8 <[^>]*> 00000010 mfhi zero
0+01cc <[^>]*> 00200812 mflo at,\$ac1
0+01d0 <[^>]*> 00401011 mthi v0,\$ac2
0+01d4 <[^>]*> 00601813 mtlo v1,\$ac3
0+01d8 <[^>]*> 7c8004f8 wrdsp a0,0x0
0+01dc <[^>]*> 7c81fcf8 wrdsp a0,0x3f
0+01e0 <[^>]*> 7cbffcf8 wrdsp a1
0+01e4 <[^>]*> 7c0034b8 rddsp a2,0x0
0+01e8 <[^>]*> 7c3f34b8 rddsp a2,0x3f
0+01ec <[^>]*> 7fff3cb8 rddsp a3
0+01f0 <[^>]*> 7d49418a lbux t0,t1\(t2\)
0+01f4 <[^>]*> 7d6a490a lhx t1,t2\(t3\)
0+01f8 <[^>]*> 7d8b500a lwx t2,t3\(t4\)
0+01fc <[^>]*> 041cff80 bposge32 00000000 <text_label>
0+0200 <[^>]*> 00000000 nop
\.\.\.

39
gas/testsuite/gas/mips/mips32-dsp.l
View File

@ -1,39 +0,0 @@
.*: Assembler messages:
.*:39: Warning: DSP immediate not in range 0..7 \([0-9]*\)
.*:42: Warning: DSP immediate not in range 0..7 \(8\)
.*:44: Warning: DSP immediate not in range 0..15 \([0-9]*\)
.*:47: Warning: DSP immediate not in range 0..15 \(16\)
.*:49: Warning: DSP immediate not in range 0..15 \([0-9]*\)
.*:52: Warning: DSP immediate not in range 0..15 \(16\)
.*:54: Warning: DSP immediate not in range 0..31 \([0-9]*\)
.*:57: Warning: DSP immediate not in range 0..31 \(32\)
.*:59: Warning: DSP immediate not in range 0..7 \([0-9]*\)
.*:62: Warning: DSP immediate not in range 0..7 \(8\)
.*:64: Warning: DSP immediate not in range 0..15 \([0-9]*\)
.*:67: Warning: DSP immediate not in range 0..15 \(16\)
.*:69: Warning: DSP immediate not in range 0..15 \([0-9]*\)
.*:72: Warning: DSP immediate not in range 0..15 \(16\)
.*:74: Warning: DSP immediate not in range 0..31 \([0-9]*\)
.*:77: Warning: DSP immediate not in range 0..31 \(32\)
.*:99: Warning: DSP immediate not in range 0..255 \([0-9]*\)
.*:102: Warning: DSP immediate not in range 0..255 \(256\)
.*:104: Warning: DSP immediate not in range -512..511 \(-513\)
.*:107: Warning: DSP immediate not in range -512..511 \(512\)
.*:121: Warning: DSP immediate not in range 0..31 \([0-9]*\)
.*:124: Warning: DSP immediate not in range 0..31 \(32\)
.*:125: Warning: DSP immediate not in range 0..31 \([0-9]*\)
.*:128: Warning: DSP immediate not in range 0..31 \(32\)
.*:129: Warning: DSP immediate not in range 0..31 \([0-9]*\)
.*:132: Warning: DSP immediate not in range 0..31 \(32\)
.*:133: Warning: DSP immediate not in range 0..31 \([0-9]*\)
.*:136: Warning: DSP immediate not in range 0..31 \(32\)
.*:141: Warning: DSP immediate not in range 0..31 \([0-9]*\)
.*:144: Warning: DSP immediate not in range 0..31 \(32\)
.*:146: Warning: DSP immediate not in range 0..31 \([0-9]*\)
.*:149: Warning: DSP immediate not in range 0..31 \(32\)
.*:151: Warning: DSP immediate not in range -32..31 \(-33\)
.*:154: Warning: DSP immediate not in range -32..31 \(32\)
.*:161: Warning: DSP immediate not in range 0..63 \([0-9]*\)
.*:164: Warning: DSP immediate not in range 0..63 \(64\)
.*:166: Warning: DSP immediate not in range 0..63 \([0-9]*\)
.*:169: Warning: DSP immediate not in range 0..63 \(64\)

39
gas/testsuite/gas/mips/mips32-dsp.s
View File

@ -1,6 +1,7 @@
# source file to test assembly of MIPS DSP ASE for MIPS32 instructions
.set noreorder
.set nomacro
.set noat
.text
@ -36,45 +37,29 @@ text_label:
preceu.ph.qbr $27,$28
preceu.ph.qbla $28,$29
preceu.ph.qbra $29,$30
shll.qb $30,$31,-1
shll.qb $30,$31,0
shll.qb $30,$31,7
shll.qb $30,$31,8
shllv.qb $31,$0,$1
shll.ph $0,$1,-1
shll.ph $0,$1,0
shll.ph $0,$1,15
shll.ph $0,$1,16
shllv.ph $1,$2,$3
shll_s.ph $2,$3,-1
shll_s.ph $2,$3,0
shll_s.ph $2,$3,15
shll_s.ph $2,$3,16
shllv_s.ph $3,$4,$5
shll_s.w $4,$5,-1
shll_s.w $4,$5,0
shll_s.w $4,$5,31
shll_s.w $4,$5,32
shllv_s.w $5,$6,$7
shrl.qb $6,$7,-1
shrl.qb $6,$7,0
shrl.qb $6,$7,7
shrl.qb $6,$7,8
shrlv.qb $7,$8,$9
shra.ph $8,$9,-1
shra.ph $8,$9,0
shra.ph $8,$9,15
shra.ph $8,$9,16
shrav.ph $9,$10,$11
shra_r.ph $10,$11,-1
shra_r.ph $10,$11,0
shra_r.ph $10,$11,15
shra_r.ph $10,$11,16
shrav_r.ph $11,$12,$13
shra_r.w $12,$13,-1
shra_r.w $12,$13,0
shra_r.w $12,$13,31
shra_r.w $12,$13,32
shrav_r.w $13,$14,$15
muleu_s.ph.qbl $14,$15,$16
muleu_s.ph.qbr $15,$16,$17
@ -96,15 +81,11 @@ text_label:
maq_sa.w.phr $ac0,$31,$0
bitrev $0,$1
insv $1,$2
repl.qb $2,-1
repl.qb $2,0
repl.qb $2,255
repl.qb $2,256
replv.qb $3,$4
repl.ph $4,-513
repl.ph $4,-512
repl.ph $4,511
repl.ph $4,512
replv.ph $5,$6
cmpu.eq.qb $6,$7
cmpu.lt.qb $7,$8
@ -118,55 +99,37 @@ text_label:
pick.qb $15,$16,$17
pick.ph $16,$17,$18
packrl.ph $17,$18,$19
extr.w $18,$ac1,-1
extr.w $18,$ac1,0
extr.w $18,$ac1,31
extr.w $18,$ac1,32
extr_r.w $19,$ac2,-1
extr_r.w $19,$ac2,0
extr_r.w $19,$ac2,31
extr_r.w $19,$ac2,32
extr_rs.w $20,$ac3,-1
extr_rs.w $20,$ac3,0
extr_rs.w $20,$ac3,31
extr_rs.w $20,$ac3,32
extr_s.h $21,$ac0,-1
extr_s.h $21,$ac0,0
extr_s.h $21,$ac0,31
extr_s.h $21,$ac0,32
extrv_s.h $22,$ac1,$23
extrv.w $23,$ac2,$24
extrv_r.w $24,$ac3,$25
extrv_rs.w $25,$ac0,$26
extp $26,$ac1,-1
extp $26,$ac1,0
extp $26,$ac1,31
extp $26,$ac1,32
extpv $27,$ac2,$28
extpdp $28,$ac3,-1
extpdp $28,$ac3,0
extpdp $28,$ac3,31
extpdp $28,$ac3,32
extpdpv $29,$ac0,$30
shilo $ac1,-33
shilo $ac1,-32
shilo $ac1,31
shilo $ac1,32
shilov $ac2,$30
mthlip $31,$ac3
mfhi $0,$ac0
mflo $1,$ac1
mthi $2,$ac2
mtlo $3,$ac3
wrdsp $4,-1
wrdsp $4,0
wrdsp $4,63
wrdsp $4,64
wrdsp $5
rddsp $6,-1
rddsp $6,0
rddsp $6,63
rddsp $6,64
rddsp $7
lbux $8,$9($10)
lhx $9,$10($11)

320
gas/testsuite/gas/mips/mips32-mt.d
View File

@ -567,260 +567,68 @@ Disassembly of section .text:
0+08b0 <[^>]*> 418a5824 mttc2 t2,\$11
0+08b4 <[^>]*> 418b6034 mtthc2 t3,\$12
0+08b8 <[^>]*> 418c6825 cttc2 t4,\$13
0+08bc <[^>]*> 410e6830 mftr t5,t6,1,0,1
0+08c0 <[^>]*> 410e6831 mftr t5,t6,1,1,1
0+08c4 <[^>]*> 410e6832 mfthc1 t5,\$f14
0+08c8 <[^>]*> 410e6833 mftr t5,t6,1,3,1
0+08cc <[^>]*> 410e6834 mfthc2 t5,\$14
0+08d0 <[^>]*> 410e6835 mftr t5,t6,1,5,1
0+08d4 <[^>]*> 410e6836 mftr t5,t6,1,6,1
0+08d8 <[^>]*> 410e6837 mftr t5,t6,1,7,1
0+08dc <[^>]*> 410e6820 mftgpr t5,t6
0+08e0 <[^>]*> 410e6821 mftacx t5,\$ac3
0+08e4 <[^>]*> 410e6822 mftc1 t5,\$f14
0+08e8 <[^>]*> 410e6823 cftc1 t5,\$14
0+08ec <[^>]*> 410e6824 mftc2 t5,\$14
0+08f0 <[^>]*> 410e6825 cftc2 t5,\$14
0+08f4 <[^>]*> 410e6826 mftr t5,t6,1,6,0
0+08f8 <[^>]*> 410e6827 mftr t5,t6,1,7,0
0+08fc <[^>]*> 410e6830 mftr t5,t6,1,0,1
0+0900 <[^>]*> 410e6831 mftr t5,t6,1,1,1
0+0904 <[^>]*> 410e6832 mfthc1 t5,\$f14
0+0908 <[^>]*> 410e6833 mftr t5,t6,1,3,1
0+090c <[^>]*> 410e6834 mfthc2 t5,\$14
0+0910 <[^>]*> 410e6835 mftr t5,t6,1,5,1
0+0914 <[^>]*> 410e6836 mftr t5,t6,1,6,1
0+0918 <[^>]*> 410e6837 mftr t5,t6,1,7,1
0+091c <[^>]*> 410e6820 mftgpr t5,t6
0+0920 <[^>]*> 410e6821 mftacx t5,\$ac3
0+0924 <[^>]*> 410e6822 mftc1 t5,\$f14
0+0928 <[^>]*> 410e6823 cftc1 t5,\$14
0+092c <[^>]*> 410e6824 mftc2 t5,\$14
0+0930 <[^>]*> 410e6825 cftc2 t5,\$14
0+0934 <[^>]*> 410e6826 mftr t5,t6,1,6,0
0+0938 <[^>]*> 410e6827 mftr t5,t6,1,7,0
0+093c <[^>]*> 410e6810 mftr t5,t6,0,0,1
0+0940 <[^>]*> 410e6811 mftr t5,t6,0,1,1
0+0944 <[^>]*> 410e6812 mftr t5,t6,0,2,1
0+0948 <[^>]*> 410e6813 mftr t5,t6,0,3,1
0+094c <[^>]*> 410e6814 mftr t5,t6,0,4,1
0+0950 <[^>]*> 410e6815 mftr t5,t6,0,5,1
0+0954 <[^>]*> 410e6816 mftr t5,t6,0,6,1
0+0958 <[^>]*> 410e6817 mftr t5,t6,0,7,1
0+095c <[^>]*> 410e6800 mftc0 t5,c0_epc
0+0960 <[^>]*> 410e6801 mftc0 t5,\$14,1
0+0964 <[^>]*> 410e6802 mftc0 t5,\$14,2
0+0968 <[^>]*> 410e6803 mftc0 t5,\$14,3
0+096c <[^>]*> 410e6804 mftc0 t5,\$14,4
0+0970 <[^>]*> 410e6805 mftc0 t5,\$14,5
0+0974 <[^>]*> 410e6806 mftc0 t5,\$14,6
0+0978 <[^>]*> 410e6807 mftc0 t5,\$14,7
0+097c <[^>]*> 410e6810 mftr t5,t6,0,0,1
0+0980 <[^>]*> 410e6811 mftr t5,t6,0,1,1
0+0984 <[^>]*> 410e6812 mftr t5,t6,0,2,1
0+0988 <[^>]*> 410e6813 mftr t5,t6,0,3,1
0+098c <[^>]*> 410e6814 mftr t5,t6,0,4,1
0+0990 <[^>]*> 410e6815 mftr t5,t6,0,5,1
0+0994 <[^>]*> 410e6816 mftr t5,t6,0,6,1
0+0998 <[^>]*> 410e6817 mftr t5,t6,0,7,1
0+099c <[^>]*> 410e6800 mftc0 t5,c0_epc
0+09a0 <[^>]*> 410e6801 mftc0 t5,\$14,1
0+09a4 <[^>]*> 410e6802 mftc0 t5,\$14,2
0+09a8 <[^>]*> 410e6803 mftc0 t5,\$14,3
0+09ac <[^>]*> 410e6804 mftc0 t5,\$14,4
0+09b0 <[^>]*> 410e6805 mftc0 t5,\$14,5
0+09b4 <[^>]*> 410e6806 mftc0 t5,\$14,6
0+09b8 <[^>]*> 410e6807 mftc0 t5,\$14,7
0+09bc <[^>]*> 410e6830 mftr t5,t6,1,0,1
0+09c0 <[^>]*> 410e6831 mftr t5,t6,1,1,1
0+09c4 <[^>]*> 410e6832 mfthc1 t5,\$f14
0+09c8 <[^>]*> 410e6833 mftr t5,t6,1,3,1
0+09cc <[^>]*> 410e6834 mfthc2 t5,\$14
0+09d0 <[^>]*> 410e6835 mftr t5,t6,1,5,1
0+09d4 <[^>]*> 410e6836 mftr t5,t6,1,6,1
0+09d8 <[^>]*> 410e6837 mftr t5,t6,1,7,1
0+09dc <[^>]*> 410e6820 mftgpr t5,t6
0+09e0 <[^>]*> 410e6821 mftacx t5,\$ac3
0+09e4 <[^>]*> 410e6822 mftc1 t5,\$f14
0+09e8 <[^>]*> 410e6823 cftc1 t5,\$14
0+09ec <[^>]*> 410e6824 mftc2 t5,\$14
0+09f0 <[^>]*> 410e6825 cftc2 t5,\$14
0+09f4 <[^>]*> 410e6826 mftr t5,t6,1,6,0
0+09f8 <[^>]*> 410e6827 mftr t5,t6,1,7,0
0+09fc <[^>]*> 410e6830 mftr t5,t6,1,0,1
0+0a00 <[^>]*> 410e6831 mftr t5,t6,1,1,1
0+0a04 <[^>]*> 410e6832 mfthc1 t5,\$f14
0+0a08 <[^>]*> 410e6833 mftr t5,t6,1,3,1
0+0a0c <[^>]*> 410e6834 mfthc2 t5,\$14
0+0a10 <[^>]*> 410e6835 mftr t5,t6,1,5,1
0+0a14 <[^>]*> 410e6836 mftr t5,t6,1,6,1
0+0a18 <[^>]*> 410e6837 mftr t5,t6,1,7,1
0+0a1c <[^>]*> 410e6820 mftgpr t5,t6
0+0a20 <[^>]*> 410e6821 mftacx t5,\$ac3
0+0a24 <[^>]*> 410e6822 mftc1 t5,\$f14
0+0a28 <[^>]*> 410e6823 cftc1 t5,\$14
0+0a2c <[^>]*> 410e6824 mftc2 t5,\$14
0+0a30 <[^>]*> 410e6825 cftc2 t5,\$14
0+0a34 <[^>]*> 410e6826 mftr t5,t6,1,6,0
0+0a38 <[^>]*> 410e6827 mftr t5,t6,1,7,0
0+0a3c <[^>]*> 410e6810 mftr t5,t6,0,0,1
0+0a40 <[^>]*> 410e6811 mftr t5,t6,0,1,1
0+0a44 <[^>]*> 410e6812 mftr t5,t6,0,2,1
0+0a48 <[^>]*> 410e6813 mftr t5,t6,0,3,1
0+0a4c <[^>]*> 410e6814 mftr t5,t6,0,4,1
0+0a50 <[^>]*> 410e6815 mftr t5,t6,0,5,1
0+0a54 <[^>]*> 410e6816 mftr t5,t6,0,6,1
0+0a58 <[^>]*> 410e6817 mftr t5,t6,0,7,1
0+0a5c <[^>]*> 410e6800 mftc0 t5,c0_epc
0+0a60 <[^>]*> 410e6801 mftc0 t5,\$14,1
0+0a64 <[^>]*> 410e6802 mftc0 t5,\$14,2
0+0a68 <[^>]*> 410e6803 mftc0 t5,\$14,3
0+0a6c <[^>]*> 410e6804 mftc0 t5,\$14,4
0+0a70 <[^>]*> 410e6805 mftc0 t5,\$14,5
0+0a74 <[^>]*> 410e6806 mftc0 t5,\$14,6
0+0a78 <[^>]*> 410e6807 mftc0 t5,\$14,7
0+0a7c <[^>]*> 410e6810 mftr t5,t6,0,0,1
0+0a80 <[^>]*> 410e6811 mftr t5,t6,0,1,1
0+0a84 <[^>]*> 410e6812 mftr t5,t6,0,2,1
0+0a88 <[^>]*> 410e6813 mftr t5,t6,0,3,1
0+0a8c <[^>]*> 410e6814 mftr t5,t6,0,4,1
0+0a90 <[^>]*> 410e6815 mftr t5,t6,0,5,1
0+0a94 <[^>]*> 410e6816 mftr t5,t6,0,6,1
0+0a98 <[^>]*> 410e6817 mftr t5,t6,0,7,1
0+0a9c <[^>]*> 410e6800 mftc0 t5,c0_epc
0+0aa0 <[^>]*> 410e6801 mftc0 t5,\$14,1
0+0aa4 <[^>]*> 410e6802 mftc0 t5,\$14,2
0+0aa8 <[^>]*> 410e6803 mftc0 t5,\$14,3
0+0aac <[^>]*> 410e6804 mftc0 t5,\$14,4
0+0ab0 <[^>]*> 410e6805 mftc0 t5,\$14,5
0+0ab4 <[^>]*> 410e6806 mftc0 t5,\$14,6
0+0ab8 <[^>]*> 410e6807 mftc0 t5,\$14,7
0+0abc <[^>]*> 418d7030 mttr t5,t6,1,0,1
0+0ac0 <[^>]*> 418d7031 mttr t5,t6,1,1,1
0+0ac4 <[^>]*> 418d7032 mtthc1 t5,\$f14
0+0ac8 <[^>]*> 418d7033 mttr t5,t6,1,3,1
0+0acc <[^>]*> 418d7034 mtthc2 t5,\$14
0+0ad0 <[^>]*> 418d7035 mttr t5,t6,1,5,1
0+0ad4 <[^>]*> 418d7036 mttr t5,t6,1,6,1
0+0ad8 <[^>]*> 418d7037 mttr t5,t6,1,7,1
0+0adc <[^>]*> 418d7020 mttgpr t5,t6
0+0ae0 <[^>]*> 418d7021 mttacx t5,\$ac3
0+0ae4 <[^>]*> 418d7022 mttc1 t5,\$f14
0+0ae8 <[^>]*> 418d7023 cttc1 t5,\$14
0+0aec <[^>]*> 418d7024 mttc2 t5,\$14
0+0af0 <[^>]*> 418d7025 cttc2 t5,\$14
0+0af4 <[^>]*> 418d7026 mttr t5,t6,1,6,0
0+0af8 <[^>]*> 418d7027 mttr t5,t6,1,7,0
0+0afc <[^>]*> 418d7030 mttr t5,t6,1,0,1
0+0b00 <[^>]*> 418d7031 mttr t5,t6,1,1,1
0+0b04 <[^>]*> 418d7032 mtthc1 t5,\$f14
0+0b08 <[^>]*> 418d7033 mttr t5,t6,1,3,1
0+0b0c <[^>]*> 418d7034 mtthc2 t5,\$14
0+0b10 <[^>]*> 418d7035 mttr t5,t6,1,5,1
0+0b14 <[^>]*> 418d7036 mttr t5,t6,1,6,1
0+0b18 <[^>]*> 418d7037 mttr t5,t6,1,7,1
0+0b1c <[^>]*> 418d7020 mttgpr t5,t6
0+0b20 <[^>]*> 418d7021 mttacx t5,\$ac3
0+0b24 <[^>]*> 418d7022 mttc1 t5,\$f14
0+0b28 <[^>]*> 418d7023 cttc1 t5,\$14
0+0b2c <[^>]*> 418d7024 mttc2 t5,\$14
0+0b30 <[^>]*> 418d7025 cttc2 t5,\$14
0+0b34 <[^>]*> 418d7026 mttr t5,t6,1,6,0
0+0b38 <[^>]*> 418d7027 mttr t5,t6,1,7,0
0+0b3c <[^>]*> 418d7010 mttr t5,t6,0,0,1
0+0b40 <[^>]*> 418d7011 mttr t5,t6,0,1,1
0+0b44 <[^>]*> 418d7012 mttr t5,t6,0,2,1
0+0b48 <[^>]*> 418d7013 mttr t5,t6,0,3,1
0+0b4c <[^>]*> 418d7014 mttr t5,t6,0,4,1
0+0b50 <[^>]*> 418d7015 mttr t5,t6,0,5,1
0+0b54 <[^>]*> 418d7016 mttr t5,t6,0,6,1
0+0b58 <[^>]*> 418d7017 mttr t5,t6,0,7,1
0+0b5c <[^>]*> 418d7000 mttc0 t5,c0_epc
0+0b60 <[^>]*> 418d7001 mttc0 t5,\$14,1
0+0b64 <[^>]*> 418d7002 mttc0 t5,\$14,2
0+0b68 <[^>]*> 418d7003 mttc0 t5,\$14,3
0+0b6c <[^>]*> 418d7004 mttc0 t5,\$14,4
0+0b70 <[^>]*> 418d7005 mttc0 t5,\$14,5
0+0b74 <[^>]*> 418d7006 mttc0 t5,\$14,6
0+0b78 <[^>]*> 418d7007 mttc0 t5,\$14,7
0+0b7c <[^>]*> 418d7010 mttr t5,t6,0,0,1
0+0b80 <[^>]*> 418d7011 mttr t5,t6,0,1,1
0+0b84 <[^>]*> 418d7012 mttr t5,t6,0,2,1
0+0b88 <[^>]*> 418d7013 mttr t5,t6,0,3,1
0+0b8c <[^>]*> 418d7014 mttr t5,t6,0,4,1
0+0b90 <[^>]*> 418d7015 mttr t5,t6,0,5,1
0+0b94 <[^>]*> 418d7016 mttr t5,t6,0,6,1
0+0b98 <[^>]*> 418d7017 mttr t5,t6,0,7,1
0+0b9c <[^>]*> 418d7000 mttc0 t5,c0_epc
0+0ba0 <[^>]*> 418d7001 mttc0 t5,\$14,1
0+0ba4 <[^>]*> 418d7002 mttc0 t5,\$14,2
0+0ba8 <[^>]*> 418d7003 mttc0 t5,\$14,3
0+0bac <[^>]*> 418d7004 mttc0 t5,\$14,4
0+0bb0 <[^>]*> 418d7005 mttc0 t5,\$14,5
0+0bb4 <[^>]*> 418d7006 mttc0 t5,\$14,6
0+0bb8 <[^>]*> 418d7007 mttc0 t5,\$14,7
0+0bbc <[^>]*> 418d7030 mttr t5,t6,1,0,1
0+0bc0 <[^>]*> 418d7031 mttr t5,t6,1,1,1
0+0bc4 <[^>]*> 418d7032 mtthc1 t5,\$f14
0+0bc8 <[^>]*> 418d7033 mttr t5,t6,1,3,1
0+0bcc <[^>]*> 418d7034 mtthc2 t5,\$14
0+0bd0 <[^>]*> 418d7035 mttr t5,t6,1,5,1
0+0bd4 <[^>]*> 418d7036 mttr t5,t6,1,6,1
0+0bd8 <[^>]*> 418d7037 mttr t5,t6,1,7,1
0+0bdc <[^>]*> 418d7020 mttgpr t5,t6
0+0be0 <[^>]*> 418d7021 mttacx t5,\$ac3
0+0be4 <[^>]*> 418d7022 mttc1 t5,\$f14
0+0be8 <[^>]*> 418d7023 cttc1 t5,\$14
0+0bec <[^>]*> 418d7024 mttc2 t5,\$14
0+0bf0 <[^>]*> 418d7025 cttc2 t5,\$14
0+0bf4 <[^>]*> 418d7026 mttr t5,t6,1,6,0
0+0bf8 <[^>]*> 418d7027 mttr t5,t6,1,7,0
0+0bfc <[^>]*> 418d7030 mttr t5,t6,1,0,1
0+0c00 <[^>]*> 418d7031 mttr t5,t6,1,1,1
0+0c04 <[^>]*> 418d7032 mtthc1 t5,\$f14
0+0c08 <[^>]*> 418d7033 mttr t5,t6,1,3,1
0+0c0c <[^>]*> 418d7034 mtthc2 t5,\$14
0+0c10 <[^>]*> 418d7035 mttr t5,t6,1,5,1
0+0c14 <[^>]*> 418d7036 mttr t5,t6,1,6,1
0+0c18 <[^>]*> 418d7037 mttr t5,t6,1,7,1
0+0c1c <[^>]*> 418d7020 mttgpr t5,t6
0+0c20 <[^>]*> 418d7021 mttacx t5,\$ac3
0+0c24 <[^>]*> 418d7022 mttc1 t5,\$f14
0+0c28 <[^>]*> 418d7023 cttc1 t5,\$14
0+0c2c <[^>]*> 418d7024 mttc2 t5,\$14
0+0c30 <[^>]*> 418d7025 cttc2 t5,\$14
0+0c34 <[^>]*> 418d7026 mttr t5,t6,1,6,0
0+0c38 <[^>]*> 418d7027 mttr t5,t6,1,7,0
0+0c3c <[^>]*> 418d7010 mttr t5,t6,0,0,1
0+0c40 <[^>]*> 418d7011 mttr t5,t6,0,1,1
0+0c44 <[^>]*> 418d7012 mttr t5,t6,0,2,1
0+0c48 <[^>]*> 418d7013 mttr t5,t6,0,3,1
0+0c4c <[^>]*> 418d7014 mttr t5,t6,0,4,1
0+0c50 <[^>]*> 418d7015 mttr t5,t6,0,5,1
0+0c54 <[^>]*> 418d7016 mttr t5,t6,0,6,1
0+0c58 <[^>]*> 418d7017 mttr t5,t6,0,7,1
0+0c5c <[^>]*> 418d7000 mttc0 t5,c0_epc
0+0c60 <[^>]*> 418d7001 mttc0 t5,\$14,1
0+0c64 <[^>]*> 418d7002 mttc0 t5,\$14,2
0+0c68 <[^>]*> 418d7003 mttc0 t5,\$14,3
0+0c6c <[^>]*> 418d7004 mttc0 t5,\$14,4
0+0c70 <[^>]*> 418d7005 mttc0 t5,\$14,5
0+0c74 <[^>]*> 418d7006 mttc0 t5,\$14,6
0+0c78 <[^>]*> 418d7007 mttc0 t5,\$14,7
0+0c7c <[^>]*> 418d7010 mttr t5,t6,0,0,1
0+0c80 <[^>]*> 418d7011 mttr t5,t6,0,1,1
0+0c84 <[^>]*> 418d7012 mttr t5,t6,0,2,1
0+0c88 <[^>]*> 418d7013 mttr t5,t6,0,3,1
0+0c8c <[^>]*> 418d7014 mttr t5,t6,0,4,1
0+0c90 <[^>]*> 418d7015 mttr t5,t6,0,5,1
0+0c94 <[^>]*> 418d7016 mttr t5,t6,0,6,1
0+0c98 <[^>]*> 418d7017 mttr t5,t6,0,7,1
0+0c9c <[^>]*> 418d7000 mttc0 t5,c0_epc
0+0ca0 <[^>]*> 418d7001 mttc0 t5,\$14,1
0+0ca4 <[^>]*> 418d7002 mttc0 t5,\$14,2
0+0ca8 <[^>]*> 418d7003 mttc0 t5,\$14,3
0+0cac <[^>]*> 418d7004 mttc0 t5,\$14,4
0+0cb0 <[^>]*> 418d7005 mttc0 t5,\$14,5
0+0cb4 <[^>]*> 418d7006 mttc0 t5,\$14,6
0+0cb8 <[^>]*> 418d7007 mttc0 t5,\$14,7
0+08bc <[^>]*> 410e6800 mftc0 t5,c0_epc
0+08c0 <[^>]*> 410e6801 mftc0 t5,\$14,1
0+08c4 <[^>]*> 410e6802 mftc0 t5,\$14,2
0+08c8 <[^>]*> 410e6803 mftc0 t5,\$14,3
0+08cc <[^>]*> 410e6804 mftc0 t5,\$14,4
0+08d0 <[^>]*> 410e6805 mftc0 t5,\$14,5
0+08d4 <[^>]*> 410e6806 mftc0 t5,\$14,6
0+08d8 <[^>]*> 410e6807 mftc0 t5,\$14,7
0+08dc <[^>]*> 410e6810 mftr t5,t6,0,0,1
0+08e0 <[^>]*> 410e6811 mftr t5,t6,0,1,1
0+08e4 <[^>]*> 410e6812 mftr t5,t6,0,2,1
0+08e8 <[^>]*> 410e6813 mftr t5,t6,0,3,1
0+08ec <[^>]*> 410e6814 mftr t5,t6,0,4,1
0+08f0 <[^>]*> 410e6815 mftr t5,t6,0,5,1
0+08f4 <[^>]*> 410e6816 mftr t5,t6,0,6,1
0+08f8 <[^>]*> 410e6817 mftr t5,t6,0,7,1
0+08fc <[^>]*> 410e6820 mftgpr t5,t6
0+0900 <[^>]*> 410e6821 mftacx t5,\$ac3
0+0904 <[^>]*> 410e6822 mftc1 t5,\$f14
0+0908 <[^>]*> 410e6823 cftc1 t5,\$14
0+090c <[^>]*> 410e6824 mftc2 t5,\$14
0+0910 <[^>]*> 410e6825 cftc2 t5,\$14
0+0914 <[^>]*> 410e6826 mftr t5,t6,1,6,0
0+0918 <[^>]*> 410e6827 mftr t5,t6,1,7,0
0+091c <[^>]*> 410e6830 mftr t5,t6,1,0,1
0+0920 <[^>]*> 410e6831 mftr t5,t6,1,1,1
0+0924 <[^>]*> 410e6832 mfthc1 t5,\$f14
0+0928 <[^>]*> 410e6833 mftr t5,t6,1,3,1
0+092c <[^>]*> 410e6834 mfthc2 t5,\$14
0+0930 <[^>]*> 410e6835 mftr t5,t6,1,5,1
0+0934 <[^>]*> 410e6836 mftr t5,t6,1,6,1
0+0938 <[^>]*> 410e6837 mftr t5,t6,1,7,1
0+093c <[^>]*> 418d7000 mttc0 t5,c0_epc
0+0940 <[^>]*> 418d7001 mttc0 t5,\$14,1
0+0944 <[^>]*> 418d7002 mttc0 t5,\$14,2
0+0948 <[^>]*> 418d7003 mttc0 t5,\$14,3
0+094c <[^>]*> 418d7004 mttc0 t5,\$14,4
0+0950 <[^>]*> 418d7005 mttc0 t5,\$14,5
0+0954 <[^>]*> 418d7006 mttc0 t5,\$14,6
0+0958 <[^>]*> 418d7007 mttc0 t5,\$14,7
0+095c <[^>]*> 418d7010 mttr t5,t6,0,0,1
0+0960 <[^>]*> 418d7011 mttr t5,t6,0,1,1
0+0964 <[^>]*> 418d7012 mttr t5,t6,0,2,1
0+0968 <[^>]*> 418d7013 mttr t5,t6,0,3,1
0+096c <[^>]*> 418d7014 mttr t5,t6,0,4,1
0+0970 <[^>]*> 418d7015 mttr t5,t6,0,5,1
0+0974 <[^>]*> 418d7016 mttr t5,t6,0,6,1
0+0978 <[^>]*> 418d7017 mttr t5,t6,0,7,1
0+097c <[^>]*> 418d7020 mttgpr t5,t6
0+0980 <[^>]*> 418d7021 mttacx t5,\$ac3
0+0984 <[^>]*> 418d7022 mttc1 t5,\$f14
0+0988 <[^>]*> 418d7023 cttc1 t5,\$14
0+098c <[^>]*> 418d7024 mttc2 t5,\$14
0+0990 <[^>]*> 418d7025 cttc2 t5,\$14
0+0994 <[^>]*> 418d7026 mttr t5,t6,1,6,0
0+0998 <[^>]*> 418d7027 mttr t5,t6,1,7,0
0+099c <[^>]*> 418d7030 mttr t5,t6,1,0,1
0+09a0 <[^>]*> 418d7031 mttr t5,t6,1,1,1
0+09a4 <[^>]*> 418d7032 mtthc1 t5,\$f14
0+09a8 <[^>]*> 418d7033 mttr t5,t6,1,3,1
0+09ac <[^>]*> 418d7034 mtthc2 t5,\$14
0+09b0 <[^>]*> 418d7035 mttr t5,t6,1,5,1
0+09b4 <[^>]*> 418d7036 mttr t5,t6,1,6,1
0+09b8 <[^>]*> 418d7037 mttr t5,t6,1,7,1
\.\.\.

257
gas/testsuite/gas/mips/mips32-mt.l
View File

@ -1,257 +0,0 @@
.*: Assembler messages:
.*:568: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:568: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:569: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:569: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:570: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:570: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:571: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:571: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:572: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:572: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:573: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:573: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:574: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:574: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:575: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:575: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:576: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:577: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:578: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:579: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:580: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:581: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:582: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:583: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:584: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:585: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:586: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:587: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:588: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:589: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:590: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:591: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:592: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:592: Warning: MT immediate not in range 0..1 \(2\)
.*:593: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:593: Warning: MT immediate not in range 0..1 \(2\)
.*:594: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:594: Warning: MT immediate not in range 0..1 \(2\)
.*:595: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:595: Warning: MT immediate not in range 0..1 \(2\)
.*:596: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:596: Warning: MT immediate not in range 0..1 \(2\)
.*:597: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:597: Warning: MT immediate not in range 0..1 \(2\)
.*:598: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:598: Warning: MT immediate not in range 0..1 \(2\)
.*:599: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:599: Warning: MT immediate not in range 0..1 \(2\)
.*:600: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:601: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:602: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:603: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:604: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:605: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:606: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:607: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:624: Warning: MT immediate not in range 0..1 \(2\)
.*:625: Warning: MT immediate not in range 0..1 \(2\)
.*:626: Warning: MT immediate not in range 0..1 \(2\)
.*:627: Warning: MT immediate not in range 0..1 \(2\)
.*:628: Warning: MT immediate not in range 0..1 \(2\)
.*:629: Warning: MT immediate not in range 0..1 \(2\)
.*:630: Warning: MT immediate not in range 0..1 \(2\)
.*:631: Warning: MT immediate not in range 0..1 \(2\)
.*:632: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:633: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:634: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:635: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:636: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:637: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:638: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:639: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:656: Warning: MT immediate not in range 0..1 \(2\)
.*:657: Warning: MT immediate not in range 0..1 \(2\)
.*:658: Warning: MT immediate not in range 0..1 \(2\)
.*:659: Warning: MT immediate not in range 0..1 \(2\)
.*:660: Warning: MT immediate not in range 0..1 \(2\)
.*:661: Warning: MT immediate not in range 0..1 \(2\)
.*:662: Warning: MT immediate not in range 0..1 \(2\)
.*:663: Warning: MT immediate not in range 0..1 \(2\)
.*:664: Warning: MT immediate not in range 0..1 \(2\)
.*:664: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:665: Warning: MT immediate not in range 0..1 \(2\)
.*:665: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:666: Warning: MT immediate not in range 0..1 \(2\)
.*:666: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:667: Warning: MT immediate not in range 0..1 \(2\)
.*:667: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:668: Warning: MT immediate not in range 0..1 \(2\)
.*:668: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:669: Warning: MT immediate not in range 0..1 \(2\)
.*:669: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:670: Warning: MT immediate not in range 0..1 \(2\)
.*:670: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:671: Warning: MT immediate not in range 0..1 \(2\)
.*:671: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:672: Warning: MT immediate not in range 0..1 \(2\)
.*:673: Warning: MT immediate not in range 0..1 \(2\)
.*:674: Warning: MT immediate not in range 0..1 \(2\)
.*:675: Warning: MT immediate not in range 0..1 \(2\)
.*:676: Warning: MT immediate not in range 0..1 \(2\)
.*:677: Warning: MT immediate not in range 0..1 \(2\)
.*:678: Warning: MT immediate not in range 0..1 \(2\)
.*:679: Warning: MT immediate not in range 0..1 \(2\)
.*:680: Warning: MT immediate not in range 0..1 \(2\)
.*:681: Warning: MT immediate not in range 0..1 \(2\)
.*:682: Warning: MT immediate not in range 0..1 \(2\)
.*:683: Warning: MT immediate not in range 0..1 \(2\)
.*:684: Warning: MT immediate not in range 0..1 \(2\)
.*:685: Warning: MT immediate not in range 0..1 \(2\)
.*:686: Warning: MT immediate not in range 0..1 \(2\)
.*:687: Warning: MT immediate not in range 0..1 \(2\)
.*:688: Warning: MT immediate not in range 0..1 \(2\)
.*:688: Warning: MT immediate not in range 0..1 \(2\)
.*:689: Warning: MT immediate not in range 0..1 \(2\)
.*:689: Warning: MT immediate not in range 0..1 \(2\)
.*:690: Warning: MT immediate not in range 0..1 \(2\)
.*:690: Warning: MT immediate not in range 0..1 \(2\)
.*:691: Warning: MT immediate not in range 0..1 \(2\)
.*:691: Warning: MT immediate not in range 0..1 \(2\)
.*:692: Warning: MT immediate not in range 0..1 \(2\)
.*:692: Warning: MT immediate not in range 0..1 \(2\)
.*:693: Warning: MT immediate not in range 0..1 \(2\)
.*:693: Warning: MT immediate not in range 0..1 \(2\)
.*:694: Warning: MT immediate not in range 0..1 \(2\)
.*:694: Warning: MT immediate not in range 0..1 \(2\)
.*:695: Warning: MT immediate not in range 0..1 \(2\)
.*:695: Warning: MT immediate not in range 0..1 \(2\)
.*:696: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:696: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:697: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:697: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:698: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:698: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:699: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:699: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:700: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:700: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:701: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:701: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:702: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:702: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:703: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:703: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:704: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:705: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:706: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:707: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:708: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:709: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:710: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:711: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:712: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:713: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:714: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:715: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:716: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:717: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:718: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:719: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:720: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:720: Warning: MT immediate not in range 0..1 \(2\)
.*:721: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:721: Warning: MT immediate not in range 0..1 \(2\)
.*:722: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:722: Warning: MT immediate not in range 0..1 \(2\)
.*:723: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:723: Warning: MT immediate not in range 0..1 \(2\)
.*:724: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:724: Warning: MT immediate not in range 0..1 \(2\)
.*:725: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:725: Warning: MT immediate not in range 0..1 \(2\)
.*:726: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:726: Warning: MT immediate not in range 0..1 \(2\)
.*:727: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:727: Warning: MT immediate not in range 0..1 \(2\)
.*:728: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:729: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:730: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:731: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:732: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:733: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:734: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:735: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:752: Warning: MT immediate not in range 0..1 \(2\)
.*:753: Warning: MT immediate not in range 0..1 \(2\)
.*:754: Warning: MT immediate not in range 0..1 \(2\)
.*:755: Warning: MT immediate not in range 0..1 \(2\)
.*:756: Warning: MT immediate not in range 0..1 \(2\)
.*:757: Warning: MT immediate not in range 0..1 \(2\)
.*:758: Warning: MT immediate not in range 0..1 \(2\)
.*:759: Warning: MT immediate not in range 0..1 \(2\)
.*:760: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:761: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:762: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:763: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:764: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:765: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:766: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:767: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:784: Warning: MT immediate not in range 0..1 \(2\)
.*:785: Warning: MT immediate not in range 0..1 \(2\)
.*:786: Warning: MT immediate not in range 0..1 \(2\)
.*:787: Warning: MT immediate not in range 0..1 \(2\)
.*:788: Warning: MT immediate not in range 0..1 \(2\)
.*:789: Warning: MT immediate not in range 0..1 \(2\)
.*:790: Warning: MT immediate not in range 0..1 \(2\)
.*:791: Warning: MT immediate not in range 0..1 \(2\)
.*:792: Warning: MT immediate not in range 0..1 \(2\)
.*:792: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:793: Warning: MT immediate not in range 0..1 \(2\)
.*:793: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:794: Warning: MT immediate not in range 0..1 \(2\)
.*:794: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:795: Warning: MT immediate not in range 0..1 \(2\)
.*:795: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:796: Warning: MT immediate not in range 0..1 \(2\)
.*:796: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:797: Warning: MT immediate not in range 0..1 \(2\)
.*:797: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:798: Warning: MT immediate not in range 0..1 \(2\)
.*:798: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:799: Warning: MT immediate not in range 0..1 \(2\)
.*:799: Warning: MT immediate not in range 0..1 \([0-9]*\)
.*:800: Warning: MT immediate not in range 0..1 \(2\)
.*:801: Warning: MT immediate not in range 0..1 \(2\)
.*:802: Warning: MT immediate not in range 0..1 \(2\)
.*:803: Warning: MT immediate not in range 0..1 \(2\)
.*:804: Warning: MT immediate not in range 0..1 \(2\)
.*:805: Warning: MT immediate not in range 0..1 \(2\)
.*:806: Warning: MT immediate not in range 0..1 \(2\)
.*:807: Warning: MT immediate not in range 0..1 \(2\)
.*:808: Warning: MT immediate not in range 0..1 \(2\)
.*:809: Warning: MT immediate not in range 0..1 \(2\)
.*:810: Warning: MT immediate not in range 0..1 \(2\)
.*:811: Warning: MT immediate not in range 0..1 \(2\)
.*:812: Warning: MT immediate not in range 0..1 \(2\)
.*:813: Warning: MT immediate not in range 0..1 \(2\)
.*:814: Warning: MT immediate not in range 0..1 \(2\)
.*:815: Warning: MT immediate not in range 0..1 \(2\)
.*:816: Warning: MT immediate not in range 0..1 \(2\)
.*:816: Warning: MT immediate not in range 0..1 \(2\)
.*:817: Warning: MT immediate not in range 0..1 \(2\)
.*:817: Warning: MT immediate not in range 0..1 \(2\)
.*:818: Warning: MT immediate not in range 0..1 \(2\)
.*:818: Warning: MT immediate not in range 0..1 \(2\)
.*:819: Warning: MT immediate not in range 0..1 \(2\)
.*:819: Warning: MT immediate not in range 0..1 \(2\)
.*:820: Warning: MT immediate not in range 0..1 \(2\)
.*:820: Warning: MT immediate not in range 0..1 \(2\)
.*:821: Warning: MT immediate not in range 0..1 \(2\)
.*:821: Warning: MT immediate not in range 0..1 \(2\)
.*:822: Warning: MT immediate not in range 0..1 \(2\)
.*:822: Warning: MT immediate not in range 0..1 \(2\)
.*:823: Warning: MT immediate not in range 0..1 \(2\)
.*:823: Warning: MT immediate not in range 0..1 \(2\)

192
gas/testsuite/gas/mips/mips32-mt.s
View File

@ -565,46 +565,6 @@ text_label:
mttc2 $10,$11
mtthc2 $11,$12
cttc2 $12,$13
mftr $13,$14,-1,0,-1
mftr $13,$14,-1,1,-1
mftr $13,$14,-1,2,-1
mftr $13,$14,-1,3,-1
mftr $13,$14,-1,4,-1
mftr $13,$14,-1,5,-1
mftr $13,$14,-1,6,-1
mftr $13,$14,-1,7,-1
mftr $13,$14,-1,0,0
mftr $13,$14,-1,1,0
mftr $13,$14,-1,2,0
mftr $13,$14,-1,3,0
mftr $13,$14,-1,4,0
mftr $13,$14,-1,5,0
mftr $13,$14,-1,6,0
mftr $13,$14,-1,7,0
mftr $13,$14,-1,0,1
mftr $13,$14,-1,1,1
mftr $13,$14,-1,2,1
mftr $13,$14,-1,3,1
mftr $13,$14,-1,4,1
mftr $13,$14,-1,5,1
mftr $13,$14,-1,6,1
mftr $13,$14,-1,7,1
mftr $13,$14,-1,0,2
mftr $13,$14,-1,1,2
mftr $13,$14,-1,2,2
mftr $13,$14,-1,3,2
mftr $13,$14,-1,4,2
mftr $13,$14,-1,5,2
mftr $13,$14,-1,6,2
mftr $13,$14,-1,7,2
mftr $13,$14,0,0,-1
mftr $13,$14,0,1,-1
mftr $13,$14,0,2,-1
mftr $13,$14,0,3,-1
mftr $13,$14,0,4,-1
mftr $13,$14,0,5,-1
mftr $13,$14,0,6,-1
mftr $13,$14,0,7,-1
mftr $13,$14,0,0,0
mftr $13,$14,0,1,0
mftr $13,$14,0,2,0
@ -621,22 +581,6 @@ text_label:
mftr $13,$14,0,5,1
mftr $13,$14,0,6,1
mftr $13,$14,0,7,1
mftr $13,$14,0,0,2
mftr $13,$14,0,1,2
mftr $13,$14,0,2,2
mftr $13,$14,0,3,2
mftr $13,$14,0,4,2
mftr $13,$14,0,5,2
mftr $13,$14,0,6,2
mftr $13,$14,0,7,2
mftr $13,$14,1,0,-1
mftr $13,$14,1,1,-1
mftr $13,$14,1,2,-1
mftr $13,$14,1,3,-1
mftr $13,$14,1,4,-1
mftr $13,$14,1,5,-1
mftr $13,$14,1,6,-1
mftr $13,$14,1,7,-1
mftr $13,$14,1,0,0
mftr $13,$14,1,1,0
mftr $13,$14,1,2,0
@ -653,86 +597,6 @@ text_label:
mftr $13,$14,1,5,1
mftr $13,$14,1,6,1
mftr $13,$14,1,7,1
mftr $13,$14,1,0,2
mftr $13,$14,1,1,2
mftr $13,$14,1,2,2
mftr $13,$14,1,3,2
mftr $13,$14,1,4,2
mftr $13,$14,1,5,2
mftr $13,$14,1,6,2
mftr $13,$14,1,7,2
mftr $13,$14,2,0,-1
mftr $13,$14,2,1,-1
mftr $13,$14,2,2,-1
mftr $13,$14,2,3,-1
mftr $13,$14,2,4,-1
mftr $13,$14,2,5,-1
mftr $13,$14,2,6,-1
mftr $13,$14,2,7,-1
mftr $13,$14,2,0,0
mftr $13,$14,2,1,0
mftr $13,$14,2,2,0
mftr $13,$14,2,3,0
mftr $13,$14,2,4,0
mftr $13,$14,2,5,0
mftr $13,$14,2,6,0
mftr $13,$14,2,7,0
mftr $13,$14,2,0,1
mftr $13,$14,2,1,1
mftr $13,$14,2,2,1
mftr $13,$14,2,3,1
mftr $13,$14,2,4,1
mftr $13,$14,2,5,1
mftr $13,$14,2,6,1
mftr $13,$14,2,7,1
mftr $13,$14,2,0,2
mftr $13,$14,2,1,2
mftr $13,$14,2,2,2
mftr $13,$14,2,3,2
mftr $13,$14,2,4,2
mftr $13,$14,2,5,2
mftr $13,$14,2,6,2
mftr $13,$14,2,7,2
mttr $13,$14,-1,0,-1
mttr $13,$14,-1,1,-1
mttr $13,$14,-1,2,-1
mttr $13,$14,-1,3,-1
mttr $13,$14,-1,4,-1
mttr $13,$14,-1,5,-1
mttr $13,$14,-1,6,-1
mttr $13,$14,-1,7,-1
mttr $13,$14,-1,0,0
mttr $13,$14,-1,1,0
mttr $13,$14,-1,2,0
mttr $13,$14,-1,3,0
mttr $13,$14,-1,4,0
mttr $13,$14,-1,5,0
mttr $13,$14,-1,6,0
mttr $13,$14,-1,7,0
mttr $13,$14,-1,0,1
mttr $13,$14,-1,1,1
mttr $13,$14,-1,2,1
mttr $13,$14,-1,3,1
mttr $13,$14,-1,4,1
mttr $13,$14,-1,5,1
mttr $13,$14,-1,6,1
mttr $13,$14,-1,7,1
mttr $13,$14,-1,0,2
mttr $13,$14,-1,1,2
mttr $13,$14,-1,2,2
mttr $13,$14,-1,3,2
mttr $13,$14,-1,4,2
mttr $13,$14,-1,5,2
mttr $13,$14,-1,6,2
mttr $13,$14,-1,7,2
mttr $13,$14,0,0,-1
mttr $13,$14,0,1,-1
mttr $13,$14,0,2,-1
mttr $13,$14,0,3,-1
mttr $13,$14,0,4,-1
mttr $13,$14,0,5,-1
mttr $13,$14,0,6,-1
mttr $13,$14,0,7,-1
mttr $13,$14,0,0,0
mttr $13,$14,0,1,0
mttr $13,$14,0,2,0
@ -749,22 +613,6 @@ text_label:
mttr $13,$14,0,5,1
mttr $13,$14,0,6,1
mttr $13,$14,0,7,1
mttr $13,$14,0,0,2
mttr $13,$14,0,1,2
mttr $13,$14,0,2,2
mttr $13,$14,0,3,2
mttr $13,$14,0,4,2
mttr $13,$14,0,5,2
mttr $13,$14,0,6,2
mttr $13,$14,0,7,2
mttr $13,$14,1,0,-1
mttr $13,$14,1,1,-1
mttr $13,$14,1,2,-1
mttr $13,$14,1,3,-1
mttr $13,$14,1,4,-1
mttr $13,$14,1,5,-1
mttr $13,$14,1,6,-1
mttr $13,$14,1,7,-1
mttr $13,$14,1,0,0
mttr $13,$14,1,1,0
mttr $13,$14,1,2,0
@ -781,46 +629,6 @@ text_label:
mttr $13,$14,1,5,1
mttr $13,$14,1,6,1
mttr $13,$14,1,7,1
mttr $13,$14,1,0,2
mttr $13,$14,1,1,2
mttr $13,$14,1,2,2
mttr $13,$14,1,3,2
mttr $13,$14,1,4,2
mttr $13,$14,1,5,2
mttr $13,$14,1,6,2
mttr $13,$14,1,7,2
mttr $13,$14,2,0,-1
mttr $13,$14,2,1,-1
mttr $13,$14,2,2,-1
mttr $13,$14,2,3,-1
mttr $13,$14,2,4,-1
mttr $13,$14,2,5,-1
mttr $13,$14,2,6,-1
mttr $13,$14,2,7,-1
mttr $13,$14,2,0,0
mttr $13,$14,2,1,0
mttr $13,$14,2,2,0
mttr $13,$14,2,3,0
mttr $13,$14,2,4,0
mttr $13,$14,2,5,0
mttr $13,$14,2,6,0
mttr $13,$14,2,7,0
mttr $13,$14,2,0,1
mttr $13,$14,2,1,1
mttr $13,$14,2,2,1
mttr $13,$14,2,3,1
mttr $13,$14,2,4,1
mttr $13,$14,2,5,1
mttr $13,$14,2,6,1
mttr $13,$14,2,7,1
mttr $13,$14,2,0,2
mttr $13,$14,2,1,2
mttr $13,$14,2,2,2
mttr $13,$14,2,3,2
mttr $13,$14,2,4,2
mttr $13,$14,2,5,2
mttr $13,$14,2,6,2
mttr $13,$14,2,7,2
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8

4
include/opcode/ChangeLog
View File

@ -1,3 +1,7 @@
2006-06-05 Thiemo Seufer <ths@mips.com>
* mips.h: Improve description of MT flags.
2006-05-25 Richard Sandiford <richard@codesourcery.com>
* m68k.h (mcf_mask): Define.

4
include/opcode/mips.h
View File

@ -353,8 +353,8 @@ struct mips_opcode
"@" 10 bit signed immediate (OP_*_IMM10)
MT ASE usage:
"!" 1 bit immediate at bit 5
"$" 1 bit immediate at bit 4
"!" 1 bit usermode flag (OP_*_MT_U)
"$" 1 bit load high flag (OP_*_MT_H)
"*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
"&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
"g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)