From aa49c64f3e93a777b3938daac491bbc983f93cf4 Mon Sep 17 00:00:00 2001 From: Andrew Cagney Date: Wed, 3 Dec 1997 08:03:33 +0000 Subject: [PATCH] * d10v_sim.h (SEXT56): Define. * simops.c (OP_4201): For "rac", sign extend 56 bit value before it is shifted. * d10v_sim.h (MAX32, MIN32, MASK32, MASK40): Re-define using SIGNED64 macro. --- sim/d10v/ChangeLog | 10 +++ sim/d10v/d10v_sim.h | 76 +++++++---------- sim/d10v/simops.c | 16 ++-- sim/testsuite/d10v-elf/.Sanitize | 1 + sim/testsuite/d10v-elf/ChangeLog | 11 ++- sim/testsuite/d10v-elf/Makefile.in | 2 + sim/testsuite/d10v-elf/t-macros.i | 127 +++++++++++++++++++++++++++++ sim/testsuite/d10v-elf/t-rac.s | 16 ++++ sim/testsuite/d10v-elf/t-rep.s | 26 ++++++ 9 files changed, 230 insertions(+), 55 deletions(-) create mode 100644 sim/testsuite/d10v-elf/t-macros.i create mode 100644 sim/testsuite/d10v-elf/t-rac.s create mode 100644 sim/testsuite/d10v-elf/t-rep.s diff --git a/sim/d10v/ChangeLog b/sim/d10v/ChangeLog index 8612dbdddd..68bca21540 100644 --- a/sim/d10v/ChangeLog +++ b/sim/d10v/ChangeLog @@ -1,3 +1,13 @@ +Wed Dec 3 17:27:06 1997 Andrew Cagney + + * d10v_sim.h (SEXT56): Define. + + * simops.c (OP_4201): For "rac", sign extend 56 bit value before + it is shifted. + + * d10v_sim.h (MAX32, MIN32, MASK32, MASK40): Re-define using + SIGNED64 macro. + Tue Dec 2 15:38:34 1997 Fred Fish * interp.c (sim_resume): Call do_2_short with LEFT_FIRST or diff --git a/sim/d10v/d10v_sim.h b/sim/d10v/d10v_sim.h index 49b3edcfff..2f9e72b39c 100644 --- a/sim/d10v/d10v_sim.h +++ b/sim/d10v/d10v_sim.h @@ -1,3 +1,4 @@ +#include "config.h" #include #include #include @@ -18,43 +19,14 @@ extern int d10v_debug; -#if UCHAR_MAX == 255 -typedef unsigned char uint8; -typedef signed char int8; -#else -#error "Char is not an 8-bit type" -#endif - -#if SHRT_MAX == 32767 -typedef unsigned short uint16; -typedef signed short int16; -#else -#error "Short is not a 16-bit type" -#endif - -#if INT_MAX == 2147483647 -typedef unsigned int uint32; -typedef signed int int32; - -#elif LONG_MAX == 2147483647 -typedef unsigned long uint32; -typedef signed long int32; - -#else -#error "Neither int nor long is a 32-bit type" -#endif - -#if LONG_MAX > 2147483647 -typedef unsigned long uint64; -typedef signed long int64; - -#elif __GNUC__ -typedef unsigned long long uint64; -typedef signed long long int64; - -#else -#error "Can't find an appropriate 64-bit type" -#endif +#include "sim-types.h" +typedef unsigned8 uint8; +typedef unsigned16 uint16; +typedef signed16 int16; +typedef unsigned32 uint32; +typedef signed32 int32; +typedef unsigned64 uint64; +typedef signed64 int64; /* FIXME: D10V defines */ typedef uint16 reg_t; @@ -62,6 +34,7 @@ typedef uint16 reg_t; struct simops { long opcode; + int is_long; long mask; int format; int cycles; @@ -118,7 +91,8 @@ struct _state uint8 F1; uint8 C; uint8 exe; - int exception; + int exception; + int pc_changed; /* everything below this line is not reset by sim_create_inferior() */ uint8 *imem; uint8 *dmem; @@ -132,7 +106,7 @@ extern struct simops Simops[]; extern asection *text; extern bfd_vma text_start; extern bfd_vma text_end; -extern bfd *exec_bfd; +extern bfd *prog_bfd; #define PC (State.cregs[2]) #define PSW (State.cregs[0]) @@ -160,23 +134,27 @@ extern bfd *exec_bfd; #define SEXT16(x) ((((x)&0xffff)^(~0x7fff))+0x8000) /* sign-extend a 32-bit number */ -#define SEXT32(x) ((((x)&0xffffffffLL)^(~0x7fffffffLL))+0x80000000LL) +#define SEXT32(x) ((((x)&SIGNED64(0xffffffff))^(~SIGNED64(0x7fffffff)))+SIGNED64(0x80000000)) /* sign extend a 40 bit number */ -#define SEXT40(x) ((((x)&0xffffffffffLL)^(~0x7fffffffffLL))+0x8000000000LL) +#define SEXT40(x) ((((x)&SIGNED64(0xffffffffff))^(~SIGNED64(0x7fffffffff)))+SIGNED64(0x8000000000)) /* sign extend a 44 bit number */ -#define SEXT44(x) ((((x)&0xfffffffffffLL)^(~0x7ffffffffffLL))+0x80000000000LL) +#define SEXT44(x) ((((x)&SIGNED64(0xfffffffffff))^(~SIGNED64(0x7ffffffffff)))+SIGNED64(0x80000000000)) + +/* sign extend a 56 bit number */ +#define SEXT56(x) ((((x)&SIGNED64(0xffffffffffffff))^(~SIGNED64(0x7fffffffffffff)))+SIGNED64(0x80000000000000)) /* sign extend a 60 bit number */ -#define SEXT60(x) ((((x)&0xfffffffffffffffLL)^(~0x7ffffffffffffffLL))+0x800000000000000LL) +#define SEXT60(x) ((((x)&SIGNED64(0xfffffffffffffff))^(~SIGNED64(0x7ffffffffffffff)))+SIGNED64(0x800000000000000)) -#define MAX32 0x7fffffffLL -#define MIN32 0xff80000000LL -#define MASK32 0xffffffffLL -#define MASK40 0xffffffffffLL +#define MAX32 SIGNED64(0x7fffffff) +#define MIN32 SIGNED64(0xff80000000) +#define MASK32 SIGNED64(0xffffffff) +#define MASK40 SIGNED64(0xffffffffff) -#define INC_ADDR(x,i) x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i)) +/* The alignment of MOD_E in the following macro depends upon "i" always being a power of 2. */ +#define INC_ADDR(x,i) x = ((State.MD && x == (MOD_E & ~((i)-1))) ? MOD_S : (x)+(i)) extern uint8 *dmem_addr PARAMS ((uint32)); extern bfd_vma decode_pc PARAMS ((void)); @@ -213,3 +191,5 @@ extern void write_longlong PARAMS ((uint8 *addr, int64 data)); #define SET_IMAP0(x) SW(0xff00,x) #define SET_IMAP1(x) SW(0xff02,x) #define SET_DMAP(x) SW(0xff04,x) + +#define JMP(x) { PC = (x); State.pc_changed = 1; } diff --git a/sim/d10v/simops.c b/sim/d10v/simops.c index 64c8a33f1e..723a7d9fb9 100644 --- a/sim/d10v/simops.c +++ b/sim/d10v/simops.c @@ -1912,18 +1912,20 @@ OP_5201 () } State.F1 = State.F0; + tmp = SEXT56 ((State.a[0] << 16) | (State.a[1] & 0xffff)); if (shift >=0) - tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) << shift; + tmp <<= shift; else - tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) >> -shift; - tmp = ( SEXT60(tmp) + 0x8000 ) >> 16; - if (tmp > MAX32) + tmp >>= -shift; + tmp += 0x8000; + tmp >>= 16; /* look at bits 0:43 */ + if (tmp > SEXT44 (SIGNED64 (0x0007fffffff))) { State.regs[OP[0]] = 0x7fff; State.regs[OP[0]+1] = 0xffff; State.F0 = 1; } - else if (tmp < MIN32) + else if (tmp < SEXT44 (SIGNED64 (0xfff80000000))) { State.regs[OP[0]] = 0x8000; State.regs[OP[0]+1] = 0; @@ -2429,8 +2431,10 @@ OP_0 () uint16 tmp; trace_input ("sub", OP_REG, OP_REG, OP_VOID); + /* see ../common/sim-alu.h for a more extensive discussion on how to + compute the carry/overflow bits. */ tmp = State.regs[OP[0]] - State.regs[OP[1]]; - State.C = (tmp > State.regs[OP[0]]); + State.C = ((uint16) State.regs[OP[0]] >= (uint16) State.regs[OP[1]]); State.regs[OP[0]] = tmp; trace_output (OP_REG); } diff --git a/sim/testsuite/d10v-elf/.Sanitize b/sim/testsuite/d10v-elf/.Sanitize index 2f3a8d8d16..6c46ef12ce 100644 --- a/sim/testsuite/d10v-elf/.Sanitize +++ b/sim/testsuite/d10v-elf/.Sanitize @@ -12,6 +12,7 @@ loop.s t-macros.i t-mac.s t-msbu.s +t-rac.s t-rachi.s t-rep.s t-mulxu.s diff --git a/sim/testsuite/d10v-elf/ChangeLog b/sim/testsuite/d10v-elf/ChangeLog index a6f0854420..29be1fb014 100644 --- a/sim/testsuite/d10v-elf/ChangeLog +++ b/sim/testsuite/d10v-elf/ChangeLog @@ -1,6 +1,15 @@ +Wed Dec 3 16:35:24 1997 Andrew Cagney + + * t-rac.s: New files. + + * t-macros.i: Add macros for checking psw and 2w quantities. + + * Makefile.in (TESTS): Update. + Tue Dec 2 11:01:36 1997 Andrew Cagney - * t-sub2w.s, t-mulxu.s, t-mac.s, t-mvtac.s, t-msbu.s: New files. + * t-sub2w.s, t-mulxu.s, t-mac.s, t-mvtac.s, t-msbu.s, t-sub.s: New + files. * Makefile.in: Update. diff --git a/sim/testsuite/d10v-elf/Makefile.in b/sim/testsuite/d10v-elf/Makefile.in index c89ffb2d84..df43e19234 100644 --- a/sim/testsuite/d10v-elf/Makefile.in +++ b/sim/testsuite/d10v-elf/Makefile.in @@ -44,9 +44,11 @@ TESTS = \ t-mvtac.ok \ t-msbu.ok \ t-mulxu.ok \ + t-rac.ok \ t-rachi.ok \ t-rep.ok \ t-sub2w.ok \ + t-sub.ok \ t-subi.ok \ # diff --git a/sim/testsuite/d10v-elf/t-macros.i b/sim/testsuite/d10v-elf/t-macros.i new file mode 100644 index 0000000000..83029b5a0a --- /dev/null +++ b/sim/testsuite/d10v-elf/t-macros.i @@ -0,0 +1,127 @@ + .macro start + .text + .align 2 + .globl _start +_start: + .endm + + + .macro exit47 + ldi r6, 1 + ldi r2, 47 + trap 15 + .endm + + + .macro exit0 + ldi r6, 1 + ldi r2, 0 + trap 15 + .endm + + + .macro load reg val + ldi \reg, #\val + .endm + + + .macro load2w reg hi lo + ld2w \reg, @(1f,r0) + .data + .align 2 +1: .short \hi + .short \lo + .text + .endm + + + .macro check exit reg val + cmpeqi \reg, #\val + brf0t 1f +0: ldi r6, 1 + ldi r2, \exit + trap 15 +1: + .endm + + + .macro check2w2 exit reg hi lo + st2w \reg, @(1f,r0) + ld r2, @(1f, r0) + cmpeqi r2, #\hi + brf0f 0f + ld r2, @(1f + 2, r0) + cmpeqi r2, #\lo + brf0f 0f + bra 2f +0: ldi r6, 1 + ldi r2, \exit + trap 15 + .data + .align 2 +1: .long 0 + .text +2: + .endm + + + .macro loadacc2 acc guard hi lo + ldi r2, #\lo + mvtaclo r2, \acc + ldi r2, #\hi + mvtachi r2, \acc + ldi r2, #\guard + mvtacg r2, \acc + .endm + + + .macro checkacc2 exit acc guard hi lo + ldi r2, #\guard + mvfacg r3, \acc + cmpeq r2, r3 + brf0f 0f + ldi r2, #\hi + mvfachi r3, \acc + cmpeq r2, r3 + brf0f 0f + ldi r2, #\lo + mvfaclo r3, \acc + cmpeq r2, r3 + brf0f 0f + bra 4f +0: ldi r6, 1 + ldi r2, \exit + trap 15 +4: + .endm + + + .macro loadpsw2 val + ldi r2, #\val + mvtc r2, cr0 + .endm + + + .macro checkpsw2 exit val + mvfc r2, cr0 + cmpeqi r2, #\val + brf0t 1f + ldi r6, 1 + ldi r2, \exit + trap 15 +1: + .endm + + + .macro hello + ;; 4:write (1, string, strlen (string)) + ldi r6, 4 + ldi r2, 1 + ldi r3, 1f + ldi r4, 2f-1f-1 + trap 15 + .section .rodata +1: .string "Hello World!\n" +2: .align 2 + .text + .endm diff --git a/sim/testsuite/d10v-elf/t-rac.s b/sim/testsuite/d10v-elf/t-rac.s new file mode 100644 index 0000000000..f2123116c6 --- /dev/null +++ b/sim/testsuite/d10v-elf/t-rac.s @@ -0,0 +1,16 @@ +.include "t-macros.i" + + start + + ;; clear FX + loadpsw2 0x8004 + loadacc2 a0 0x80 0x0000 0x0000 + loadacc2 a1 0x00 0x0000 0x5000 + load r10 0x0123 + load r11 0x4567 +test_rac1: + RAC r10, a0, #-2 + checkpsw2 1 0x8008 + check2w2 2 r10 0x8000 0x0000 + + exit0 diff --git a/sim/testsuite/d10v-elf/t-rep.s b/sim/testsuite/d10v-elf/t-rep.s new file mode 100644 index 0000000000..b539bd2766 --- /dev/null +++ b/sim/testsuite/d10v-elf/t-rep.s @@ -0,0 +1,26 @@ +.include "t-macros.i" + + start + + + + # Check that the instruction @REP_E is executed when it + # is reached using a branch instruction + + ldi r2, 1 +test_rep_1: + rep r2, end_rep_1 + nop || nop + nop || nop + nop || nop + nop || nop + ldi r3, 46 + bra end_rep_1 + ldi r3, 42 +end_rep_1: + addi r3, 1 + + check 1 r3 47 + + + exit0