* cgen-opc.in: New file.
* cgen.sh: Translate @ARCH@. Cat cgen-opc.in into @arch@-opc.c. * Makefile.am (CGENFILES): Add cgen-opc.in. * Makefile.in: Regenerate. * cgen-opc.c (cgen_set_cpu): Delete init of hw list `next' chain. (cgen_hw_lookup): Make result const. * cgen-dis.in (*): Use PTR instead of void *. (print_insn): Delete unused vars `i', `syntax'. * m32r-opc.h, m32r-opc.c, m32r-asm.c, m32r-dis.c: Regenerate.
This commit is contained in:
Doug Evans
parent
e0bd6e186c
commit
ab0bd0493a
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@ -15,7 +15,7 @@
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Do-first:
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cygnus_files="cgen.sh cgen-asm.in cgen-dis.in"
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cygnus_files="cgen.sh cgen-asm.in cgen-dis.in cgen-opc.in"
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if ( echo $* | grep keep\-cygnus > /dev/null ) ; then
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keep_these_too="${cygnus_files} ${keep_these_too}"
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@ -1,7 +1,23 @@
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Wed Feb 11 18:58:34 1998 Doug Evans <devans@seba.cygnus.com>
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* cgen-opc.in: New file.
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* cgen.sh: Translate @ARCH@. Cat cgen-opc.in into @arch@-opc.c.
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* Makefile.am (CGENFILES): Add cgen-opc.in.
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* Makefile.in: Regenerate.
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* cgen-opc.c (cgen_set_cpu): Delete init of hw list `next' chain.
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(cgen_hw_lookup): Make result const.
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* cgen-dis.in (*): Use PTR instead of void *.
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(print_insn): Delete unused vars `i', `syntax'.
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* m32r-opc.h, m32r-opc.c, m32r-asm.c, m32r-dis.c: Regenerate.
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start-sanitize-sky
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Tue Feb 10 14:56:24 1998 Doug Evans <devans@canuck.cygnus.com>
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* dvp-opc.c (*): pke,gpuif renamed to vif,gif.
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(vif_opcodes): Update renamed insns.
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* dvp-dis.c (*): Likewise.
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end-sanitize-sky
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@ -55,6 +55,7 @@ CFILES = \
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sh-dis.c \
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sparc-dis.c \
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sparc-opc.c \
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tic30-dis.c \
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w65-dis.c \
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z8k-dis.c \
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z8kgen.c
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@ -99,6 +100,7 @@ ALL_MACHINES = \
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sh-dis.lo \
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sparc-dis.lo \
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sparc-opc.lo \
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tic30-dis.lo \
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$(start-sanitize-tic80) \
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tic80-dis.lo \
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tic80-opc.lo \
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@ -158,7 +160,7 @@ CGENFILES = $(CGENDIR)/object.scm $(CGENDIR)/utils.scm \
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$(CGENDIR)/ifield.scm $(CGENDIR)/iformat.scm \
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$(CGENDIR)/operand.scm $(CGENDIR)/insn.scm \
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$(CGENDIR)/opcodes.scm $(CGENDIR)/cgen-opc.scm \
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cgen-asm.in cgen-dis.in
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cgen-opc.in cgen-asm.in cgen-dis.in
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# The end marker is written this way to pass through automake unscathed.
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ENDSAN = end-sanitize-cygnus
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@ -243,7 +245,8 @@ alpha-dis.lo: alpha-dis.c $(INCDIR)/ansidecl.h sysdep.h \
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alpha-opc.lo: alpha-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/alpha.h \
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$(BFD_H)
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arm-dis.lo: arm-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
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$(INCDIR)/ansidecl.h arm-opc.h
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$(INCDIR)/ansidecl.h arm-opc.h $(INCDIR)/coff/internal.h \
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$(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
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cgen-asm.lo: cgen-asm.c sysdep.h config.h $(INCDIR)/libiberty.h \
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$(BFD_H) $(INCDIR)/opcode/cgen.h
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cgen-dis.lo: cgen-dis.c sysdep.h config.h $(INCDIR)/libiberty.h \
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@ -301,6 +304,8 @@ sparc-dis.lo: sparc-dis.c $(INCDIR)/ansidecl.h sysdep.h \
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config.h $(INCDIR)/opcode/sparc.h $(INCDIR)/dis-asm.h \
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$(BFD_H) $(INCDIR)/libiberty.h
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sparc-opc.lo: sparc-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/sparc.h
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tic30-dis.lo: tic30-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
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$(INCDIR)/ansidecl.h $(INCDIR)/opcode/tic30.h
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w65-dis.lo: w65-dis.c w65-opc.h $(INCDIR)/dis-asm.h \
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$(BFD_H) $(INCDIR)/ansidecl.h
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z8k-dis.lo: z8k-dis.c sysdep.h config.h $(INCDIR)/dis-asm.h \
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@ -65,6 +65,7 @@ LIBTOOL = @LIBTOOL@
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LN_S = @LN_S@
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MAINT = @MAINT@
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MAKEINFO = @MAKEINFO@
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NM = @NM@
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PACKAGE = @PACKAGE@
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RANLIB = @RANLIB@
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VERSION = @VERSION@
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@ -125,6 +126,7 @@ CFILES = \
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sh-dis.c \
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sparc-dis.c \
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sparc-opc.c \
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tic30-dis.c \
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w65-dis.c \
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z8k-dis.c \
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z8kgen.c
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@ -169,6 +171,7 @@ ALL_MACHINES = \
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sh-dis.lo \
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sparc-dis.lo \
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sparc-opc.lo \
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tic30-dis.lo \
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$(start-sanitize-tic80) \
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tic80-dis.lo \
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tic80-opc.lo \
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@ -218,7 +221,7 @@ CGENFILES = $(CGENDIR)/object.scm $(CGENDIR)/utils.scm \
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$(CGENDIR)/ifield.scm $(CGENDIR)/iformat.scm \
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$(CGENDIR)/operand.scm $(CGENDIR)/insn.scm \
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$(CGENDIR)/opcodes.scm $(CGENDIR)/cgen-opc.scm \
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cgen-asm.in cgen-dis.in
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cgen-opc.in cgen-asm.in cgen-dis.in
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# The end marker is written this way to pass through automake unscathed.
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ENDSAN = end-sanitize-cygnus
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ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
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@ -599,7 +602,8 @@ alpha-dis.lo: alpha-dis.c $(INCDIR)/ansidecl.h sysdep.h \
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alpha-opc.lo: alpha-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/alpha.h \
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$(BFD_H)
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arm-dis.lo: arm-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
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$(INCDIR)/ansidecl.h arm-opc.h
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$(INCDIR)/ansidecl.h arm-opc.h $(INCDIR)/coff/internal.h \
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$(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
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cgen-asm.lo: cgen-asm.c sysdep.h config.h $(INCDIR)/libiberty.h \
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$(BFD_H) $(INCDIR)/opcode/cgen.h
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cgen-dis.lo: cgen-dis.c sysdep.h config.h $(INCDIR)/libiberty.h \
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@ -657,6 +661,8 @@ sparc-dis.lo: sparc-dis.c $(INCDIR)/ansidecl.h sysdep.h \
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config.h $(INCDIR)/opcode/sparc.h $(INCDIR)/dis-asm.h \
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$(BFD_H) $(INCDIR)/libiberty.h
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sparc-opc.lo: sparc-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/sparc.h
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tic30-dis.lo: tic30-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
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$(INCDIR)/ansidecl.h $(INCDIR)/opcode/tic30.h
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w65-dis.lo: w65-dis.c w65-opc.h $(INCDIR)/dis-asm.h \
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$(BFD_H) $(INCDIR)/ansidecl.h
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z8k-dis.lo: z8k-dis.c sysdep.h config.h $(INCDIR)/dis-asm.h \
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@ -57,7 +57,7 @@ static void print_insn_normal
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static int
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extract_normal (buf_ctrl, insn_value, attrs, start, length, shift, total_length, valuep)
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void *buf_ctrl;
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PTR buf_ctrl;
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cgen_insn_t insn_value;
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unsigned int attrs;
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int start, length, shift, total_length;
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@ -94,7 +94,7 @@ extract_normal (buf_ctrl, insn_value, attrs, start, length, shift, total_length,
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static void
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print_normal (dis_info, value, attrs, pc, length)
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void *dis_info;
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PTR dis_info;
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long value;
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unsigned int attrs;
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unsigned long pc; /* FIXME: should be bfd_vma */
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@ -121,7 +121,7 @@ print_normal (dis_info, value, attrs, pc, length)
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static void
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print_keyword (dis_info, keyword_table, value, attrs)
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void *dis_info;
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PTR dis_info;
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CGEN_KEYWORD *keyword_table;
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long value;
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CGEN_ATTR *attrs;
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@ -147,7 +147,7 @@ print_keyword (dis_info, keyword_table, value, attrs)
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static int
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extract_insn_normal (insn, buf_ctrl, insn_value, fields)
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const CGEN_INSN *insn;
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void *buf_ctrl;
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PTR buf_ctrl;
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cgen_insn_t insn_value;
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CGEN_FIELDS *fields;
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{
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@ -177,13 +177,13 @@ extract_insn_normal (insn, buf_ctrl, insn_value, fields)
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/* Default insn printer.
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DIS_INFO is defined as `void *' so the disassembler needn't know anything
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DIS_INFO is defined as `PTR' so the disassembler needn't know anything
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about disassemble_info.
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*/
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static void
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print_insn_normal (dis_info, insn, fields, pc, length)
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void *dis_info;
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PTR dis_info;
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const CGEN_INSN *insn;
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CGEN_FIELDS *fields;
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bfd_vma pc;
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@ -215,7 +215,7 @@ print_insn_normal (dis_info, insn, fields, pc, length)
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}
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/* Default value for CGEN_PRINT_INSN.
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Given BUFLEN bytes (target byte order) read into BUF, look up the
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Given BUFLEN bits (target byte order) read into BUF, look up the
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insn in the instruction table and disassemble it.
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The result is the size of the insn in bytes. */
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@ -231,7 +231,6 @@ print_insn (pc, info, buf, buflen)
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char *buf;
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int buflen;
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{
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int i;
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unsigned long insn_value;
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const CGEN_INSN_LIST *insn_list;
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@ -257,7 +256,6 @@ print_insn (pc, info, buf, buflen)
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while (insn_list != NULL)
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{
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const CGEN_INSN *insn = insn_list->insn;
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const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
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CGEN_FIELDS fields;
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int length;
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@ -0,0 +1,143 @@
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/* Generic opcode table support for targets using CGEN. -*- C -*-
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CGEN: Cpu tools GENerator
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This file is used to generate @arch@-opc.c.
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Copyright (C) 1998 Free Software Foundation, Inc.
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This file is part of the GNU Binutils and GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
|
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it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
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any later version.
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|
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This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
|
||||
|
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#include "sysdep.h"
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#include <stdio.h>
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#include "ansidecl.h"
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#include "libiberty.h"
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#include "bfd.h"
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#include "symcat.h"
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#include "@arch@-opc.h"
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/* Look up instruction INSN_VALUE and extract its fields.
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If non-null INSN is the insn table entry.
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Otherwise INSN_VALUE is examined to compute it.
|
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LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
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The result a pointer to the insn table entry, or NULL if the instruction
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||||
wasn't recognized. */
|
||||
|
||||
const CGEN_INSN *
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@arch@_cgen_lookup_insn (insn, insn_value, length, fields)
|
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const CGEN_INSN *insn;
|
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cgen_insn_t insn_value;
|
||||
int length;
|
||||
CGEN_FIELDS *fields;
|
||||
{
|
||||
char buf[4];
|
||||
|
||||
if (!insn)
|
||||
{
|
||||
const CGEN_INSN_LIST *insn_list;
|
||||
|
||||
#ifdef CGEN_INT_INSN
|
||||
switch (length)
|
||||
{
|
||||
case 8:
|
||||
buf[0] = insn_value;
|
||||
break;
|
||||
case 16:
|
||||
if (cgen_current_endian == CGEN_ENDIAN_BIG)
|
||||
bfd_putb16 (insn_value, buf);
|
||||
else
|
||||
bfd_putl16 (insn_value, buf);
|
||||
break;
|
||||
case 32:
|
||||
if (cgen_current_endian == CGEN_ENDIAN_BIG)
|
||||
bfd_putb32 (insn_value, buf);
|
||||
else
|
||||
bfd_putl32 (insn_value, buf);
|
||||
break;
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
#else
|
||||
abort (); /* FIXME: unfinished */
|
||||
#endif
|
||||
|
||||
/* The instructions are stored in hash lists.
|
||||
Pick the first one and keep trying until we find the right one. */
|
||||
|
||||
insn_list = CGEN_DIS_LOOKUP_INSN (buf, insn_value);
|
||||
while (insn_list != NULL)
|
||||
{
|
||||
insn = insn_list->insn;
|
||||
|
||||
/* Basic bit mask must be correct. */
|
||||
/* ??? May wish to allow target to defer this check until the extract
|
||||
handler. */
|
||||
if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
|
||||
{
|
||||
length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields);
|
||||
if (length > 0)
|
||||
return insn;
|
||||
}
|
||||
|
||||
insn_list = CGEN_DIS_NEXT_INSN (insn_list);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields);
|
||||
if (length > 0)
|
||||
return insn;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Fill in the operand instances used by insn INSN_VALUE.
|
||||
If non-null INS is the insn table entry.
|
||||
Otherwise INSN_VALUE is examined to compute it.
|
||||
LENGTH is the number of bits in INSN_VALUE if known, otherwise 0.
|
||||
INDICES is a pointer to a buffer of MAX_OPERANDS ints to be filled in.
|
||||
The result a pointer to the insn table entry, or NULL if the instruction
|
||||
wasn't recognized. */
|
||||
|
||||
const CGEN_INSN *
|
||||
@arch@_cgen_get_insn_operands (insn, insn_value, length, indices)
|
||||
const CGEN_INSN *insn;
|
||||
cgen_insn_t insn_value;
|
||||
int length;
|
||||
int *indices;
|
||||
{
|
||||
CGEN_FIELDS fields;
|
||||
const CGEN_OPERAND_INSTANCE *opinst;
|
||||
int i;
|
||||
|
||||
insn = @arch@_cgen_lookup_insn (insn, insn_value, length, &fields);
|
||||
if (! insn)
|
||||
return NULL;
|
||||
|
||||
for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
|
||||
CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
|
||||
++i, ++opinst)
|
||||
{
|
||||
const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
|
||||
if (op == NULL)
|
||||
indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
|
||||
else
|
||||
indices[i] = @arch@_cgen_get_operand (CGEN_OPERAND_INDEX (op), &fields);
|
||||
}
|
||||
|
||||
return insn;
|
||||
}
|
||||
|
|
@ -304,26 +304,46 @@ m32r_cgen_parse_operand (opindex, strp, fields)
|
|||
case M32R_OPERAND_UIMM16 :
|
||||
errmsg = cgen_parse_unsigned_integer (strp, 11, 0, 65535, &fields->f_uimm16);
|
||||
break;
|
||||
/* start-sanitize-m32rx */
|
||||
case M32R_OPERAND_IMM1 :
|
||||
errmsg = cgen_parse_unsigned_integer (strp, 12, 0, 1, &fields->f_imm1);
|
||||
break;
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
case M32R_OPERAND_ACCD :
|
||||
errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_accums, & fields->f_accd);
|
||||
break;
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
case M32R_OPERAND_ACCS :
|
||||
errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_accums, & fields->f_accs);
|
||||
break;
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
case M32R_OPERAND_ACC :
|
||||
errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_accums, & fields->f_acc);
|
||||
break;
|
||||
/* end-sanitize-m32rx */
|
||||
case M32R_OPERAND_HI16 :
|
||||
errmsg = parse_h_hi16 (strp, 12, 0, 65535, &fields->f_hi16);
|
||||
errmsg = parse_h_hi16 (strp, 16, 0, 65535, &fields->f_hi16);
|
||||
break;
|
||||
case M32R_OPERAND_SLO16 :
|
||||
errmsg = parse_h_slo16 (strp, 13, -32768, 32767, &fields->f_simm16);
|
||||
errmsg = parse_h_slo16 (strp, 17, -32768, 32767, &fields->f_simm16);
|
||||
break;
|
||||
case M32R_OPERAND_ULO16 :
|
||||
errmsg = parse_h_ulo16 (strp, 14, 0, 65535, &fields->f_uimm16);
|
||||
errmsg = parse_h_ulo16 (strp, 18, 0, 65535, &fields->f_uimm16);
|
||||
break;
|
||||
case M32R_OPERAND_UIMM24 :
|
||||
errmsg = cgen_parse_address (strp, 15, 0, NULL, & fields->f_uimm24);
|
||||
errmsg = cgen_parse_address (strp, 19, 0, NULL, & fields->f_uimm24);
|
||||
break;
|
||||
case M32R_OPERAND_DISP8 :
|
||||
errmsg = cgen_parse_address (strp, 16, 0, NULL, & fields->f_disp8);
|
||||
errmsg = cgen_parse_address (strp, 20, 0, NULL, & fields->f_disp8);
|
||||
break;
|
||||
case M32R_OPERAND_DISP16 :
|
||||
errmsg = cgen_parse_address (strp, 17, 0, NULL, & fields->f_disp16);
|
||||
errmsg = cgen_parse_address (strp, 21, 0, NULL, & fields->f_disp16);
|
||||
break;
|
||||
case M32R_OPERAND_DISP24 :
|
||||
errmsg = cgen_parse_address (strp, 18, 0, NULL, & fields->f_disp24);
|
||||
errmsg = cgen_parse_address (strp, 22, 0, NULL, & fields->f_disp24);
|
||||
break;
|
||||
|
||||
default :
|
||||
|
|
@ -390,6 +410,26 @@ m32r_cgen_insert_operand (opindex, fields, buffer)
|
|||
case M32R_OPERAND_UIMM16 :
|
||||
insert_normal (fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
|
||||
break;
|
||||
/* start-sanitize-m32rx */
|
||||
case M32R_OPERAND_IMM1 :
|
||||
insert_normal (fields->f_imm1, 0|(1<<CGEN_OPERAND_UNSIGNED), 15, 1, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
|
||||
break;
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
case M32R_OPERAND_ACCD :
|
||||
insert_normal (fields->f_accd, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 2, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
|
||||
break;
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
case M32R_OPERAND_ACCS :
|
||||
insert_normal (fields->f_accs, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 2, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
|
||||
break;
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
case M32R_OPERAND_ACC :
|
||||
insert_normal (fields->f_acc, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 1, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
|
||||
break;
|
||||
/* end-sanitize-m32rx */
|
||||
case M32R_OPERAND_HI16 :
|
||||
insert_normal (fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
|
||||
break;
|
||||
|
|
@ -470,6 +510,26 @@ m32r_cgen_validate_operand (opindex, fields)
|
|||
case M32R_OPERAND_UIMM16 :
|
||||
errmsg = cgen_validate_unsigned_integer (fields->f_uimm16, 0, 65535);
|
||||
break;
|
||||
/* start-sanitize-m32rx */
|
||||
case M32R_OPERAND_IMM1 :
|
||||
errmsg = cgen_validate_unsigned_integer (fields->f_imm1, 0, 1);
|
||||
break;
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
case M32R_OPERAND_ACCD :
|
||||
/* nothing to do */
|
||||
break;
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
case M32R_OPERAND_ACCS :
|
||||
/* nothing to do */
|
||||
break;
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
case M32R_OPERAND_ACC :
|
||||
/* nothing to do */
|
||||
break;
|
||||
/* end-sanitize-m32rx */
|
||||
case M32R_OPERAND_HI16 :
|
||||
errmsg = cgen_validate_unsigned_integer (fields->f_hi16, 0, 65535);
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -57,7 +57,7 @@ static void print_insn_normal
|
|||
|
||||
static int
|
||||
extract_normal (buf_ctrl, insn_value, attrs, start, length, shift, total_length, valuep)
|
||||
void *buf_ctrl;
|
||||
PTR buf_ctrl;
|
||||
cgen_insn_t insn_value;
|
||||
unsigned int attrs;
|
||||
int start, length, shift, total_length;
|
||||
|
|
@ -94,7 +94,7 @@ extract_normal (buf_ctrl, insn_value, attrs, start, length, shift, total_length,
|
|||
|
||||
static void
|
||||
print_normal (dis_info, value, attrs, pc, length)
|
||||
void *dis_info;
|
||||
PTR dis_info;
|
||||
long value;
|
||||
unsigned int attrs;
|
||||
unsigned long pc; /* FIXME: should be bfd_vma */
|
||||
|
|
@ -121,7 +121,7 @@ print_normal (dis_info, value, attrs, pc, length)
|
|||
|
||||
static void
|
||||
print_keyword (dis_info, keyword_table, value, attrs)
|
||||
void *dis_info;
|
||||
PTR dis_info;
|
||||
CGEN_KEYWORD *keyword_table;
|
||||
long value;
|
||||
CGEN_ATTR *attrs;
|
||||
|
|
@ -197,7 +197,7 @@ my_print_insn (pc, info, buf, buflen)
|
|||
CGEN_INLINE int
|
||||
m32r_cgen_extract_operand (opindex, buf_ctrl, insn_value, fields)
|
||||
int opindex;
|
||||
void * buf_ctrl;
|
||||
PTR buf_ctrl;
|
||||
cgen_insn_t insn_value;
|
||||
CGEN_FIELDS * fields;
|
||||
{
|
||||
|
|
@ -238,6 +238,26 @@ m32r_cgen_extract_operand (opindex, buf_ctrl, insn_value, fields)
|
|||
case M32R_OPERAND_UIMM16 :
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_uimm16);
|
||||
break;
|
||||
/* start-sanitize-m32rx */
|
||||
case M32R_OPERAND_IMM1 :
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 15, 1, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_imm1);
|
||||
break;
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
case M32R_OPERAND_ACCD :
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 2, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_accd);
|
||||
break;
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
case M32R_OPERAND_ACCS :
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 2, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_accs);
|
||||
break;
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
case M32R_OPERAND_ACC :
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 1, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_acc);
|
||||
break;
|
||||
/* end-sanitize-m32rx */
|
||||
case M32R_OPERAND_HI16 :
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_hi16);
|
||||
break;
|
||||
|
|
@ -327,6 +347,26 @@ m32r_cgen_print_operand (opindex, info, fields, attrs, pc, length)
|
|||
case M32R_OPERAND_UIMM16 :
|
||||
print_normal (info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
|
||||
break;
|
||||
/* start-sanitize-m32rx */
|
||||
case M32R_OPERAND_IMM1 :
|
||||
print_normal (info, fields->f_imm1, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
|
||||
break;
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
case M32R_OPERAND_ACCD :
|
||||
print_keyword (info, & m32r_cgen_opval_h_accums, fields->f_accd, 0|(1<<CGEN_OPERAND_UNSIGNED));
|
||||
break;
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
case M32R_OPERAND_ACCS :
|
||||
print_keyword (info, & m32r_cgen_opval_h_accums, fields->f_accs, 0|(1<<CGEN_OPERAND_UNSIGNED));
|
||||
break;
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
case M32R_OPERAND_ACC :
|
||||
print_keyword (info, & m32r_cgen_opval_h_accums, fields->f_acc, 0|(1<<CGEN_OPERAND_UNSIGNED));
|
||||
break;
|
||||
/* end-sanitize-m32rx */
|
||||
case M32R_OPERAND_HI16 :
|
||||
print_normal (info, fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
|
||||
break;
|
||||
|
|
@ -389,7 +429,7 @@ m32r_cgen_init_dis (mach, endian)
|
|||
static int
|
||||
extract_insn_normal (insn, buf_ctrl, insn_value, fields)
|
||||
const CGEN_INSN *insn;
|
||||
void *buf_ctrl;
|
||||
PTR buf_ctrl;
|
||||
cgen_insn_t insn_value;
|
||||
CGEN_FIELDS *fields;
|
||||
{
|
||||
|
|
@ -419,13 +459,13 @@ extract_insn_normal (insn, buf_ctrl, insn_value, fields)
|
|||
|
||||
/* Default insn printer.
|
||||
|
||||
DIS_INFO is defined as `void *' so the disassembler needn't know anything
|
||||
DIS_INFO is defined as `PTR' so the disassembler needn't know anything
|
||||
about disassemble_info.
|
||||
*/
|
||||
|
||||
static void
|
||||
print_insn_normal (dis_info, insn, fields, pc, length)
|
||||
void *dis_info;
|
||||
PTR dis_info;
|
||||
const CGEN_INSN *insn;
|
||||
CGEN_FIELDS *fields;
|
||||
bfd_vma pc;
|
||||
|
|
@ -473,7 +513,6 @@ print_insn (pc, info, buf, buflen)
|
|||
char *buf;
|
||||
int buflen;
|
||||
{
|
||||
int i;
|
||||
unsigned long insn_value;
|
||||
const CGEN_INSN_LIST *insn_list;
|
||||
|
||||
|
|
@ -499,7 +538,6 @@ print_insn (pc, info, buf, buflen)
|
|||
while (insn_list != NULL)
|
||||
{
|
||||
const CGEN_INSN *insn = insn_list->insn;
|
||||
const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
|
||||
CGEN_FIELDS fields;
|
||||
int length;
|
||||
|
||||
|
|
|
|||
1836
opcodes/m32r-opc.c
1836
opcodes/m32r-opc.c
File diff suppressed because it is too large
Load Diff
|
|
@ -75,6 +75,12 @@ typedef enum cgen_operand_type {
|
|||
M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1
|
||||
, M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8
|
||||
, M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5, M32R_OPERAND_UIMM16
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_OPERAND_IMM1
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_OPERAND_ACCD
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_OPERAND_ACCS
|
||||
/* end-sanitize-m32rx */
|
||||
|
|
@ -101,6 +107,16 @@ typedef enum mach_attr {
|
|||
, MACH_MAX
|
||||
} MACH_ATTR;
|
||||
|
||||
/* Enum declaration for instructions which modify the link register as a side effect. */
|
||||
typedef enum write_lr_attr {
|
||||
WRITE_LR_NO, WRITE_LR_YES
|
||||
} WRITE_LR_ATTR;
|
||||
|
||||
/* Enum declaration for instructions which modify their source register as a side effect. */
|
||||
typedef enum write_src_attr {
|
||||
WRITE_SRC_NO, WRITE_SRC_YES
|
||||
} WRITE_SRC_ATTR;
|
||||
|
||||
/* start-sanitize-m32rx */
|
||||
/* Enum declaration for parallel execution pipeline selection. */
|
||||
typedef enum pipe_attr {
|
||||
|
|
@ -111,9 +127,12 @@ typedef enum pipe_attr {
|
|||
/* Number of architecture variants. */
|
||||
#define MAX_MACHS ((int) MACH_MAX)
|
||||
|
||||
/* Number of operands. */
|
||||
/* Number of operands types. */
|
||||
#define MAX_OPERANDS ((int) M32R_OPERAND_MAX)
|
||||
|
||||
/* Maximum number of operands referenced by any insn. */
|
||||
#define MAX_OPERAND_INSTANCES 8
|
||||
|
||||
/* Operand and instruction attribute indices. */
|
||||
|
||||
/* Enum declaration for cgen_operand attrs. */
|
||||
|
|
@ -132,8 +151,9 @@ typedef enum cgen_insn_attr {
|
|||
/* start-sanitize-m32rx */
|
||||
, CGEN_INSN_PIPE
|
||||
/* end-sanitize-m32rx */
|
||||
, CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI, CGEN_INSN_FILL_SLOT, CGEN_INSN_PARALLEL
|
||||
, CGEN_INSN_RELAX, CGEN_INSN_RELAXABLE, CGEN_INSN_UNCOND_CTI
|
||||
, CGEN_INSN_WRITE_LR, CGEN_INSN_WRITE_SRC, CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI
|
||||
, CGEN_INSN_FILL_SLOT, CGEN_INSN_PARALLEL, CGEN_INSN_RELAX, CGEN_INSN_RELAXABLE
|
||||
, CGEN_INSN_UNCOND_CTI
|
||||
} CGEN_INSN_ATTR;
|
||||
|
||||
/* Number of non-boolean elements in cgen_insn. */
|
||||
|
|
@ -187,6 +207,9 @@ typedef enum cgen_insn_type {
|
|||
, M32R_INSN_CMPZ
|
||||
/* end-sanitize-m32rx */
|
||||
, M32R_INSN_DIV, M32R_INSN_DIVU, M32R_INSN_REM, M32R_INSN_REMU
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_DIVH
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_JC
|
||||
/* end-sanitize-m32rx */
|
||||
|
|
@ -240,11 +263,23 @@ typedef enum cgen_insn_type {
|
|||
, M32R_INSN_MVTC, M32R_INSN_NEG, M32R_INSN_NOP, M32R_INSN_NOT
|
||||
, M32R_INSN_RAC
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_RAC_A
|
||||
, M32R_INSN_RAC_D
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_RAC_DS
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_RAC_DSI
|
||||
/* end-sanitize-m32rx */
|
||||
, M32R_INSN_RACH
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_RACH_A
|
||||
, M32R_INSN_RACH_D
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_RACH_DS
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_RACH_DSI
|
||||
/* end-sanitize-m32rx */
|
||||
, M32R_INSN_RTE, M32R_INSN_SETH, M32R_INSN_SETH_A, M32R_INSN_SLL
|
||||
, M32R_INSN_SLL3, M32R_INSN_SLL3_A, M32R_INSN_SLLI, M32R_INSN_SLLI_A
|
||||
|
|
@ -281,7 +316,7 @@ typedef enum cgen_insn_type {
|
|||
, M32R_INSN_MULWU1
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_MACHL1
|
||||
, M32R_INSN_MACLH1
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_SC
|
||||
|
|
@ -301,7 +336,7 @@ typedef enum cgen_insn_type {
|
|||
#include "opcode/cgen.h"
|
||||
|
||||
/* This struct records data prior to insertion or after extraction. */
|
||||
typedef struct cgen_fields
|
||||
struct cgen_fields
|
||||
{
|
||||
long f_nil;
|
||||
long f_op1;
|
||||
|
|
@ -331,14 +366,45 @@ typedef struct cgen_fields
|
|||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
long f_accs;
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
long f_accd;
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
long f_bits67;
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
long f_bit14;
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
long f_imm1;
|
||||
/* end-sanitize-m32rx */
|
||||
int length;
|
||||
} CGEN_FIELDS;
|
||||
};
|
||||
|
||||
/* Attributes. */
|
||||
extern const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[];
|
||||
extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[];
|
||||
|
||||
/* Enum declaration for m32r hardware types. */
|
||||
typedef enum hw_type {
|
||||
HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT
|
||||
, HW_H_ADDR, HW_H_IADDR, HW_H_HI16, HW_H_SLO16
|
||||
, HW_H_ULO16, HW_H_GR, HW_H_CR, HW_H_ACCUM
|
||||
/* start-sanitize-m32rx */
|
||||
, HW_H_ACCUMS
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, HW_H_ABORT
|
||||
/* end-sanitize-m32rx */
|
||||
, HW_H_COND, HW_H_SM, HW_H_BSM, HW_H_IE
|
||||
, HW_H_BIE, HW_H_BCOND, HW_H_BPC, HW_MAX
|
||||
} HW_TYPE;
|
||||
|
||||
#define MAX_HW ((int) HW_MAX)
|
||||
|
||||
/* Hardware decls. */
|
||||
|
||||
extern CGEN_KEYWORD m32r_cgen_opval_h_gr;
|
||||
extern CGEN_KEYWORD m32r_cgen_opval_h_cr;
|
||||
/* start-sanitize-m32rx */
|
||||
|
|
@ -368,6 +434,7 @@ extern CGEN_KEYWORD m32r_cgen_opval_h_accums;
|
|||
(X (buffer) | \
|
||||
(X (buffer) == 0x40 || X (buffer) == 0xe0 || X (buffer) == 0x60 || X (buffer) == 0x50 ? 0 \
|
||||
: X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \
|
||||
: X (buffer) == 0x30 ? ((((unsigned char *) (buffer))[1] & 0x70) >> 4) \
|
||||
: ((((unsigned char *) (buffer))[1] & 0xf0) >> 4)))
|
||||
|
||||
/* -- */
|
||||
|
|
|
|||
Loading…
Reference in New Issue