Thu Jul 25 12:03:33 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* tc-d10v.c: Fix packaging bug. Added range checking. Added kludge for divs instruction. Fixed minor problem with multiple text sections. * tc-d10v.h (d10v_cleanup): Change prototype.
This commit is contained in:
Martin Hunt
parent
7c09665202
commit
ab48956f99
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@ -58,7 +58,7 @@ static int register_name PARAMS ((expressionS *expressionP));
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static int postfix PARAMS ((char *p));
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static bfd_reloc_code_real_type get_reloc PARAMS ((struct d10v_operand *op));
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static int get_operands PARAMS ((expressionS exp[]));
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static unsigned long build_insn PARAMS ((struct d10v_opcode *opcode, expressionS *opers));
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static unsigned long build_insn PARAMS ((struct d10v_opcode *opcode, expressionS *opers, unsigned long insn));
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static void write_long PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx));
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static void write_1_short PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx));
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static int write_2_short PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1,
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@ -144,6 +144,35 @@ register_name (expressionP)
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return 0;
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}
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static int
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check_range (num, bits, sign)
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unsigned long num;
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int bits;
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int sign;
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{
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long min, max;
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int retval=0;
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if (sign)
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{
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max = (1 << (bits - 1)) - 1;
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min = - (1 << (bits - 1));
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if (((long)num > max) || ((long)num < min))
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retval = 1;
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}
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else
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{
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max = (1 << bits) - 1;
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min = 0;
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if ((num > max) || (num < min))
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retval = 1;
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}
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return retval;
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}
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void
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md_show_usage (stream)
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FILE *stream;
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@ -372,6 +401,10 @@ d10v_insert_operand (insn, op_type, value, left)
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/* truncate to the proper number of bits */
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/* FIXME: overflow checking here? */
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if (check_range (value, bits, d10v_operands[op_type].flags & OPERAND_SIGNED))
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as_bad("operand out of range: %d",value);
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value &= 0x7FFFFFFF >> (31 - bits);
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insn |= (value << shift);
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@ -383,15 +416,23 @@ d10v_insert_operand (insn, op_type, value, left)
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and the array of operand expressions and returns the instruction */
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static unsigned long
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build_insn (opcode, opers)
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build_insn (opcode, opers, insn)
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struct d10v_opcode *opcode;
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expressionS *opers;
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unsigned long insn;
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{
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int i, bits, shift, flags;
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unsigned long insn;
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int i, bits, shift, flags, format;
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unsigned int number;
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insn = opcode->opcode;
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/* the insn argument is only used for the DIVS kludge */
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if (insn)
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format = LONG_R;
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else
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{
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insn = opcode->opcode;
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format = opcode->format;
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}
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for (i=0;opcode->operands[i];i++)
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{
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flags = d10v_operands[opcode->operands[i]].flags;
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@ -402,7 +443,7 @@ build_insn (opcode, opers)
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if (flags & OPERAND_REG)
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{
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number &= REGISTER_MASK;
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if (opcode->format == LONG_L)
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if (format == LONG_L)
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shift += 15;
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}
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@ -427,10 +468,18 @@ build_insn (opcode, opers)
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}
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/* truncate to the proper number of bits */
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/* FIXME: overflow checking here? */
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if ((opers[i].X_op == O_constant) && check_range (number, bits, flags & OPERAND_SIGNED))
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as_bad("operand out of range: %d",number);
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number &= 0x7FFFFFFF >> (31 - bits);
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insn = insn | (number << shift);
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}
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/* kludge: for DIVS, we need to put the operands in twice */
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/* on the second pass, format is changed to LONG_R to force */
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/* the second set of operands to not be shifted over 15 */
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if ((opcode->opcode == OPCODE_DIVS) && (format==LONG_L))
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insn = build_insn (opcode, opers, insn);
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return insn;
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}
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@ -480,7 +529,14 @@ write_1_short (opcode, insn, fx)
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char *f = frag_more(4);
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int i;
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insn |= FM00 | (NOP << 15);
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/* the other container needs to be NOP */
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/* according to 4.3.1: for FM=00, sub-instructions performed only
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by IU cannot be encoded in L-container. */
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if (opcode->unit == IU)
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insn |= FM00 | (NOP << 15); /* right container */
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else
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insn = FM00 | (insn << 15) | NOP; /* left container */
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/* printf("INSN: %08x\n",insn); */
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number_to_chars_bigendian (f, insn, 4);
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for (i=0; i < fx->fc; i++)
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@ -720,7 +776,7 @@ do_assemble (str, opcode)
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*opcode = (struct d10v_opcode *)hash_find (d10v_hash, name);
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if (*opcode == NULL)
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{
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as_bad ("unknown opcode");
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as_fatal ("unknown opcode: %s",name);
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return;
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}
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@ -730,56 +786,94 @@ do_assemble (str, opcode)
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/* get all the operands and save them as expressions */
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numops = get_operands (myops);
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/* now search the opcode table table for one with operands */
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/* that match what we've got */
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do
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/* now see if the operand is a fake. If so, find the correct size */
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/* instruction, if possible */
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match = 0;
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if ((*opcode)->format == OPCODE_FAKE)
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{
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match = 1;
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for (i = 0; (*opcode)->operands[i]; i++)
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int opnum = (*opcode)->operands[0];
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if (myops[opnum].X_op == O_constant)
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{
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int flags = d10v_operands[(*opcode)->operands[i]].flags;
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if (myops[i].X_op==0)
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next_opcode=(*opcode)+1;
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for (i=0; (*opcode)->operands[i+1]; i++)
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{
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match=0;
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break;
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int bits = d10v_operands[next_opcode->operands[opnum]].bits;
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int flags = d10v_operands[next_opcode->operands[opnum]].flags;
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if (!check_range (myops[opnum].X_add_number, bits, flags & OPERAND_SIGNED))
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{
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match = 1;
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break;
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}
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next_opcode++;
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}
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if (flags & OPERAND_REG)
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}
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else
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{
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/* not a constant, so use a long instruction */
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next_opcode = (*opcode)+2;
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match = 1;
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}
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if (match)
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*opcode = next_opcode;
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else
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as_fatal ("value out of range");
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}
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else
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{
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/* now search the opcode table table for one with operands */
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/* that match what we've got */
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while (!match)
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{
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match = 1;
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for (i = 0; (*opcode)->operands[i]; i++)
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{
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if ((myops[i].X_op != O_register) ||
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((flags & OPERAND_ACC) != (myops[i].X_add_number & OPERAND_ACC)) ||
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((flags & OPERAND_FLAG) != (myops[i].X_add_number & OPERAND_FLAG)) ||
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((flags & OPERAND_CONTROL) != (myops[i].X_add_number & OPERAND_CONTROL)))
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int flags = d10v_operands[(*opcode)->operands[i]].flags;
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int X_op = myops[i].X_op;
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int num = myops[i].X_add_number;
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if (X_op==0)
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{
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match=0;
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break;
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}
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}
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if (((flags & OPERAND_MINUS) && ((myops[i].X_op != O_absent) || (myops[i].X_add_number != OPERAND_MINUS))) ||
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((flags & OPERAND_PLUS) && ((myops[i].X_op != O_absent) || (myops[i].X_add_number != OPERAND_PLUS))) ||
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((flags & OPERAND_ATMINUS) && ((myops[i].X_op != O_absent) || (myops[i].X_add_number != OPERAND_ATMINUS))) ||
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((flags & OPERAND_ATPAR) && ((myops[i].X_op != O_absent) || (myops[i].X_add_number != OPERAND_ATPAR))) ||
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((flags & OPERAND_ATSIGN) && ((myops[i].X_op != O_absent) || (myops[i].X_add_number != OPERAND_ATSIGN))))
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{
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match=0;
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break;
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}
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if (flags & OPERAND_REG)
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{
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if ((X_op != O_register) ||
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((flags & OPERAND_ACC) != (num & OPERAND_ACC)) ||
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((flags & OPERAND_FLAG) != (num & OPERAND_FLAG)) ||
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((flags & OPERAND_CONTROL) != (num & OPERAND_CONTROL)))
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{
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match=0;
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break;
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}
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}
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if (((flags & OPERAND_MINUS) && ((X_op != O_absent) || (num != OPERAND_MINUS))) ||
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((flags & OPERAND_PLUS) && ((X_op != O_absent) || (num != OPERAND_PLUS))) ||
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((flags & OPERAND_ATMINUS) && ((X_op != O_absent) || (num != OPERAND_ATMINUS))) ||
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((flags & OPERAND_ATPAR) && ((X_op != O_absent) || (num != OPERAND_ATPAR))) ||
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((flags & OPERAND_ATSIGN) && ((X_op != O_absent) || (num != OPERAND_ATSIGN))))
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{
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match=0;
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break;
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}
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}
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/* we're only done if the operands matched AND there
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are no more to check */
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if (match && myops[i].X_op==0)
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break;
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next_opcode = (*opcode)+1;
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if (next_opcode->opcode == 0)
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break;
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if (strcmp(next_opcode->name, (*opcode)->name))
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break;
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(*opcode) = next_opcode;
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}
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/* we're only done if the operands matched AND there
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are no more to check */
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if (match && myops[i].X_op==0)
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break;
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next_opcode = (*opcode)+1;
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if (next_opcode->opcode == 0)
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break;
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if (strcmp(next_opcode->name, (*opcode)->name))
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break;
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(*opcode) = next_opcode;
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} while (!match);
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}
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if (!match)
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{
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@ -812,8 +906,8 @@ do_assemble (str, opcode)
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/* at this point, we have "opcode" pointing to the opcode entry in the
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d10v opcode table, with myops filled out with the operands. */
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insn = build_insn ((*opcode), myops);
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/* printf("sub-insn = %lx\n",insn); */
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insn = build_insn ((*opcode), myops, 0);
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/* printf("sub-insn = %lx\n",insn); */
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return (insn);
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}
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@ -947,12 +1041,13 @@ md_apply_fix3 (fixp, valuep, seg)
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instructions to see if it can package them with the next instruction, there may
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be a short instruction that still needs written. */
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int
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d10v_cleanup()
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d10v_cleanup (done)
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int done;
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{
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segT seg;
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subsegT subseg;
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if (prev_opcode)
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if ( prev_opcode && (done || (now_seg == prev_seg) && (now_subseg == prev_subseg)))
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{
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seg = now_seg;
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subseg = now_subseg;
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