* m32r.cpu (sth-plus): Fix address mode and calculation.
(stb-plus): Ditto. (clrpsw): Fix mask calculation. (bset, bclr, btst): Make mode in bit calculation match expression. * xc16x.cpu (rtl-version): Set to 0.8. (gr-names, ext-names,psw-names): Update, print-name -> enum-prefix, make uppercase. Remove unnecessary name-prefix spec. (grb-names, conditioncode-names, extconditioncode-names): Ditto. (grb8-names, r8-names, regmem8-names, regdiv8-names): Ditto. (reg0-name, reg0-name1, regbmem8-names, memgr8-names): Ditto. (h-cr): New hardware. (muls): Comment out parts that won't compile, add fixme. (mulu, divl, divlu, jmpabs, jmpa-, jmprel, jbc, jnbs, callr): Ditto. (scxti, scxtmg, scxtm, bclear, bclr18, bset19, bitset, bmov): Ditto. (bmovn, band, bor, bxor, bcmp, bfldl, bfldh): Ditto.
This commit is contained in:
parent
bd30e45a34
commit
ab5f875d24
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@ -1,3 +1,22 @@
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2009-09-23 Doug Evans <dje@sebabeach.org>
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* m32r.cpu (sth-plus): Fix address mode and calculation.
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(stb-plus): Ditto.
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(clrpsw): Fix mask calculation.
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(bset, bclr, btst): Make mode in bit calculation match expression.
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* xc16x.cpu (rtl-version): Set to 0.8.
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(gr-names, ext-names,psw-names): Update, print-name -> enum-prefix,
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make uppercase. Remove unnecessary name-prefix spec.
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(grb-names, conditioncode-names, extconditioncode-names): Ditto.
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(grb8-names, r8-names, regmem8-names, regdiv8-names): Ditto.
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(reg0-name, reg0-name1, regbmem8-names, memgr8-names): Ditto.
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(h-cr): New hardware.
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(muls): Comment out parts that won't compile, add fixme.
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(mulu, divl, divlu, jmpabs, jmpa-, jmprel, jbc, jnbs, callr): Ditto.
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(scxti, scxtmg, scxtm, bclear, bclr18, bset19, bitset, bmov): Ditto.
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(bmovn, band, bor, bxor, bcmp, bfldl, bfldh): Ditto.
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2009-07-16 Doug Evans <dje@sebabeach.org>
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* cpu/simplify.inc (*): One line doc strings don't need \n.
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27
cpu/m32r.cpu
27
cpu/m32r.cpu
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@ -2089,10 +2089,10 @@
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"sth $src1,@$src2+"
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(+ OP1_2 OP2_3 src1 src2)
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; This has to be coded carefully to avoid an "earlyclobber" of src2.
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(sequence ((HI new-src2))
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(set (mem HI new-src2) src1)
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(set new-src2 (add src2 (const 2)))
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(set src2 new-src2))
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(sequence ((WI new-src2))
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(set new-src2 src2)
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(set (mem HI new-src2) src1)
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(set src2 (add new-src2 (const 2))))
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((m32rx (unit u-store)
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(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
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(m32r2 (unit u-store)
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@ -2105,10 +2105,10 @@
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"stb $src1,@$src2+"
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(+ OP1_2 OP2_1 src1 src2)
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; This has to be coded carefully to avoid an "earlyclobber" of src2.
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(sequence ((QI new-src2))
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(set (mem QI new-src2) src1)
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(set new-src2 (add src2 (const 1)))
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(set src2 new-src2))
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(sequence ((WI new-src2))
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(set new-src2 src2)
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(set (mem QI new-src2) src1)
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(set src2 (add new-src2 (const 1)))
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((m32rx (unit u-store)
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(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
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(m32r2 (unit u-store)
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@ -2375,14 +2375,14 @@
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()
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)
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; PSW &= ~((unsigned char) uimm8 | 0x000ff00)
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; PSW &= ((~ uimm8) | 0xff00)
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(dni clrpsw "clrpsw"
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((PIPE O) SPECIAL_M32R)
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"clrpsw $uimm8"
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(+ OP1_7 (f-r1 2) uimm8)
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(set USI (reg h-cr 0)
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(and USI (reg h-cr 0)
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(or USI (inv BI uimm8) (const #xff00))))
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(or USI (zext SI (inv QI uimm8)) (const #xff00))))
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()
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)
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@ -2402,7 +2402,7 @@
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(+ OP1_10 (f-bit4 0) uimm3 OP2_6 sr slo16)
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(set QI (mem QI (add sr slo16))
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(or QI (mem QI (add sr slo16))
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(sll USI (const 1) (sub (const 7) uimm3))))
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(sll QI (const 1) (sub (const 7) uimm3))))
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()
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)
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@ -2413,7 +2413,7 @@
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(+ OP1_10 (f-bit4 0) uimm3 OP2_7 sr slo16)
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(set QI (mem QI (add sr slo16))
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(and QI (mem QI (add sr slo16))
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(inv QI (sll USI (const 1) (sub (const 7) uimm3)))))
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(inv QI (sll QI (const 1) (sub (const 7) uimm3)))))
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()
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)
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@ -2422,7 +2422,6 @@
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(SPECIAL_M32R (PIPE O))
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"btst $uimm3,$sr"
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(+ OP1_0 (f-bit4 0) uimm3 OP2_15 sr)
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(set condbit (and QI (srl USI sr (sub (const 7) uimm3)) (const 1)))
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(set condbit (and QI (srl QI sr (sub (const 7) uimm3)) (const 1)))
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()
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)
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172
cpu/xc16x.cpu
172
cpu/xc16x.cpu
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@ -22,6 +22,8 @@
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; Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
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; 02110-1301, USA.
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(define-rtl-version 0 8)
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(include "simplify.inc")
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; define-arch appears first
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@ -226,8 +228,7 @@
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(define-keyword
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(name gr-names)
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(print-name h-gr)
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(prefix "")
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(enum-prefix H-GR-)
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(values (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7)
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(r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15))
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(indices extern-keyword gr-names)
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)
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;; HACK: Various semantics refer to h-cr.
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;; This is here to keep things working.
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(define-hardware
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(name h-cr)
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(comment "cr registers")
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(attrs PROFILE CACHE-ADDR)
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(type register HI (16))
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(indices extern-keyword gr-names)
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)
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(define-keyword
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(name ext-names)
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(print-name h-ext)
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(prefix "")
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(enum-prefix H-EXT-)
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(values (0x1 0) (0x2 1) (0x3 2) (0x4 3)
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("1" 0) ("2" 1) ("3" 2) ("4" 3))
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(define-keyword
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(name psw-names)
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(print-name h-psw)
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(prefix "")
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(enum-prefix H-PSW-)
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(values ("IEN" 136) ("r0.11" 240) ("r1.11" 241) ("r2.11" 242) ("r3.11" 243) ("r4.11" 244)
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("r5.11" 245) ("r6.11" 246) ("r7.11" 247) ("r8.11" 248)
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("r9.11" 249) ("r10.11" 250) ("r11.11" 251) ("r12.11" 252)
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@ -277,8 +286,7 @@
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(define-keyword
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(name grb-names)
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(print-name h-grb)
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(prefix "")
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(enum-prefix H-GRB-)
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(values (rl0 0) (rh0 1) (rl1 2) (rh1 3) (rl2 4) (rh2 5) (rl3 6) (rh3 7)
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(rl4 8) (rh4 9) (rl5 10) (rh5 11) (rl6 12) (rh6 13) (rl7 14) (rh7 15))
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)
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@ -293,8 +301,7 @@
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(define-keyword
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(name conditioncode-names)
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(print-name h-cc)
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(prefix "")
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(enum-prefix H-CC-)
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(values (cc_UC 0) (cc_NET 1) (cc_Z 2) (cc_EQ 2) (cc_NZ 3) (cc_NE 3) (cc_V 4) (cc_NV 5) (cc_N 6) (cc_NN 7) (cc_ULT 8) (cc_UGE 9)
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(cc_C 8) (cc_NC 9) (cc_SGT 10) (cc_SLE 11) (cc_SLT 12) (cc_SGE 13) (cc_UGT 14)
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(cc_ULE 15))
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@ -309,8 +316,7 @@
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(define-keyword
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(name extconditioncode-names)
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(print-name h-ecc)
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(prefix "")
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(enum-prefix H-ECC-)
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(values(cc_UC 0) (cc_NET 2) (cc_Z 4) (cc_EQ 4) (cc_NZ 6) (cc_NE 6) (cc_V 8) (cc_NV 10) (cc_N 12) (cc_NN 14) (cc_ULT 16) (cc_UGE 18) (cc_C 16) (cc_NC 18) (cc_SGT 20)
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(cc_SLE 22) (cc_SLT 24) (cc_SGE 26) (cc_UGT 28) (cc_ULE 30) (cc_nusr0 1)
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(cc_nusr1 3) (cc_usr0 5) (cc_usr1 7))
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@ -325,8 +331,7 @@
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(define-keyword
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(name grb8-names)
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(print-name h-grb8)
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(prefix "")
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(enum-prefix H-GRB8-)
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(values (dpp0 0) (dpp1 1) (dpp2 2) (dpp3 3)
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(psw 136) (cp 8) (mdl 7) (mdh 6)
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(mdc 135) (sp 9) (csp 4) (vecseg 137)
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@ -346,8 +351,7 @@
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(define-keyword
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(name r8-names)
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(print-name h-r8)
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(prefix "")
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(enum-prefix H-R8-)
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(values (dpp0 0) (dpp1 1) (dpp2 2) (dpp3 3)
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(psw 136) (cp 8) (mdl 7) (mdh 6)
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(mdc 135) (sp 9) (csp 4) (vecseg 137)
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@ -367,8 +371,7 @@
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(define-keyword
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(name regmem8-names)
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(print-name h-regmem8)
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(prefix "")
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(enum-prefix H-REGMEM8-)
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(values (dpp0 0) (dpp1 1) (dpp2 2) (dpp3 3)
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(psw 136) (cp 8) (mdl 7) (mdh 6)
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(mdc 135) (sp 9) (csp 4) (vecseg 137)
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@ -388,8 +391,7 @@
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(define-keyword
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(name regdiv8-names)
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(print-name h-regdiv8)
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(prefix "")
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(enum-prefix H-REGDIV8-)
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(values (r0 0) (r1 17) (r2 34) (r3 51) (r4 68) (r5 85) (r6 102) (r7 119)
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(r8 136) (r9 153) (r10 170) (r11 187) (r12 204) (r13 221) (r14 238) (r15 255))
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)
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@ -404,8 +406,7 @@
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(define-keyword
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(name reg0-name)
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(print-name h-reg0)
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(prefix "")
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(enum-prefix H-REG0-)
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(values (0x1 1) (0x2 2) (0x3 3) (0x4 4) (0x5 5) (0x6 6) (0x7 7) (0x8 8) (0x9 9) (0xa 10) (0xb 11)
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(0xc 12) (0xd 13) (0xe 14) (0xf 15)
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("1" 1) ("2" 2) ("3" 3) ("4" 4) ("5" 5) ("6" 6) ("7" 7) ("8" 8) ("9" 9) ("10" 10) ("11" 11)
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@ -422,8 +423,7 @@
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(define-keyword
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(name reg0-name1)
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(print-name h-reg01)
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(prefix "")
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(enum-prefix H-REG01-)
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(values (0x1 1) (0x2 2) (0x3 3) (0x4 4) (0x5 5) (0x6 6) (0x7 7)
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("1" 1) ("2" 2) ("3" 3) ("4" 4) ("5" 5) ("6" 6) ("7" 7))
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)
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@ -438,8 +438,7 @@
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(define-keyword
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(name regbmem8-names)
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(print-name h-regbmem8)
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(prefix "")
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(enum-prefix H-REGBMEM8-)
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(values (dpp0 0) (dpp1 1) (dpp2 2) (dpp3 3)
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(psw 136) (cp 8) (mdl 7) (mdh 6)
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(mdc 135) (sp 9) (csp 4) (vecseg 137)
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|
@ -459,8 +458,7 @@
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(define-keyword
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(name memgr8-names)
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(print-name h-memgr8)
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(prefix "")
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(enum-prefix H-MEMGR8-)
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(values (dpp0 65024) (dpp1 65026) (dpp2 65028) (dpp3 65030)
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(psw 65296) (cp 65040) (mdl 65038) (mdh 65036)
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(mdc 65294) (sp 65042) (csp 65032) (vecseg 65298)
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|
@ -1107,7 +1105,7 @@
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((PIPE OS) (IDOC ALU))
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"mul $src1,$src2"
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(+ OP1_0 OP2_11 src1 src2)
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(reg SI h-md 0)
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(nop) ;; FIXME: (reg SI h-md 0)
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()
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)
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; MULU Rwn,Rwm
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|
@ -1115,7 +1113,7 @@
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((PIPE OS) (IDOC ALU))
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"mulu $src1,$src2"
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(+ OP1_1 OP2_11 src1 src2)
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(reg SI h-md 0)
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(nop) ;; FIXME: (reg SI h-md 0)
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()
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)
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; DIV Rwn
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|
@ -1135,8 +1133,8 @@
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"divl $srdiv"
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(+ OP1_6 OP2_11 srdiv )
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(sequence ()
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(set HI (reg HI h-cr 6) (div SI (reg SI h-md 0) srdiv))
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(set HI (reg HI h-cr 7) (mod SI (reg SI h-md 0) srdiv))
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(set HI (reg HI h-cr 6) 0) ;; FIXME: (div SI (reg SI h-md 0) srdiv))
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(set HI (reg HI h-cr 7) 0) ;; FIXME: (mod SI (reg SI h-md 0) srdiv))
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)
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()
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)
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|
@ -1146,8 +1144,8 @@
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"divlu $srdiv"
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(+ OP1_7 OP2_11 srdiv )
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(sequence ()
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(set HI (reg HI h-cr 6) (udiv SI (reg SI h-md 0) srdiv))
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(set HI (reg HI h-cr 7) (umod SI (reg SI h-md 0) srdiv))
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(set HI (reg HI h-cr 6) 0) ;; FIXME: (udiv SI (reg SI h-md 0) srdiv))
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(set HI (reg HI h-cr 7) 0) ;; FIXME: (umod SI (reg SI h-md 0) srdiv))
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)
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||||
()
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||||
)
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|
@ -1841,14 +1839,14 @@
|
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(sequence ((HI tmp1) (HI tmp2))
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||||
(set tmp1 (mem HI caddr))
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||||
(set tmp2 (sub HI pc (mem HI caddr)))
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||||
(if (gt tmp2 (const 0)) (lt tmp2 (const 32)) (eq tmp2 (const 32))
|
||||
(if (gt tmp2 (const 0)) ;; FIXME: (lt tmp2 (const 32)) (eq tmp2 (const 32))
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(set bitone (const 1)))
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||||
(if (lt tmp2 (const 0)) (eq tmp2 (const 0)) (gt tmp2 (const 32))
|
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(if (lt tmp2 (const 0)) ;; FIXME: (eq tmp2 (const 0)) (gt tmp2 (const 32))
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(set bitone (const 0)))
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(if (eq extcond (const 1) (ne extcond cc_Z))
|
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(if (eq extcond (const 1)) ;; FIXME: (ne extcond cc_Z))
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(set bit01 (const 0))
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||||
(set HI pc (mem HI caddr)))
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(if (ne extcond (const 1) (eq extcond cc_Z))
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(if (ne extcond (const 1)) ;; FIXME: (eq extcond cc_Z))
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(set bit01 (const 1))
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||||
(set HI pc (add HI pc (const 2))))
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||||
)
|
||||
|
@ -1867,9 +1865,9 @@
|
|||
(sequence ((HI tmp1) (HI tmp2))
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||||
(set tmp1 (mem HI caddr))
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||||
(set tmp2 (sub HI pc (mem HI caddr)))
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||||
(if (gt tmp2 (const 0)) (lt tmp2 (const 32)) (eq tmp2 (const 32))
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||||
(if (gt tmp2 (const 0)) ;; FIXME: (lt tmp2 (const 32)) (eq tmp2 (const 32))
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(set bitone (const 1)))
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(if (lt tmp2 (const 0)) (eq tmp2 (const 0)) (gt tmp2 (const 32))
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(if (lt tmp2 (const 0)) ;; FIXME: (eq tmp2 (const 0)) (gt tmp2 (const 32))
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(set bitone (const 0)))
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(set HI pc (add HI pc (const 2)))
|
||||
)
|
||||
|
@ -1900,9 +1898,9 @@
|
|||
(sequence ()
|
||||
(if QI (lt QI rel (const 0))
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||||
(sequence ()
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||||
(neg QI rel)
|
||||
(add QI rel (const 1))
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||||
(mul QI rel (const 2))
|
||||
;; FIXME: (neg QI rel)
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||||
;; FIXME: (add QI rel (const 1))
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||||
;; FIXME: (mul QI rel (const 2))
|
||||
(set HI pc (sub HI pc rel))
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||||
))
|
||||
(set HI pc (add HI pc (mul QI rel (const 2))))
|
||||
|
@ -2004,8 +2002,8 @@
|
|||
(if QI (lt QI relhi (const 0))
|
||||
(set tmp2 (const 1))
|
||||
(set tmp1 genreg)
|
||||
(sll tmp2 qlobit)
|
||||
(inv tmp2)
|
||||
;; FIXME: (sll tmp2 qlobit)
|
||||
;; FIXME: (inv tmp2)
|
||||
(set HI tmp1(and tmp1 tmp2))
|
||||
(set HI genreg tmp1)
|
||||
(set HI pc (add HI pc (mul QI relhi (const 2)))))
|
||||
|
@ -2052,7 +2050,7 @@
|
|||
(if QI (lt QI relhi (const 0))
|
||||
(set tmp2 (const 1))
|
||||
(set tmp1 reg8)
|
||||
(sll tmp2 qbit)
|
||||
;; FIXME: (sll tmp2 qbit)
|
||||
(set BI tmp1(or tmp1 tmp2))
|
||||
(set HI reg8 tmp1)
|
||||
(set HI pc (add HI pc (mul QI relhi (const 2)))))
|
||||
|
@ -2131,9 +2129,9 @@
|
|||
(sequence ()
|
||||
(if QI (lt QI rel (const 0))
|
||||
(sequence ()
|
||||
(neg QI rel)
|
||||
(add QI rel (const 1))
|
||||
(mul QI rel (const 2))
|
||||
;; FIXME: (neg QI rel)
|
||||
;; FIXME: (add QI rel (const 1))
|
||||
;; FIXME: (mul QI rel (const 2))
|
||||
(set HI pc (sub HI pc rel))
|
||||
))
|
||||
(set HI pc (add HI pc (mul QI rel (const 2))))
|
||||
|
@ -2319,7 +2317,7 @@
|
|||
(sequence ((HI tmp1) (HI tmp2))
|
||||
(set HI tmp1 reg8)
|
||||
(set HI tmp2 uimm16)
|
||||
(sub HI (reg HI h-cr 9) (const 2))
|
||||
;; FIXME: (sub HI (reg HI h-cr 9) (const 2))
|
||||
(set HI (reg HI h-cr 9) tmp1)
|
||||
(set HI reg8 tmp2)
|
||||
)
|
||||
|
@ -2343,7 +2341,7 @@
|
|||
(sequence ((HI tmp1) (HI tmp2))
|
||||
(set HI tmp1 regmem8)
|
||||
(set HI tmp2 memgr8)
|
||||
(sub HI (reg HI h-cr 9) (const 2))
|
||||
;; FIXME: (sub HI (reg HI h-cr 9) (const 2))
|
||||
(set HI (reg HI h-cr 9) tmp1)
|
||||
(set HI regmem8 tmp2)
|
||||
)
|
||||
|
@ -2358,7 +2356,7 @@
|
|||
(sequence ((HI tmp1) (HI tmp2))
|
||||
(set HI tmp1 reg8)
|
||||
(set HI tmp2 memory)
|
||||
(sub HI (reg HI h-cr 9) (const 2))
|
||||
;; FIXME: (sub HI (reg HI h-cr 9) (const 2))
|
||||
(set HI (reg HI h-cr 9) tmp1)
|
||||
(set HI reg8 tmp2)
|
||||
)
|
||||
|
@ -2659,8 +2657,8 @@
|
|||
(sequence ((HI tmp1) (HI tmp2))
|
||||
(set tmp2 (const 1))
|
||||
(set tmp1 reg8)
|
||||
(sll tmp2 qbit)
|
||||
(inv tmp2)
|
||||
;; FIXME: (sll tmp2 qbit)
|
||||
;; FIXME: (inv tmp2)
|
||||
(set BI tmp1(and tmp1 tmp2))
|
||||
(set HI reg8 tmp1))
|
||||
()
|
||||
|
@ -2675,8 +2673,8 @@
|
|||
(sequence ((HI tmp1) (HI tmp2))
|
||||
(set tmp2 (const 1))
|
||||
(set tmp1 reg8)
|
||||
(sll tmp2 qbit)
|
||||
(inv tmp2)
|
||||
;; FIXME: (sll tmp2 qbit)
|
||||
;; FIXME: (inv tmp2)
|
||||
(set BI tmp1(and tmp1 tmp2))
|
||||
(set HI reg8 tmp1))
|
||||
()
|
||||
|
@ -2708,7 +2706,7 @@
|
|||
(sequence ((HI tmp1) (HI tmp2))
|
||||
(set tmp2 (const 1))
|
||||
(set tmp1 reg8)
|
||||
(sll tmp2 qbit)
|
||||
;; FIXME: (sll tmp2 qbit)
|
||||
(set BI tmp1(or tmp1 tmp2))
|
||||
(set HI reg8 tmp1))
|
||||
()
|
||||
|
@ -2724,7 +2722,7 @@
|
|||
(sequence ((HI tmp1) (HI tmp2))
|
||||
(set tmp2 (const 1))
|
||||
(set tmp1 reg8)
|
||||
(sll tmp2 qbit)
|
||||
;; FIXME: (sll tmp2 qbit)
|
||||
(set BI tmp1(or tmp1 tmp2))
|
||||
(set HI reg8 tmp1))
|
||||
()
|
||||
|
@ -2760,10 +2758,10 @@
|
|||
(set HI tmp2 reg8)
|
||||
(set tmp3 (const 1))
|
||||
(set tmp4 (const 1))
|
||||
(sll tmp3 qlobit)
|
||||
(sll tmp4 qhibit)
|
||||
(and tmp1 tmp3)
|
||||
(and tmp2 tmp4)
|
||||
;; FIXME: (sll tmp3 qlobit)
|
||||
;; FIXME: (sll tmp4 qhibit)
|
||||
;; FIXME: (and tmp1 tmp3)
|
||||
;; FIXME: (and tmp2 tmp4)
|
||||
(set BI tmp1 tmp2)
|
||||
(set HI reghi8 tmp1)
|
||||
(set HI reg8 tmp2))
|
||||
|
@ -2781,11 +2779,11 @@
|
|||
(set HI tmp2 reg8)
|
||||
(set tmp3 (const 1))
|
||||
(set tmp4 (const 1))
|
||||
(sll tmp3 qlobit)
|
||||
(sll tmp4 qhibit)
|
||||
(and tmp1 tmp3)
|
||||
(and tmp2 tmp4)
|
||||
(inv HI tmp2)
|
||||
;; FIXME: (sll tmp3 qlobit)
|
||||
;; FIXME: (sll tmp4 qhibit)
|
||||
;; FIXME: (and tmp1 tmp3)
|
||||
;; FIXME: (and tmp2 tmp4)
|
||||
;; FIXME: (inv HI tmp2)
|
||||
(set BI tmp1 tmp2)
|
||||
(set HI reghi8 tmp1)
|
||||
(set HI reg8 tmp2))
|
||||
|
@ -2803,10 +2801,10 @@
|
|||
(set HI tmp2 reg8)
|
||||
(set tmp3 (const 1))
|
||||
(set tmp4 (const 1))
|
||||
(sll tmp3 qlobit)
|
||||
(sll tmp4 qhibit)
|
||||
(and tmp1 tmp3)
|
||||
(and tmp2 tmp4)
|
||||
;; FIXME: (sll tmp3 qlobit)
|
||||
;; FIXME: (sll tmp4 qhibit)
|
||||
;; FIXME: (and tmp1 tmp3)
|
||||
;; FIXME: (and tmp2 tmp4)
|
||||
(set BI tmp1(and tmp1 tmp2))
|
||||
(set HI reghi8 tmp1)
|
||||
(set HI reg8 tmp2))
|
||||
|
@ -2824,10 +2822,10 @@
|
|||
(set HI tmp2 reg8)
|
||||
(set tmp3 (const 1))
|
||||
(set tmp4 (const 1))
|
||||
(sll tmp3 qlobit)
|
||||
(sll tmp4 qhibit)
|
||||
(and tmp1 tmp3)
|
||||
(and tmp2 tmp4)
|
||||
;; FIXME: (sll tmp3 qlobit)
|
||||
;; FIXME: (sll tmp4 qhibit)
|
||||
;; FIXME: (and tmp1 tmp3)
|
||||
;; FIXME: (and tmp2 tmp4)
|
||||
(set BI tmp1(or tmp1 tmp2))
|
||||
(set HI reghi8 tmp1)
|
||||
(set HI reg8 tmp2))
|
||||
|
@ -2845,10 +2843,10 @@
|
|||
(set HI tmp2 reg8)
|
||||
(set tmp3 (const 1))
|
||||
(set tmp4 (const 1))
|
||||
(sll tmp3 qlobit)
|
||||
(sll tmp4 qhibit)
|
||||
(and tmp1 tmp3)
|
||||
(and tmp2 tmp4)
|
||||
;; FIXME: (sll tmp3 qlobit)
|
||||
;; FIXME: (sll tmp4 qhibit)
|
||||
;; FIXME: (and tmp1 tmp3)
|
||||
;; FIXME: (and tmp2 tmp4)
|
||||
(set BI tmp1(xor tmp1 tmp2))
|
||||
(set HI reghi8 tmp1)
|
||||
(set HI reg8 tmp2))
|
||||
|
@ -2866,10 +2864,10 @@
|
|||
(set HI tmp2 reg8)
|
||||
(set tmp3 (const 1))
|
||||
(set tmp4 (const 1))
|
||||
(sll tmp3 qlobit)
|
||||
(sll tmp4 qhibit)
|
||||
(and tmp1 tmp3)
|
||||
(and tmp2 tmp4)
|
||||
;; FIXME: (sll tmp3 qlobit)
|
||||
;; FIXME: (sll tmp4 qhibit)
|
||||
;; FIXME: (and tmp1 tmp3)
|
||||
;; FIXME: (and tmp2 tmp4)
|
||||
(set BI tmp1(xor tmp1 tmp2))
|
||||
(set HI reghi8 tmp1)
|
||||
(set HI reg8 tmp2))
|
||||
|
@ -2886,7 +2884,7 @@
|
|||
(set HI tmp1 reg8)
|
||||
(set QI tmp2 mask8)
|
||||
(set QI tmp3 datahi8)
|
||||
(inv QI tmp2)
|
||||
;; FIXME: (inv QI tmp2)
|
||||
(set HI tmp1 (and tmp1 tmp2))
|
||||
(set HI tmp1 (or tmp1 tmp3))
|
||||
(set HI reg8 tmp1)
|
||||
|
@ -2904,9 +2902,9 @@
|
|||
(set HI tmp1 reg8)
|
||||
(set QI tmp2 masklo8)
|
||||
(set HI tmp3 data8)
|
||||
(sll tmp2 (const 8))
|
||||
(inv HI tmp2)
|
||||
(sll tmp3 (const 8))
|
||||
;; FIXME: (sll tmp2 (const 8))
|
||||
;; FIXME: (inv HI tmp2)
|
||||
;; FIXME: (sll tmp3 (const 8))
|
||||
(set HI tmp1 (and tmp1 tmp2))
|
||||
(set HI tmp1 (or tmp1 tmp3))
|
||||
(set HI reg8 tmp1)
|
||||
|
|
Loading…
Reference in New Issue