[ARC] Add checking for LP_COUNT reg usage, improve error reporting.
gas/ 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (find_opcode_match): New function argument errmsg. (assemble_tokens): Collect and report the eventual error message found during opcode matching process. * testsuite/gas/arc/lpcount-err.s: New file. * testsuite/gas/arc/add_s-err.s: Update error message. opcode/ 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (insert_ra_chk): New function. (insert_rb_chk): Likewise. (insert_rad): Update text error message. (insert_rcd): Likewise. (insert_rhv2): Likewise. (insert_r0): Likewise. (insert_r1): Likewise. (insert_r2): Likewise. (insert_r3): Likewise. (insert_sp): Likewise. (insert_gp): Likewise. (insert_pcl): Likewise. (insert_blink): Likewise. (insert_ilink1): Likewise. (insert_ilink2): Likewise. (insert_ras): Likewise. (insert_rbs): Likewise. (insert_rcs): Likewise. (insert_simm3s): Likewise. (insert_rrange): Likewise. (insert_fpel): Likewise. (insert_blinkel): Likewise. (insert_pcel): Likewise. (insert_nps_3bit_dst): Likewise. (insert_nps_3bit_dst_short): Likewise. (insert_nps_3bit_src2_short): Likewise. (insert_nps_bitop_size_2b): Likewise. (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise. (RA_CHK): Define. (RB): Adjust. (RB_CHK): Define. (RC): Adjust. * arc-dis.c (print_insn_arc): Add LOAD and STORE class. * arc-tbl.h (div, divu): All instructions are DIVREM class. Change first insn argument to check for LP_COUNT usage. (rem): Likewise. (ld, ldd): All instructions are LOAD class. Change first insn argument to check for LP_COUNT usage. (st, std): All instructions are STORE class. (mac, mpy, dmac, mul, dmpy): All instructions are MPY class. Change first insn argument to check for LP_COUNT usage. (mov): All instructions are MOVE class. Change first insn argument to check for LP_COUNT usage. include/ 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (insn_class_t): Add DIVREM, LOAD, MOVE, MPY, STORE instruction classes.
This commit is contained in:
Claudiu Zissulescu
parent
ee881e5d33
commit
abe7c33b45
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@ -1,3 +1,12 @@
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2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
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* config/tc-arc.c (find_opcode_match): New function argument
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errmsg.
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(assemble_tokens): Collect and report the eventual error message
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found during opcode matching process.
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* testsuite/gas/arc/lpcount-err.s: New file.
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* testsuite/gas/arc/add_s-err.s: Update error message.
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2016-11-28 Ramiro Polla <ramiro@hex-rays.com>
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Amit Pawar <amit.pawar@amd.com>
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@ -1710,7 +1710,8 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
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int *pntok,
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struct arc_flags *first_pflag,
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int nflgs,
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int *pcpumatch)
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int *pcpumatch,
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const char **errmsg)
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{
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const struct arc_opcode *opcode;
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struct arc_opcode_hash_entry_iterator iter;
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@ -1765,7 +1766,7 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
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{
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case ARC_OPERAND_ADDRTYPE:
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{
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const char *errmsg = NULL;
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*errmsg = NULL;
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/* Check to be an address type. */
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if (tok[tokidx].X_op != O_addrtype)
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@ -1776,8 +1777,8 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
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address type. */
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gas_assert (operand->insert != NULL);
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(*operand->insert) (0, tok[tokidx].X_add_number,
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&errmsg);
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if (errmsg != NULL)
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errmsg);
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if (*errmsg != NULL)
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goto match_failed;
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}
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break;
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@ -1803,11 +1804,11 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
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/* Special handling? */
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if (operand->insert)
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{
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const char *errmsg = NULL;
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*errmsg = NULL;
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(*operand->insert)(0,
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regno (tok[tokidx].X_add_number),
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&errmsg);
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if (errmsg)
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errmsg);
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if (*errmsg)
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{
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if (operand->flags & ARC_OPERAND_IGNORE)
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{
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@ -1923,11 +1924,11 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
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{
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if (operand->insert)
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{
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const char *errmsg = NULL;
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*errmsg = NULL;
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(*operand->insert)(0,
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tok[tokidx].X_add_number,
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&errmsg);
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if (errmsg)
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errmsg);
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if (*errmsg)
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goto match_failed;
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}
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else if (!(operand->flags & ARC_OPERAND_IGNORE))
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@ -1948,11 +1949,11 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
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regs |= get_register (tok[tokidx].X_op_symbol);
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if (operand->insert)
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{
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const char *errmsg = NULL;
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*errmsg = NULL;
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(*operand->insert)(0,
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regs,
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&errmsg);
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if (errmsg)
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errmsg);
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if (*errmsg)
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goto match_failed;
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}
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else
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@ -2326,6 +2327,7 @@ assemble_tokens (const char *opname,
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bfd_boolean found_something = FALSE;
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const struct arc_opcode_hash_entry *entry;
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int cpumatch = 1;
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const char *errmsg = NULL;
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/* Search opcodes. */
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entry = arc_find_opcode (opname);
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@ -2342,7 +2344,7 @@ assemble_tokens (const char *opname,
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frag_now->fr_file, frag_now->fr_line, opname);
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found_something = TRUE;
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opcode = find_opcode_match (entry, tok, &ntok, pflags,
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nflgs, &cpumatch);
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nflgs, &cpumatch, &errmsg);
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if (opcode != NULL)
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{
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struct arc_insn insn;
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@ -2356,7 +2358,10 @@ assemble_tokens (const char *opname,
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if (found_something)
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{
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if (cpumatch)
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as_bad (_("inappropriate arguments for opcode '%s'"), opname);
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if (errmsg)
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as_bad (_("%s for instruction '%s'"), errmsg, opname);
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else
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as_bad (_("inappropriate arguments for opcode '%s'"), opname);
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else
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as_bad (_("opcode '%s' not supported for target %s"), opname,
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selected_cpu.name);
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@ -4,7 +4,7 @@
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; { dg-do assemble { target arc*-*-* } }
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; { dg-options "--mcpu=arc700" }
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;; The following insns are accepted by ARCv2 only
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add_s r4,r4,-1 ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" }
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add_s r4,r4,-1 ; { dg-error "Error: Register must be either r0-r3 or r12-r15 for instruction." }
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add_s 0,0xAAAA5555,-1 ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" }
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add_s r0,r15,0x20 ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" }
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add_s r1,r15,0x20 ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" }
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@ -0,0 +1,9 @@
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;; LP_COUNT register cannot be used with multi-cycle instructions such as:
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;; load, lr, multiply and divide.
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; { dg-do assemble { target arc*-*-* } }
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.cpu HS
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mpy lp_count,r0,r1 ; { dg-error "Error: LP_COUNT register cannot be used as destination register." }
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ld lp_count,[r2,1] ; { dg-error "Error: LP_COUNT register cannot be used as destination register." }
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div lp_count,r12,r1 ; { dg-error "Error: LP_COUNT register cannot be used as destination register." }
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@ -1,3 +1,8 @@
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2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
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* opcode/arc.h (insn_class_t): Add DIVREM, LOAD, MOVE, MPY, STORE
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instruction classes.
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2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
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* opcode/sparc.h (sparc_opcode_arch): New fields hwcaps and
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@ -47,17 +47,22 @@ typedef enum
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BMU,
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BRANCH,
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CONTROL,
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DIVREM,
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DPI,
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DSP,
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FLOAT,
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INVALID,
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JUMP,
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KERNEL,
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LOAD,
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LOGICAL,
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MEMORY,
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MOVE,
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MPY,
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NET,
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PROTOCOL_DECODE,
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PMU,
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STORE,
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XY
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} insn_class_t;
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@ -1,3 +1,49 @@
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2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
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* arc-opc.c (insert_ra_chk): New function.
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(insert_rb_chk): Likewise.
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(insert_rad): Update text error message.
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(insert_rcd): Likewise.
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(insert_rhv2): Likewise.
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(insert_r0): Likewise.
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(insert_r1): Likewise.
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(insert_r2): Likewise.
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(insert_r3): Likewise.
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(insert_sp): Likewise.
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(insert_gp): Likewise.
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(insert_pcl): Likewise.
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(insert_blink): Likewise.
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(insert_ilink1): Likewise.
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(insert_ilink2): Likewise.
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(insert_ras): Likewise.
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(insert_rbs): Likewise.
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(insert_rcs): Likewise.
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(insert_simm3s): Likewise.
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(insert_rrange): Likewise.
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(insert_fpel): Likewise.
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(insert_blinkel): Likewise.
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(insert_pcel): Likewise.
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(insert_nps_3bit_dst): Likewise.
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(insert_nps_3bit_dst_short): Likewise.
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(insert_nps_3bit_src2_short): Likewise.
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(insert_nps_bitop_size_2b): Likewise.
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(MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
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(RA_CHK): Define.
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(RB): Adjust.
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(RB_CHK): Define.
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(RC): Adjust.
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* arc-dis.c (print_insn_arc): Add LOAD and STORE class.
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* arc-tbl.h (div, divu): All instructions are DIVREM class.
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Change first insn argument to check for LP_COUNT usage.
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(rem): Likewise.
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(ld, ldd): All instructions are LOAD class. Change first insn
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argument to check for LP_COUNT usage.
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(st, std): All instructions are STORE class.
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(mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
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Change first insn argument to check for LP_COUNT usage.
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(mov): All instructions are MOVE class. Change first insn
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argument to check for LP_COUNT usage.
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2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
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* arc-dis.c (is_compatible_p): Remove function.
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@ -750,8 +750,10 @@ arc_opcode_to_insn_type (const struct arc_opcode *opcode)
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insn_type = dis_branch;
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}
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break;
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case LOAD:
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case STORE:
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case MEMORY:
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insn_type = dis_dref; /* FIXME! DB indicates mov as memory! */
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insn_type = dis_dref;
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break;
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default:
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insn_type = dis_nonbranch;
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@ -30,6 +30,17 @@
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instructions. All NPS400 features are built into all ARC target builds as
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this reduces the chances that regressions might creep in. */
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/* Insert RA register into a 32-bit opcode, with checks. */
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static unsigned long long
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insert_ra_chk (unsigned long long insn,
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long long int value,
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const char **errmsg ATTRIBUTE_UNUSED)
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{
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if (value == 60)
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*errmsg = _("LP_COUNT register cannot be used as destination register");
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return insn | (value & 0x3F);
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}
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/* Insert RB register into a 32-bit opcode. */
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static unsigned long long
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insert_rb (unsigned long long insn,
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@ -39,6 +50,18 @@ insert_rb (unsigned long long insn,
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return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
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}
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/* Insert RB register with checks. */
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static unsigned long long
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insert_rb_chk (unsigned long long insn,
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long long int value,
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const char **errmsg ATTRIBUTE_UNUSED)
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{
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if (value == 60)
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*errmsg = _("LP_COUNT register cannot be used as destination register");
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return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
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}
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static long long int
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extract_rb (unsigned long long insn ATTRIBUTE_UNUSED,
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bfd_boolean * invalid ATTRIBUTE_UNUSED)
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@ -58,7 +81,9 @@ insert_rad (unsigned long long insn,
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const char **errmsg ATTRIBUTE_UNUSED)
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{
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if (value & 0x01)
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*errmsg = _("Improper register value.");
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*errmsg = _("cannot use odd number destination register");
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if (value == 60)
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*errmsg = _("LP_COUNT register cannot be used as destination register");
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return insn | (value & 0x3F);
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}
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@ -69,7 +94,7 @@ insert_rcd (unsigned long long insn,
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const char **errmsg ATTRIBUTE_UNUSED)
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{
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if (value & 0x01)
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*errmsg = _("Improper register value.");
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*errmsg = _("cannot use odd number source register");
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return insn | ((value & 0x3F) << 6);
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}
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@ -142,7 +167,7 @@ insert_rhv2 (unsigned long long insn,
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{
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if (value == 0x1E)
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*errmsg =
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_("Register R30 is a limm indicator for this type of instruction.");
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_("Register R30 is a limm indicator");
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return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03);
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}
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@ -161,7 +186,7 @@ insert_r0 (unsigned long long insn,
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const char **errmsg ATTRIBUTE_UNUSED)
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{
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if (value != 0)
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*errmsg = _("Register must be R0.");
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*errmsg = _("Register must be R0");
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return insn;
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}
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@ -179,7 +204,7 @@ insert_r1 (unsigned long long insn,
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const char **errmsg ATTRIBUTE_UNUSED)
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{
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if (value != 1)
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*errmsg = _("Register must be R1.");
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*errmsg = _("Register must be R1");
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return insn;
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}
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@ -196,7 +221,7 @@ insert_r2 (unsigned long long insn,
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const char **errmsg ATTRIBUTE_UNUSED)
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{
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if (value != 2)
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*errmsg = _("Register must be R2.");
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*errmsg = _("Register must be R2");
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return insn;
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}
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@ -213,7 +238,7 @@ insert_r3 (unsigned long long insn,
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const char **errmsg ATTRIBUTE_UNUSED)
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{
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if (value != 3)
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*errmsg = _("Register must be R3.");
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*errmsg = _("Register must be R3");
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return insn;
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}
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@ -230,7 +255,7 @@ insert_sp (unsigned long long insn,
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const char **errmsg ATTRIBUTE_UNUSED)
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{
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if (value != 28)
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*errmsg = _("Register must be SP.");
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*errmsg = _("Register must be SP");
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return insn;
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}
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@ -247,7 +272,7 @@ insert_gp (unsigned long long insn,
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const char **errmsg ATTRIBUTE_UNUSED)
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{
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if (value != 26)
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*errmsg = _("Register must be GP.");
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*errmsg = _("Register must be GP");
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return insn;
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}
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@ -264,7 +289,7 @@ insert_pcl (unsigned long long insn,
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const char **errmsg ATTRIBUTE_UNUSED)
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{
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if (value != 63)
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*errmsg = _("Register must be PCL.");
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*errmsg = _("Register must be PCL");
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return insn;
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}
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@ -281,7 +306,7 @@ insert_blink (unsigned long long insn,
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const char **errmsg ATTRIBUTE_UNUSED)
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{
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if (value != 31)
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*errmsg = _("Register must be BLINK.");
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*errmsg = _("Register must be BLINK");
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return insn;
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}
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@ -298,7 +323,7 @@ insert_ilink1 (unsigned long long insn,
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const char **errmsg ATTRIBUTE_UNUSED)
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{
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if (value != 29)
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*errmsg = _("Register must be ILINK1.");
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*errmsg = _("Register must be ILINK1");
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return insn;
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}
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@ -315,7 +340,7 @@ insert_ilink2 (unsigned long long insn,
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const char **errmsg ATTRIBUTE_UNUSED)
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{
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if (value != 30)
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*errmsg = _("Register must be ILINK2.");
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*errmsg = _("Register must be ILINK2");
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return insn;
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}
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@ -346,7 +371,7 @@ insert_ras (unsigned long long insn,
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insn |= (value - 8);
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break;
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default:
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*errmsg = _("Register must be either r0-r3 or r12-r15.");
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*errmsg = _("Register must be either r0-r3 or r12-r15");
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break;
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}
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return insn;
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@ -383,7 +408,7 @@ insert_rbs (unsigned long long insn,
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insn |= ((value - 8)) << 8;
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break;
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default:
|
||||
*errmsg = _("Register must be either r0-r3 or r12-r15.");
|
||||
*errmsg = _("Register must be either r0-r3 or r12-r15");
|
||||
break;
|
||||
}
|
||||
return insn;
|
||||
|
|
@ -420,7 +445,7 @@ insert_rcs (unsigned long long insn,
|
|||
insn |= ((value - 8)) << 5;
|
||||
break;
|
||||
default:
|
||||
*errmsg = _("Register must be either r0-r3 or r12-r15.");
|
||||
*errmsg = _("Register must be either r0-r3 or r12-r15");
|
||||
break;
|
||||
}
|
||||
return insn;
|
||||
|
|
@ -470,7 +495,7 @@ insert_simm3s (unsigned long long insn,
|
|||
tmp = 0x06;
|
||||
break;
|
||||
default:
|
||||
*errmsg = _("Accepted values are from -1 to 6.");
|
||||
*errmsg = _("Accepted values are from -1 to 6");
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -498,12 +523,12 @@ insert_rrange (unsigned long long insn,
|
|||
int reg2 = value & 0xFFFF;
|
||||
if (reg1 != 13)
|
||||
{
|
||||
*errmsg = _("First register of the range should be r13.");
|
||||
*errmsg = _("First register of the range should be r13");
|
||||
return insn;
|
||||
}
|
||||
if (reg2 < 13 || reg2 > 26)
|
||||
{
|
||||
*errmsg = _("Last register of the range doesn't fit.");
|
||||
*errmsg = _("Last register of the range doesn't fit");
|
||||
return insn;
|
||||
}
|
||||
insn |= ((reg2 - 12) & 0x0F) << 1;
|
||||
|
|
@ -524,7 +549,7 @@ insert_fpel (unsigned long long insn,
|
|||
{
|
||||
if (value != 27)
|
||||
{
|
||||
*errmsg = _("Invalid register number, should be fp.");
|
||||
*errmsg = _("Invalid register number, should be fp");
|
||||
return insn;
|
||||
}
|
||||
|
||||
|
|
@ -546,7 +571,7 @@ insert_blinkel (unsigned long long insn,
|
|||
{
|
||||
if (value != 31)
|
||||
{
|
||||
*errmsg = _("Invalid register number, should be blink.");
|
||||
*errmsg = _("Invalid register number, should be blink");
|
||||
return insn;
|
||||
}
|
||||
|
||||
|
|
@ -568,7 +593,7 @@ insert_pclel (unsigned long long insn,
|
|||
{
|
||||
if (value != 63)
|
||||
{
|
||||
*errmsg = _("Invalid register number, should be pcl.");
|
||||
*errmsg = _("Invalid register number, should be pcl");
|
||||
return insn;
|
||||
}
|
||||
|
||||
|
|
@ -664,7 +689,7 @@ insert_nps_3bit_reg_at_##OFFSET##_##NAME \
|
|||
insn |= (value - 8) << (OFFSET); \
|
||||
break; \
|
||||
default: \
|
||||
*errmsg = _("Register must be either r0-r3 or r12-r15."); \
|
||||
*errmsg = _("Register must be either r0-r3 or r12-r15"); \
|
||||
break; \
|
||||
} \
|
||||
return insn; \
|
||||
|
|
@ -712,7 +737,7 @@ insert_nps_bitop_size_2b (unsigned long long insn ATTRIBUTE_UNUSED,
|
|||
break;
|
||||
default:
|
||||
value = 0;
|
||||
*errmsg = _("Invalid size, should be 1, 2, 4, or 8.");
|
||||
*errmsg = _("Invalid size, should be 1, 2, 4, or 8");
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -822,7 +847,7 @@ insert_nps_##NAME##_pos (unsigned long long insn ATTRIBUTE_UNUSED, \
|
|||
value = value / 8; \
|
||||
break; \
|
||||
default: \
|
||||
*errmsg = _("Invalid position, should be 0, 8, 16, or 24."); \
|
||||
*errmsg = _("Invalid position, should be 0, 8, 16, or 24"); \
|
||||
value = 0; \
|
||||
} \
|
||||
insn |= (value << SHIFT); \
|
||||
|
|
@ -1529,9 +1554,13 @@ const struct arc_operand arc_operands[] =
|
|||
instructions. */
|
||||
#define RA (IGNORED + 1)
|
||||
{ 6, 0, 0, ARC_OPERAND_IR, 0, 0 },
|
||||
#define RB (RA + 1)
|
||||
#define RA_CHK (RA + 1)
|
||||
{ 6, 0, 0, ARC_OPERAND_IR, insert_ra_chk, 0 },
|
||||
#define RB (RA_CHK + 1)
|
||||
{ 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb },
|
||||
#define RC (RB + 1)
|
||||
#define RB_CHK (RB + 1)
|
||||
{ 6, 12, 0, ARC_OPERAND_IR, insert_rb_chk, extract_rb },
|
||||
#define RC (RB_CHK + 1)
|
||||
{ 6, 6, 0, ARC_OPERAND_IR, 0, 0 },
|
||||
#define RBdup (RC + 1)
|
||||
{ 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb },
|
||||
|
|
|
|||
4472
opcodes/arc-tbl.h
4472
opcodes/arc-tbl.h
File diff suppressed because it is too large
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Reference in New Issue