* gas/arm/arch7.s: Fix typo basepri_max should be basepri_mask.
* gas/arm/mrs-msr-thumb-v7e-m.s: Likewise. * gas/arm/arch7.d: Update expected disassembly. * gas/arm/attr-march-armv7.d: Remove Microcontroller tag. * gas/arm/blx-bad.d: Only run for ELF based targets. * gas/arm/mrs-msr-thumb-v6t2.d: Likewise. * gas/arm/vldm-arm.d: Likewise. * gas/arm/mrs-msr-thumb-v7-m.d: Likewise. Remove qualifiers from PSR and IAPSR regsiter names. * gas/arm/mrs-msr-thumb-v7e-m.d: Likewise. * gas/arm/thumb2_bcond.d: Update expected disassembly to allow for relaxing of branch insns. * gas/arm/thumb32.d: Fix whitespace problems in disassembly. * config/tc-arm.c (parse_psr): Use selected_cpu not cpu_variant to detect M-profile targets. (do_t_swi): Exclude v7 and higher variants from arm_ext_os test. (v7m_psrs): Fix typo: basepri_max should be basepri_mask. * arm-dis.c (psr_name): Revert previous delta. * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
This commit is contained in:
Nick Clifton
parent
1448a0a258
commit
ac7f631be1
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@ -1,3 +1,11 @@
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2011-04-18 Julian Brown <julian@codesourcery.com>
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Nick Clifton <nickc@redhat.com>
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* config/tc-arm.c (parse_psr): Use selected_cpu not cpu_variant to
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detect M-profile targets.
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(do_t_swi): Exclude v7 and higher variants from arm_ext_os test.
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(v7m_psrs): Fix typo: basepri_max should be basepri_mask.
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2011-04-14 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
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* config/tc-s390.c (s390_machine): New prototype.
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@ -5354,7 +5354,7 @@ parse_psr (char **str, bfd_boolean lhs)
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const struct asm_psr *psr;
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char *start;
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bfd_boolean is_apsr = FALSE;
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bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m);
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bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
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/* CPSR's and SPSR's can now be lowercase. This is just a convenience
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feature for ease of use and backwards compatibility. */
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@ -11760,7 +11760,9 @@ do_t_swi (void)
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to ARM_EXT_V6M. */
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if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
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{
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if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os))
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if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
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/* This only applies to the v6m howver, not later architectures. */
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&& ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
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as_bad (_("SVC is not permitted on this architecture"));
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ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
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}
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@ -16632,7 +16634,8 @@ static const struct asm_psr v7m_psrs[] =
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{"psp", 9 }, {"PSP", 9 },
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{"primask", 16}, {"PRIMASK", 16},
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{"basepri", 17}, {"BASEPRI", 17},
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{"basepri_max", 18}, {"BASEPRI_MAX", 18},
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{"basepri_max", 18}, {"BASEPRI_MAX", 18}, /* Typo, preserved for backwards compatibility. */
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{"basepri_mask",18}, {"BASEPRI_MASK", 18},
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{"faultmask", 19}, {"FAULTMASK", 19},
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{"control", 20}, {"CONTROL", 20}
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};
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@ -1,3 +1,19 @@
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2011-04-18 Nick Clifton <nickc@redhat.com>
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* gas/arm/arch7.s: Fix typo basepri_max should be basepri_mask.
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* gas/arm/mrs-msr-thumb-v7e-m.s: Likewise.
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* gas/arm/arch7.d: Update expected disassembly.
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* gas/arm/attr-march-armv7.d: Remove Microcontroller tag.
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* gas/arm/blx-bad.d: Only run for ELF based targets.
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* gas/arm/mrs-msr-thumb-v6t2.d: Likewise.
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* gas/arm/vldm-arm.d: Likewise.
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* gas/arm/mrs-msr-thumb-v7-m.d: Likewise.
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Remove qualifiers from PSR and IAPSR regsiter names.
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* gas/arm/mrs-msr-thumb-v7e-m.d: Likewise.
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* gas/arm/thumb2_bcond.d: Update expected disassembly to allow for
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relaxing of branch insns.
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* gas/arm/thumb32.d: Fix whitespace problems in disassembly.
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2011-04-18 Tristan Gingold <gingold@adacore.com>
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* gas/macros/app1.s: Export symbol
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@ -57,13 +57,13 @@ Disassembly of section .text:
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0+0c0 <[^>]*> f3ef 8009 mrs r0, PSP
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0+0c4 <[^>]*> f3ef 8010 mrs r0, PRIMASK
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0+0c8 <[^>]*> f3ef 8011 mrs r0, BASEPRI
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0+0cc <[^>]*> f3ef 8012 mrs r0, BASEPRI_MAX
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0+0cc <[^>]*> f3ef 8012 mrs r0, BASEPRI_MASK
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0+0d0 <[^>]*> f3ef 8013 mrs r0, FAULTMASK
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0+0d4 <[^>]*> f3ef 8014 mrs r0, CONTROL
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0+0d8 <[^>]*> f380 8800 msr (CPSR_f|APSR_nzcvq), r0
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0+0dc <[^>]*> f380 8801 msr IAPSR_nzcvq, r0
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0+0e0 <[^>]*> f380 8802 msr EAPSR_nzcvq, r0
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0+0e4 <[^>]*> f380 8803 msr PSR_nzcvq, r0
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0+0dc <[^>]*> f380 8801 msr IAPSR, r0
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0+0e0 <[^>]*> f380 8802 msr EAPSR, r0
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0+0e4 <[^>]*> f380 8803 msr PSR, r0
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0+0e8 <[^>]*> f380 8805 msr IPSR, r0
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0+0ec <[^>]*> f380 8806 msr EPSR, r0
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0+0f0 <[^>]*> f380 8807 msr IEPSR, r0
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@ -71,9 +71,10 @@ Disassembly of section .text:
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0+0f8 <[^>]*> f380 8809 msr PSP, r0
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0+0fc <[^>]*> f380 8810 msr PRIMASK, r0
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0+100 <[^>]*> f380 8811 msr BASEPRI, r0
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0+104 <[^>]*> f380 8812 msr BASEPRI_MAX, r0
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0+104 <[^>]*> f380 8812 msr BASEPRI_MASK, r0
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0+108 <[^>]*> f380 8813 msr FAULTMASK, r0
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0+10c <[^>]*> f380 8814 msr CONTROL, r0
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0+110 <[^>]*> f3ef 8003 mrs r0, PSR
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0+114 <[^>]*> f380 8803 msr PSR_nzcvq, r0
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0+114 <[^>]*> f380 8803 msr PSR, r0
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0+118 <[^>]*> df00 svc 0
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#...
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@ -60,7 +60,7 @@ label2:
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mrs r0, psp
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mrs r0, primask
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mrs r0, basepri
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mrs r0, basepri_max
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mrs r0, basepri_mask
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mrs r0, faultmask
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mrs r0, control
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msr apsr_nzcvq, r0
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@ -74,7 +74,7 @@ label2:
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msr psp, r0
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msr primask, r0
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msr basepri, r0
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msr basepri_max, r0
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msr BASEPRI_MASK, r0
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msr faultmask, r0
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msr control, r0
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mrs r0, xpsr
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@ -9,6 +9,5 @@ Attribute Section: aeabi
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File Attributes
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Tag_CPU_name: "7"
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Tag_CPU_arch: v7
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Tag_CPU_arch_profile: Microcontroller
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Tag_THUMB_ISA_use: Thumb-2
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Tag_DIV_use: Not allowed
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@ -1,5 +1,7 @@
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#objdump: -drw --show-raw-insn
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#name: BLX encoding
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# This test is only valid on ELF based ports.
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#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
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.*: file format .*arm.*
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@ -1,5 +1,7 @@
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#objdump: -dr --prefix-addresses --show-raw-insn
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#name: MRS/MSR test, architecture v6t2, Thumb mode
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# This test is only valid on ELF based ports.
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#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
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.*: file format .*
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@ -1,6 +1,7 @@
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#objdump: -dr --prefix-addresses --show-raw-insn
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#name: MRS/MSR test, architecture v7-M, Thumb mode
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# This test is only valid on ELF based ports.
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#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
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.*: file format .*
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@ -9,7 +10,7 @@ Disassembly of section .text:
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0+00 <[^>]*> f3ef 8400 mrs r4, CPSR
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0+04 <[^>]*> f3ef 8502 mrs r5, EAPSR
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0+08 <[^>]*> f3ef 8610 mrs r6, PRIMASK
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0+0c <[^>]*> f383 8803 msr PSR_nzcvq, r3
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0+0c <[^>]*> f383 8803 msr PSR, r3
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0+10 <[^>]*> f384 8800 msr CPSR_f, r4
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0+14 <[^>]*> f385 8801 msr IAPSR_nzcvq, r5
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0+14 <[^>]*> f385 8801 msr IAPSR, r5
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0+18 <[^>]*> f386 8810 msr PRIMASK, r6
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@ -1,5 +1,7 @@
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#objdump: -dr --prefix-addresses --show-raw-insn
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#name: MRS/MSR test, architecture v7e-M, Thumb mode
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# This test is only valid on ELF based ports.
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#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
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.*: file format .*
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@ -9,5 +11,5 @@ Disassembly of section .text:
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0+04 <[^>]*> f3ef 8502 mrs r5, EAPSR
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0+08 <[^>]*> f3ef 8610 mrs r6, PRIMASK
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0+0c <[^>]*> f384 8c00 msr CPSR_fs, r4
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0+10 <[^>]*> f385 8401 msr IAPSR_g, r5
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0+14 <[^>]*> f386 8812 msr BASEPRI_MAX, r6
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0+10 <[^>]*> f385 8401 msr IAPSR, r5
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0+14 <[^>]*> f386 8812 msr BASEPRI_MASK, r6
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@ -7,4 +7,4 @@
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mrs r6, primask
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msr apsr_nzcvqg, r4
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msr iapsr_g, r5
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msr basepri_max, r6
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msr basepri_mask, r6
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@ -4,24 +4,24 @@
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.*: +file format .*arm.*
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Disassembly of section .text:
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0+000 <[^>]+> bf18 it ne
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0+002 <[^>]+> f7ff bffd bne.w 0+0 <[^>]+>
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0+006 <[^>]+> bf38 it cc
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0+008 <[^>]+> f7ff bffa bcc.w 0+0 <[^>]+>
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0+00c <[^>]+> bf28 it cs
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0+00e <[^>]+> f7ff fff7 blcs 0+0 <[^>]+>
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0+012 <[^>]+> bfb8 it lt
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0+014 <[^>]+> 47a8 blxlt r5
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0+016 <[^>]+> bf08 it eq
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0+018 <[^>]+> 4740 bxeq r8
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0+01a <[^>]+> bfc8 it gt
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0+01c <[^>]+> e8d4 f001 tbbgt \[r4, r1\]
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0+020 <[^>]+> bfb8 it lt
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0+022 <[^>]+> df00 svclt 0
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0+024 <[^>]+> bf08 it eq
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0+026 <[^>]+> f8d0 f000 ldreq.w pc, \[r0\]
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0+02a <[^>]+> bfdc itt le
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0+02c <[^>]+> be00 bkpt 0x0000
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0+02e <[^>]+> bf00 nople
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0+030 <[^>]+> bf00 nop
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0+000 <[^>]+> bf18[ ]+it ne
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0+002 <[^>]+> [0-9a-f ]+[ ]+bne.[nw] 0+0 <[^>]+>
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0+00. <[^>]+> bf38[ ]+it cc
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0+00. <[^>]+> f7ff bff[ab][ ]+bcc.w 0+0 <[^>]+>
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0+00. <[^>]+> bf28[ ]+it cs
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0+0.. <[^>]+> f7ff fff[78][ ]+blcs 0+0 <[^>]+>
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0+0.. <[^>]+> bfb8[ ]+it lt
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0+0.. <[^>]+> 47a8[ ]+blxlt r5
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0+0.. <[^>]+> bf08[ ]+it eq
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0+0.. <[^>]+> 4740[ ]+bxeq r8
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0+0.. <[^>]+> bfc8[ ]+it gt
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0+0.. <[^>]+> e8d4 f001[ ]+tbbgt \[r4, r1\]
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0+0.. <[^>]+> bfb8[ ]+it lt
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0+0.. <[^>]+> df00[ ]+svclt 0
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0+0.. <[^>]+> bf08[ ]+it eq
|
||||
0+0.. <[^>]+> f8d0 f000[ ]+ldreq.w pc, \[r0\]
|
||||
0+0.. <[^>]+> bfdc[ ]+itt le
|
||||
0+0.. <[^>]+> be00[ ]+bkpt 0x0000
|
||||
0+0.. <[^>]+> bf00[ ]+nople
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||||
0+0.. <[^>]+> bf00[ ]+nop
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#...
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|
|
|
|||
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|
@ -535,11 +535,11 @@ Disassembly of section .text:
|
|||
0[0-9a-f]+ <[^>]+> e9d5 2300 ldrd r2, r3, \[r5\]
|
||||
0[0-9a-f]+ <[^>]+> e9d5 230c ldrd r2, r3, \[r5, #48\].*
|
||||
0[0-9a-f]+ <[^>]+> e955 230c ldrd r2, r3, \[r5, #-48\].*
|
||||
0[0-9a-f]+ <[^>]+> e95f 4505 ldrd r4, r5, \[pc, #-16\] ; 0+5f0 <^>]+>
|
||||
0[0-9a-f]+ <[^>]+> e95f 4504 ldrd r4, r5, \[pc, #-16\] ; 000005f0 <here>
|
||||
0[0-9a-f]+ <[^>]+> e9c5 2300 strd r2, r3, \[r5\]
|
||||
0[0-9a-f]+ <[^>]+> e9c5 230c strd r2, r3, \[r5, #48\].*
|
||||
0[0-9a-f]+ <[^>]+> e945 230c strd r2, r3, \[r5, #-48\].*
|
||||
0[0-9a-f]+ <[^>]+> e94f 2308 strd r2, r3, \[pc, #-32\] ; 0+5f0 <^>]+>
|
||||
0[0-9a-f]+ <[^>]+> e94f 2308 strd r2, r3, \[pc, #-32\] ; 0+5f0 <here>
|
||||
0[0-9a-f]+ <[^>]+> f815 1e00 ldrbt r1, \[r5\]
|
||||
0[0-9a-f]+ <[^>]+> f815 1e30 ldrbt r1, \[r5, #48\].*
|
||||
0[0-9a-f]+ <[^>]+> f915 1e00 ldrsbt r1, \[r5\]
|
||||
|
|
@ -1065,3 +1065,4 @@ Disassembly of section .text:
|
|||
0[0-9a-f]+ <[^>]+> fa62 f103 ror.w r1, r2, r3
|
||||
0[0-9a-f]+ <[^>]+> fa61 f103 ror.w r1, r1, r3
|
||||
0[0-9a-f]+ <[^>]+> bf00 nop
|
||||
0[0-9a-f]+ <[^>]+> bf00 nop
|
||||
|
|
|
|||
|
|
@ -2,6 +2,8 @@
|
|||
# as: -mfpu=vfp3
|
||||
# source: vldm.s
|
||||
# objdump: -dr --prefix-addresses --show-raw-insn
|
||||
# This test is only valid on ELF based ports.
|
||||
#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
|
||||
|
||||
.*: +file format .*arm.*
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,7 @@
|
|||
2011-04-18 Julian Brown <julian@codesourcery.com>
|
||||
|
||||
* arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
|
||||
|
||||
2011-04-11 Dan McDonald <dan@wellkeeper.com>
|
||||
|
||||
PR gas/12296
|
||||
|
|
|
|||
|
|
@ -109,8 +109,7 @@
|
|||
#define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K)
|
||||
#define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 | ARM_EXT_SEC)
|
||||
#define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_SEC)
|
||||
#define ARM_AEXT_V7_ARM (ARM_AEXT_V6KT2 | ARM_EXT_V7 | ARM_EXT_BARRIER \
|
||||
| ARM_EXT_OS)
|
||||
#define ARM_AEXT_V7_ARM (ARM_AEXT_V6KT2 | ARM_EXT_V7 | ARM_EXT_BARRIER)
|
||||
#define ARM_AEXT_V7A (ARM_AEXT_V7_ARM | ARM_EXT_V7A)
|
||||
#define ARM_AEXT_V7R (ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV)
|
||||
#define ARM_AEXT_NOTM \
|
||||
|
|
|
|||
|
|
@ -1,3 +1,7 @@
|
|||
2011-04-18 Nick Clifton <nickc@redhat.com>
|
||||
|
||||
* arm-dis.c (psr_name): Revert previous delta.
|
||||
|
||||
2011-04-13 Nick Clifton <nickc@redhat.com>
|
||||
|
||||
* v850-dis.c (disassemble): Always print a closing square brace if
|
||||
|
|
|
|||
|
|
@ -3722,7 +3722,7 @@ psr_name (int regno)
|
|||
case 9: return "PSP";
|
||||
case 16: return "PRIMASK";
|
||||
case 17: return "BASEPRI";
|
||||
case 18: return "BASEPRI_MAX";
|
||||
case 18: return "BASEPRI_MASK";
|
||||
case 19: return "FAULTMASK";
|
||||
case 20: return "CONTROL";
|
||||
default: return "<unknown>";
|
||||
|
|
@ -4192,15 +4192,6 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
|
|||
else
|
||||
func (stream, "(UNDEF: %lu)", sysm);
|
||||
}
|
||||
else if ((given & 0xff) <= 3)
|
||||
{
|
||||
func (stream, "%s_", psr_name (given & 0xff));
|
||||
|
||||
if (given & 0x800)
|
||||
func (stream, "nzcvq");
|
||||
if (given & 0x400)
|
||||
func (stream, "g");
|
||||
}
|
||||
else
|
||||
{
|
||||
func (stream, psr_name (given & 0xff));
|
||||
|
|
|
|||
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Reference in New Issue