Implement separate user (SPU) and interrupt (SPI) stack pointers.

This commit is contained in:
Andrew Cagney 1998-02-13 05:22:49 +00:00
parent 93c6a010dc
commit ac9a7d8a2c
3 changed files with 15 additions and 0 deletions

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@ -1,3 +1,11 @@
Fri Feb 13 15:15:58 1998 Andrew Cagney <cagney@b1.cygnus.com>
* simops.c (move_to_cr): Sync regs[SP_IDX] with State.sp according
to PSW:SM.
* d10v_sim.h (struct _state): Add sp, as holding area for SPI/SPU.
(SP_IDX): Define.
Wed Feb 11 16:53:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
* simops.c (OP_5F00): Call error instead of abort for unknown

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@ -75,10 +75,15 @@ enum _ins_type
extern unsigned long ins_type_counters[ (int)INS_MAX ];
enum {
SP_IDX = 15,
};
struct _state
{
reg_t regs[16]; /* general-purpose registers */
reg_t cregs[16]; /* control registers */
reg_t sp[2]; /* holding area for SPI(0)/SPU(1) */
int64 a[2]; /* accumulators */
uint8 SM;
uint8 EA;

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@ -50,6 +50,7 @@ move_to_cr (int cr, reg_t val)
switch (cr)
{
case PSW_CR:
State.sp[State.SM] = State.regs[SP_IDX]; /* save old SP */
State.SM = (val & PSW_SM_BIT) != 0;
State.EA = (val & PSW_EA_BIT) != 0;
State.DB = (val & PSW_DB_BIT) != 0;
@ -62,6 +63,7 @@ move_to_cr (int cr, reg_t val)
State.F0 = (val & PSW_F0_BIT) != 0;
State.F1 = (val & PSW_F1_BIT) != 0;
State.C = (val & PSW_C_BIT) != 0;
State.regs[SP_IDX] = State.sp[State.SM]; /* restore new SP */
if (State.ST && !State.FX)
{
(*d10v_callback->printf_filtered)