[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
This commit is contained in:
Thiemo Seufer
parent
59bc7ed3ce
commit
ad3fea084d
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@ -1,3 +1,33 @@
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2006-05-23 Thiemo Seufer <ths@mips.com>
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David Ung <davidu@mips.com>
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Nigel Stephens <nigel@mips.com>
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[ gas/ChangeLog ]
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* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
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(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
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ISA_HAS_MXHC1): New macros.
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(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
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ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
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(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
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(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
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MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
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(mips_after_parse_args): Change default handling of float register
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size to account for 32bit code with 64bit FP. Better sanity checking
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of ISA/ASE/ABI option combinations.
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(s_mipsset): Support switching of GPR and FPR sizes via
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.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
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options.
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(mips_elf_final_processing): We should record the use of 64bit FP
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registers in 32bit code but we don't, because ELF header flags are
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a scarce ressource.
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(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
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extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
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24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
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(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
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* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
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missing -march options. Document .set arch=CPU. Move .set smartmips
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to ASE page. Use @code for .set FOO examples.
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2006-05-23 Jie Zhang <jie.zhang@analog.com>
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* config/tc-bfin.c (bfin_start_line_hook): Bump line counters
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@ -274,17 +274,23 @@ static int file_ase_mdmx;
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command line (e.g., by -march). */
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static int file_ase_smartmips;
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#define ISA_SUPPORT_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
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|| mips_opts.isa == ISA_MIPS32R2)
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#define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
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|| mips_opts.isa == ISA_MIPS32R2)
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/* True if -mdsp was passed or implied by arguments passed on the
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command line (e.g., by -march). */
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static int file_ase_dsp;
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#define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
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|| mips_opts.isa == ISA_MIPS64R2)
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/* True if -mmt was passed or implied by arguments passed on the
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command line (e.g., by -march). */
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static int file_ase_mt;
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#define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
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|| mips_opts.isa == ISA_MIPS64R2)
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/* The argument of the -march= flag. The architecture we are assembling. */
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static int file_mips_arch = CPU_UNKNOWN;
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static const char *mips_arch_string;
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@ -306,7 +312,7 @@ static int mips_32bitmode = 0;
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|| (ABI) == N64_ABI \
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|| (ABI) == O64_ABI)
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/* Return true if ISA supports 64 bit gp register instructions. */
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/* Return true if ISA supports 64 bit wide gp registers. */
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#define ISA_HAS_64BIT_REGS(ISA) \
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((ISA) == ISA_MIPS3 \
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|| (ISA) == ISA_MIPS4 \
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@ -314,6 +320,15 @@ static int mips_32bitmode = 0;
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|| (ISA) == ISA_MIPS64 \
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|| (ISA) == ISA_MIPS64R2)
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/* Return true if ISA supports 64 bit wide float registers. */
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#define ISA_HAS_64BIT_FPRS(ISA) \
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((ISA) == ISA_MIPS3 \
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|| (ISA) == ISA_MIPS4 \
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|| (ISA) == ISA_MIPS5 \
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|| (ISA) == ISA_MIPS32R2 \
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|| (ISA) == ISA_MIPS64 \
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|| (ISA) == ISA_MIPS64R2)
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/* Return true if ISA supports 64-bit right rotate (dror et al.)
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instructions. */
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#define ISA_HAS_DROR(ISA) \
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@ -333,14 +348,20 @@ static int mips_32bitmode = 0;
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|| (ISA) == ISA_MIPS64 \
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|| (ISA) == ISA_MIPS64R2)
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/* Return true if ISA supports move to/from high part of a 64-bit
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floating-point register. */
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#define ISA_HAS_MXHC1(ISA) \
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((ISA) == ISA_MIPS32R2 \
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|| (ISA) == ISA_MIPS64R2)
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#define HAVE_32BIT_GPRS \
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(mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
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(mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
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#define HAVE_32BIT_FPRS \
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(mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
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(mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
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#define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
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#define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
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#define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
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#define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
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#define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
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@ -1031,11 +1052,18 @@ static int validate_mips_insn (const struct mips_opcode *);
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struct mips_cpu_info
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{
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const char *name; /* CPU or ISA name. */
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int is_isa; /* Is this an ISA? (If 0, a CPU.) */
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int flags; /* ASEs available, or ISA flag. */
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int isa; /* ISA level. */
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int cpu; /* CPU number (default CPU if ISA). */
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};
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#define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
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#define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
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#define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
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#define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
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#define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
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#define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
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static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
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static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
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static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
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@ -11380,14 +11408,43 @@ mips_after_parse_args (void)
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|| !ISA_HAS_64BIT_REGS (mips_opts.isa));
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}
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/* ??? GAS treats single-float processors as though they had 64-bit
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float registers (although it complains when double-precision
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instructions are used). As things stand, saying they have 32-bit
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registers would lead to spurious "register must be even" messages.
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So here we assume float registers are always the same size as
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integer ones, unless the user says otherwise. */
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if (file_mips_fp32 < 0)
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file_mips_fp32 = file_mips_gp32;
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switch (file_mips_fp32)
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{
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default:
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case -1:
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/* No user specified float register size.
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??? GAS treats single-float processors as though they had 64-bit
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float registers (although it complains when double-precision
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instructions are used). As things stand, saying they have 32-bit
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registers would lead to spurious "register must be even" messages.
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So here we assume float registers are never smaller than the
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integer ones. */
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if (file_mips_gp32 == 0)
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/* 64-bit integer registers implies 64-bit float registers. */
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file_mips_fp32 = 0;
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else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
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&& ISA_HAS_64BIT_FPRS (mips_opts.isa))
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/* -mips3d and -mdmx imply 64-bit float registers, if possible. */
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file_mips_fp32 = 0;
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else
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/* 32-bit float registers. */
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file_mips_fp32 = 1;
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break;
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/* The user specified the size of the float registers. Check if it
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agrees with the ABI and ISA. */
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case 0:
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if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
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as_bad (_("-mfp64 used with a 32-bit fpu"));
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else if (ABI_NEEDS_32BIT_REGS (mips_abi)
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&& !ISA_HAS_MXHC1 (mips_opts.isa))
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as_warn (_("-mfp64 used with a 32-bit ABI"));
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break;
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case 1:
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if (ABI_NEEDS_64BIT_REGS (mips_abi))
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as_warn (_("-mfp32 used with a 64-bit ABI"));
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break;
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}
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/* End of GCC-shared inference code. */
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@ -11406,13 +11463,36 @@ mips_after_parse_args (void)
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if (mips_opts.mips16 == -1)
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mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
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if (mips_opts.ase_mips3d == -1)
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mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0;
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mips_opts.ase_mips3d = ((CPU_HAS_MIPS3D (file_mips_arch)
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|| (arch_info->flags & MIPS_CPU_ASE_MIPS3D))
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&& file_mips_fp32 == 0) ? 1 : 0;
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if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
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as_bad (_("-mfp32 used with -mips3d"));
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if (mips_opts.ase_mdmx == -1)
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mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0;
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mips_opts.ase_mdmx = ((CPU_HAS_MDMX (file_mips_arch)
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|| (arch_info->flags & MIPS_CPU_ASE_MDMX))
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&& file_mips_fp32 == 0) ? 1 : 0;
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if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
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as_bad (_("-mfp32 used with -mdmx"));
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if (mips_opts.ase_smartmips == -1)
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mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
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if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
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as_warn ("%s ISA does not support SmartMIPS",
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mips_cpu_info_from_isa (mips_opts.isa)->name);
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if (mips_opts.ase_dsp == -1)
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mips_opts.ase_dsp = (CPU_HAS_DSP (file_mips_arch)) ? 1 : 0;
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mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
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if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
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as_warn ("%s ISA does not support DSP ASE",
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mips_cpu_info_from_isa (mips_opts.isa)->name);
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if (mips_opts.ase_mt == -1)
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mips_opts.ase_mt = (CPU_HAS_MT (file_mips_arch)) ? 1 : 0;
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mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
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if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
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as_warn ("%s ISA does not support MT ASE",
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mips_cpu_info_from_isa (mips_opts.isa)->name);
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file_mips_isa = mips_opts.isa;
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file_ase_mips16 = mips_opts.mips16;
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@ -12266,6 +12346,28 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
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{
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mips_opts.nobopt = 1;
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}
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else if (strcmp (name, "gp=default") == 0)
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mips_opts.gp32 = file_mips_gp32;
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else if (strcmp (name, "gp=32") == 0)
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mips_opts.gp32 = 1;
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else if (strcmp (name, "gp=64") == 0)
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{
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if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
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as_warn ("%s isa does not support 64-bit registers",
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mips_cpu_info_from_isa (mips_opts.isa)->name);
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mips_opts.gp32 = 0;
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}
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else if (strcmp (name, "fp=default") == 0)
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mips_opts.fp32 = file_mips_fp32;
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else if (strcmp (name, "fp=32") == 0)
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mips_opts.fp32 = 1;
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else if (strcmp (name, "fp=64") == 0)
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{
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if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
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as_warn ("%s isa does not support 64-bit floating point registers",
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mips_cpu_info_from_isa (mips_opts.isa)->name);
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mips_opts.fp32 = 0;
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}
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else if (strcmp (name, "mips16") == 0
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|| strcmp (name, "MIPS-16") == 0)
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mips_opts.mips16 = 1;
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@ -12274,7 +12376,7 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
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mips_opts.mips16 = 0;
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else if (strcmp (name, "smartmips") == 0)
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{
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if (!ISA_SUPPORT_SMARTMIPS)
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if (!ISA_SUPPORTS_SMARTMIPS)
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as_warn ("%s ISA does not support SmartMIPS ASE",
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mips_cpu_info_from_isa (mips_opts.isa)->name);
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mips_opts.ase_smartmips = 1;
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@ -12290,11 +12392,21 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
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else if (strcmp (name, "nomdmx") == 0)
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mips_opts.ase_mdmx = 0;
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else if (strcmp (name, "dsp") == 0)
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mips_opts.ase_dsp = 1;
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{
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if (!ISA_SUPPORTS_DSP_ASE)
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as_warn ("%s ISA does not support DSP ASE",
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mips_cpu_info_from_isa (mips_opts.isa)->name);
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mips_opts.ase_dsp = 1;
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}
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else if (strcmp (name, "nodsp") == 0)
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mips_opts.ase_dsp = 0;
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else if (strcmp (name, "mt") == 0)
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mips_opts.ase_mt = 1;
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{
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if (!ISA_SUPPORTS_MT_ASE)
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as_warn ("%s ISA does not support MT ASE",
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mips_cpu_info_from_isa (mips_opts.isa)->name);
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mips_opts.ase_mt = 1;
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}
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else if (strcmp (name, "nomt") == 0)
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mips_opts.ase_mt = 0;
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else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
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@ -14012,6 +14124,12 @@ mips_elf_final_processing (void)
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if (mips_32bitmode)
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elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
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#if 0 /* XXX FIXME */
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/* 32 bit code with 64 bit FP registers. */
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if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
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elf_elfheader (stdoutput)->e_flags |= ???;
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#endif
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}
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#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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@ -14414,72 +14532,90 @@ s_mips_mask (int reg_type)
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static const struct mips_cpu_info mips_cpu_info_table[] =
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{
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/* Entries for generic ISAs */
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{ "mips1", 1, ISA_MIPS1, CPU_R3000 },
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{ "mips2", 1, ISA_MIPS2, CPU_R6000 },
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{ "mips3", 1, ISA_MIPS3, CPU_R4000 },
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{ "mips4", 1, ISA_MIPS4, CPU_R8000 },
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{ "mips5", 1, ISA_MIPS5, CPU_MIPS5 },
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{ "mips32", 1, ISA_MIPS32, CPU_MIPS32 },
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{ "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "mips64", 1, ISA_MIPS64, CPU_MIPS64 },
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{ "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 },
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{ "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
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{ "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
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{ "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
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{ "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
|
||||
{ "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
|
||||
{ "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
|
||||
{ "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
|
||||
{ "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
|
||||
|
||||
/* MIPS I */
|
||||
{ "r3000", 0, ISA_MIPS1, CPU_R3000 },
|
||||
{ "r2000", 0, ISA_MIPS1, CPU_R3000 },
|
||||
{ "r3900", 0, ISA_MIPS1, CPU_R3900 },
|
||||
{ "r3000", 0, ISA_MIPS1, CPU_R3000 },
|
||||
{ "r2000", 0, ISA_MIPS1, CPU_R3000 },
|
||||
{ "r3900", 0, ISA_MIPS1, CPU_R3900 },
|
||||
|
||||
/* MIPS II */
|
||||
{ "r6000", 0, ISA_MIPS2, CPU_R6000 },
|
||||
{ "r6000", 0, ISA_MIPS2, CPU_R6000 },
|
||||
|
||||
/* MIPS III */
|
||||
{ "r4000", 0, ISA_MIPS3, CPU_R4000 },
|
||||
{ "r4010", 0, ISA_MIPS2, CPU_R4010 },
|
||||
{ "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
|
||||
{ "vr4111", 0, ISA_MIPS3, CPU_R4111 },
|
||||
{ "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
|
||||
{ "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
|
||||
{ "vr4181", 0, ISA_MIPS3, CPU_R4111 },
|
||||
{ "vr4300", 0, ISA_MIPS3, CPU_R4300 },
|
||||
{ "r4400", 0, ISA_MIPS3, CPU_R4400 },
|
||||
{ "r4600", 0, ISA_MIPS3, CPU_R4600 },
|
||||
{ "orion", 0, ISA_MIPS3, CPU_R4600 },
|
||||
{ "r4650", 0, ISA_MIPS3, CPU_R4650 },
|
||||
{ "r4000", 0, ISA_MIPS3, CPU_R4000 },
|
||||
{ "r4010", 0, ISA_MIPS2, CPU_R4010 },
|
||||
{ "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
|
||||
{ "vr4111", 0, ISA_MIPS3, CPU_R4111 },
|
||||
{ "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
|
||||
{ "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
|
||||
{ "vr4181", 0, ISA_MIPS3, CPU_R4111 },
|
||||
{ "vr4300", 0, ISA_MIPS3, CPU_R4300 },
|
||||
{ "r4400", 0, ISA_MIPS3, CPU_R4400 },
|
||||
{ "r4600", 0, ISA_MIPS3, CPU_R4600 },
|
||||
{ "orion", 0, ISA_MIPS3, CPU_R4600 },
|
||||
{ "r4650", 0, ISA_MIPS3, CPU_R4650 },
|
||||
|
||||
/* MIPS IV */
|
||||
{ "r8000", 0, ISA_MIPS4, CPU_R8000 },
|
||||
{ "r10000", 0, ISA_MIPS4, CPU_R10000 },
|
||||
{ "r12000", 0, ISA_MIPS4, CPU_R12000 },
|
||||
{ "vr5000", 0, ISA_MIPS4, CPU_R5000 },
|
||||
{ "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
|
||||
{ "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
|
||||
{ "rm5200", 0, ISA_MIPS4, CPU_R5000 },
|
||||
{ "rm5230", 0, ISA_MIPS4, CPU_R5000 },
|
||||
{ "rm5231", 0, ISA_MIPS4, CPU_R5000 },
|
||||
{ "rm5261", 0, ISA_MIPS4, CPU_R5000 },
|
||||
{ "rm5721", 0, ISA_MIPS4, CPU_R5000 },
|
||||
{ "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
|
||||
{ "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
|
||||
{ "r8000", 0, ISA_MIPS4, CPU_R8000 },
|
||||
{ "r10000", 0, ISA_MIPS4, CPU_R10000 },
|
||||
{ "r12000", 0, ISA_MIPS4, CPU_R12000 },
|
||||
{ "vr5000", 0, ISA_MIPS4, CPU_R5000 },
|
||||
{ "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
|
||||
{ "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
|
||||
{ "rm5200", 0, ISA_MIPS4, CPU_R5000 },
|
||||
{ "rm5230", 0, ISA_MIPS4, CPU_R5000 },
|
||||
{ "rm5231", 0, ISA_MIPS4, CPU_R5000 },
|
||||
{ "rm5261", 0, ISA_MIPS4, CPU_R5000 },
|
||||
{ "rm5721", 0, ISA_MIPS4, CPU_R5000 },
|
||||
{ "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
|
||||
{ "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
|
||||
|
||||
/* MIPS 32 */
|
||||
{ "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
|
||||
{ "4km", 0, ISA_MIPS32, CPU_MIPS32 },
|
||||
{ "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
|
||||
{ "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
|
||||
{ "4km", 0, ISA_MIPS32, CPU_MIPS32 },
|
||||
{ "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
|
||||
{ "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
|
||||
|
||||
/* MIPS32 Release 2 */
|
||||
{ "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "24k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
/* MIPS 32 Release 2 */
|
||||
{ "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "24k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
/* 24ke is a 24k with DSP ASE, other ASEs are optional. */
|
||||
{ "24ke", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
/* 34k is a 24k with MT ASE, other ASEs are optional. */
|
||||
{ "34kc", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "34kf", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "34kx", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
|
||||
/* MIPS 64 */
|
||||
{ "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
|
||||
{ "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
|
||||
{ "20kc", 0, ISA_MIPS64, CPU_MIPS64 },
|
||||
{ "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
|
||||
{ "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
|
||||
{ "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
|
||||
|
||||
/* MIPS 64 Release 2 */
|
||||
{ "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64R2, CPU_MIPS64R2 },
|
||||
|
||||
/* Broadcom SB-1 CPU core */
|
||||
{ "sb1", 0, ISA_MIPS64, CPU_SB1 },
|
||||
{ "sb1", 0, ISA_MIPS64, CPU_SB1 },
|
||||
|
||||
/* End marker */
|
||||
{ NULL, 0, 0, 0 }
|
||||
|
|
@ -14594,7 +14730,7 @@ mips_cpu_info_from_isa (int isa)
|
|||
int i;
|
||||
|
||||
for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
|
||||
if (mips_cpu_info_table[i].is_isa
|
||||
if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
|
||||
&& isa == mips_cpu_info_table[i].isa)
|
||||
return (&mips_cpu_info_table[i]);
|
||||
|
||||
|
|
|
|||
|
|
@ -91,19 +91,28 @@ flags force a certain group of registers to be treated as 32 bits wide at
|
|||
all times. @samp{-mgp32} controls the size of general-purpose registers
|
||||
and @samp{-mfp32} controls the size of floating-point registers.
|
||||
|
||||
The @code{.set gp=32} and @code{.set fp=32} directives allow the size
|
||||
of registers to be changed for parts of an object. The default value is
|
||||
restored by @code{.set gp=default} and @code{.set fp=default}.
|
||||
|
||||
On some MIPS variants there is a 32-bit mode flag; when this flag is
|
||||
set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
|
||||
save the 32-bit registers on a context switch, so it is essential never
|
||||
to use the 64-bit registers.
|
||||
|
||||
@item -mgp64
|
||||
Assume that 64-bit general purpose registers are available. This is
|
||||
provided in the interests of symmetry with -gp32.
|
||||
@itemx -mfp64
|
||||
Assume that 64-bit registers are available. This is provided in the
|
||||
interests of symmetry with @samp{-mgp32} and @samp{-mfp32}.
|
||||
|
||||
The @code{.set gp=64} and @code{.set fp=64} directives allow the size
|
||||
of registers to be changed for parts of an object. The default value is
|
||||
restored by @code{.set gp=default} and @code{.set fp=default}.
|
||||
|
||||
@item -mips16
|
||||
@itemx -no-mips16
|
||||
Generate code for the MIPS 16 processor. This is equivalent to putting
|
||||
@samp{.set mips16} at the start of the assembly file. @samp{-no-mips16}
|
||||
@code{.set mips16} at the start of the assembly file. @samp{-no-mips16}
|
||||
turns off this option.
|
||||
|
||||
@item -msmartmips
|
||||
|
|
@ -111,7 +120,7 @@ turns off this option.
|
|||
Enables the SmartMIPS extensions to the MIPS32 instruction set, which
|
||||
provides a number of new instructions which target smartcard and
|
||||
cryptographic applications. This is equivalent to putting
|
||||
@samp{.set smartmips} at the start of the assembly file.
|
||||
@code{.set smartmips} at the start of the assembly file.
|
||||
@samp{-mno-smartmips} turns off this option.
|
||||
|
||||
@item -mips3d
|
||||
|
|
@ -210,7 +219,29 @@ rm7000,
|
|||
rm9000,
|
||||
10000,
|
||||
12000,
|
||||
mips32-4k,
|
||||
4kc,
|
||||
4km,
|
||||
4kp,
|
||||
4ksc,
|
||||
4kec,
|
||||
4kem,
|
||||
4kep,
|
||||
4ksd,
|
||||
m4k,
|
||||
m4kp,
|
||||
24kc,
|
||||
24kf,
|
||||
24kx,
|
||||
24kec,
|
||||
24kef,
|
||||
24kex,
|
||||
34kc,
|
||||
34kf,
|
||||
34kx,
|
||||
5kc,
|
||||
5kf,
|
||||
20kc,
|
||||
25kf,
|
||||
sb1
|
||||
@end quotation
|
||||
|
||||
|
|
@ -399,17 +430,21 @@ assembly. @code{.set mips@var{n}} affects not only which instructions
|
|||
are permitted, but also how certain macros are expanded. @code{.set
|
||||
mips0} restores the @sc{isa} level to its original level: either the
|
||||
level you selected with command line options, or the default for your
|
||||
configuration. You can use this feature to permit specific @sc{r4000}
|
||||
configuration. You can use this feature to permit specific @sc{mips3}
|
||||
instructions while assembling in 32 bit mode. Use this directive with
|
||||
care!
|
||||
|
||||
The directive @samp{.set mips16} puts the assembler into MIPS 16 mode,
|
||||
in which it will assemble instructions for the MIPS 16 processor. Use
|
||||
@samp{.set nomips16} to return to normal 32 bit mode.
|
||||
@cindex MIPS CPU override
|
||||
@kindex @code{.set arch=@var{cpu}}
|
||||
The @code{.set arch=@var{cpu}} directive provides even finer control.
|
||||
It changes the effective CPU target and allows the assembler to use
|
||||
instructions specific to a particular CPU. All CPUs supported by the
|
||||
@samp{-march} command line option are also selectable by this directive.
|
||||
The original value is restored by @code{.set arch=default}.
|
||||
|
||||
The @samp{.set smartmips} directive enables use of the SmartMIPS
|
||||
extensions to the MIPS32 @sc{isa}; the @samp{.set nosmartmips} directive
|
||||
reverses that.
|
||||
The directive @code{.set mips16} puts the assembler into MIPS 16 mode,
|
||||
in which it will assemble instructions for the MIPS 16 processor. Use
|
||||
@code{.set nomips16} to return to normal 32 bit mode.
|
||||
|
||||
Traditional @sc{mips} assemblers do not support this directive.
|
||||
|
||||
|
|
@ -419,10 +454,10 @@ Traditional @sc{mips} assemblers do not support this directive.
|
|||
@kindex @code{.set autoextend}
|
||||
@kindex @code{.set noautoextend}
|
||||
By default, MIPS 16 instructions are automatically extended to 32 bits
|
||||
when necessary. The directive @samp{.set noautoextend} will turn this
|
||||
off. When @samp{.set noautoextend} is in effect, any 32 bit instruction
|
||||
must be explicitly extended with the @samp{.e} modifier (e.g.,
|
||||
@samp{li.e $4,1000}). The directive @samp{.set autoextend} may be used
|
||||
when necessary. The directive @code{.set noautoextend} will turn this
|
||||
off. When @code{.set noautoextend} is in effect, any 32 bit instruction
|
||||
must be explicitly extended with the @code{.e} modifier (e.g.,
|
||||
@code{li.e $4,1000}). The directive @code{.set autoextend} may be used
|
||||
to once again automatically extend instructions when necessary.
|
||||
|
||||
This directive is only meaningful when in MIPS 16 mode. Traditional
|
||||
|
|
@ -467,6 +502,15 @@ from the MIPS-3D Application Specific Extension from that point on
|
|||
in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D
|
||||
instructions from being accepted.
|
||||
|
||||
@cindex SmartMIPS instruction generation override
|
||||
@kindex @code{.set smartmips}
|
||||
@kindex @code{.set nosmartmips}
|
||||
The directive @code{.set smartmips} makes the assembler accept
|
||||
instructions from the SmartMIPS Application Specific Extension to the
|
||||
MIPS32 @sc{isa} from that point on in the assembly. The
|
||||
@code{.set nosmartmips} directive prevents SmartMIPS instructions from
|
||||
being accepted.
|
||||
|
||||
@cindex MIPS MDMX instruction generation override
|
||||
@kindex @code{.set mdmx}
|
||||
@kindex @code{.set nomdmx}
|
||||
|
|
|
|||
|
|
@ -1,3 +1,12 @@
|
|||
2006-05-23 Thiemo Seufer <ths@mips.com>
|
||||
|
||||
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
|
||||
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
|
||||
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
|
||||
output.
|
||||
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
|
||||
catch assembler warnings.
|
||||
|
||||
2006-05-22 Nick Clifton <nickc@redhat.com>
|
||||
|
||||
* gas/mips/mips32-dsp.l: Fix expected unsigned decoding of -1 in
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
#objdump: -d -mmips:8000
|
||||
#as: -32 -march=8000 -EB -mgp32 -mfp64 -KPIC
|
||||
#name: MIPS -mgp32 -mfp64 (SVR4 PIC)
|
||||
#stderr: mips-gp32-fp64.l
|
||||
|
||||
.*: +file format.*
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
#objdump: -d -mmips:8000
|
||||
#as: -32 -march=8000 -EB -mgp32 -mfp64
|
||||
#name: MIPS -mgp32 -mfp64
|
||||
#stderr: mips-gp32-fp64.l
|
||||
|
||||
.*: +file format.*
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,2 @@
|
|||
Assembler messages:
|
||||
Warning: -mfp64 used with a 32-bit ABI
|
||||
|
|
@ -1,6 +1,7 @@
|
|||
#objdump: -d -mmips:8000
|
||||
#as: -mabi=o64 -march=8000 -EB -mfp32 -KPIC
|
||||
#name: MIPS -mgp64 -mfp32 (SVR4 PIC)
|
||||
#stderr: mips-gp64-fp32-pic.l
|
||||
|
||||
.*: +file format.*
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,2 @@
|
|||
Assembler messages:
|
||||
Warning: -mfp32 used with a 64-bit ABI
|
||||
|
|
@ -1,4 +1,5 @@
|
|||
.*: Assembler messages:
|
||||
Assembler messages:
|
||||
Warning: -mfp32 used with a 64-bit ABI
|
||||
.*:92: Warning: Macro instruction expanded into multiple instructions in a branch delay slot
|
||||
.*:96: Warning: Macro instruction expanded into multiple instructions in a branch delay slot
|
||||
.*:100: Warning: Macro instruction expanded into multiple instructions in a branch delay slot
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#objdump: -d -mmips:8000
|
||||
#as: -mabi=o64 -march=8000 -EB
|
||||
#name: MIPS -mgp64 -mfp64
|
||||
#stderr: mips-gp64-fp32.l
|
||||
#stderr: mips-gp64-fp64.l
|
||||
|
||||
.*: +file format.*
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue