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Reorder invalid default mask check 

gas/

2013-11-15  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>

	* config/tc-i386.c (check_VecOperands): Reorder checks.

gas/testsuite/

2013-11-15  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>

	* gas/i386/inval-avx512f.s: Add invalid test for gather instruction
	with default mask.
	* gas/i386/inval-avx512f.l: Update correspondingly.
This commit is contained in:
Michael Zolotukhin 2013-11-15 05:22:32 -08:00 committed by H.J. Lu
parent 9abb1bd666
commit ad8ecc8114
5 changed files with 57 additions and 37 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
gas/ChangeLog
View File

@ -1,3 +1,7 @@
2013-11-15 Michael Zolotukhin <michael.v.zolotukhin@gmail.com>
* config/tc-i386.c (check_VecOperands): Reorder checks.
2013-11-11 Catherine Moore <clm@codesourcery.com>
* config/mips/tc-mips.c (convert_reg_type): Use

16
gas/config/tc-i386.c
View File

@ -4345,6 +4345,14 @@ check_VecOperands (const insn_template *t)
return 1;
}
/* Check if default mask is allowed. */
if (t->opcode_modifier.nodefmask
&& (!i.mask || i.mask->mask->reg_num == 0))
{
i.error = no_default_mask;
return 1;
}
/* For VSIB byte, we need a vector register for index, and all vector
registers must be distinct. */
if (t->opcode_modifier.vecsib)
@ -4462,14 +4470,6 @@ check_VecOperands (const insn_template *t)
return 1;
}
/* Check if default mask is allowed. */
if (t->opcode_modifier.nodefmask
&& (!i.mask || i.mask->mask->reg_num == 0))
{
i.error = no_default_mask;
return 1;
}
/* Check RC/SAE. */
if (i.rounding)
{

6
gas/testsuite/ChangeLog
View File

@ -1,3 +1,9 @@
2013-11-15 Michael Zolotukhin <michael.v.zolotukhin@gmail.com>
* gas/i386/inval-avx512f.s: Add invalid test for gather instruction
with default mask.
* gas/i386/inval-avx512f.l: Update correspondingly.
2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
* gas/aarch64/deprecated.d: New file.

64
gas/testsuite/gas/i386/inval-avx512f.l
View File

@ -9,26 +9,28 @@
.*:12: Error: .*
.*:14: Error: .*
.*:15: Error: .*
.*:18: Error: .*
.*:19: Error: .*
.*:17: Error: .*
.*:20: Error: .*
.*:21: Error: .*
.*:21: Error: .*
.*:22: Error: .*
.*:22: Error: .*
.*:23: Error: .*
.*:23: Error: .*
.*:24: Error: .*
.*:24: Error: .*
.*:25: Error: .*
.*:26: Error: .*
.*:25: Error: .*
.*:27: Error: .*
.*:28: Error: .*
.*:29: Error: .*
.*:30: Error: .*
.*:31: Error: .*
.*:32: Error: .*
.*:33: Error: .*
.*:34: Error: .*
.*:35: Error: .*
.*:36: Error: .*
.*:37: Error: .*
.*:38: Error: .*
.*:39: Error: .*
.*:40: Error: .*
.*:41: Error: .*
GAS LISTING .*
@ -48,24 +50,28 @@ GAS LISTING .*
[ ]*14[ ]+vcvtps2pd \(%eax\)\{%k1\}, %zmm1
[ ]*15[ ]+vcvtps2pd \(%eax\)\{z\}, %zmm1
[ ]*16[ ]+
[ ]*17[ ]+\.intel_syntax noprefix
[ ]*18[ ]+mov eax\{k1\}, \{sae\}
[ ]*19[ ]+mov eax, \{sae\}
[ ]*20[ ]+mov eax\{k2\}, ebx
[ ]*21[ ]+vaddps zmm2\{z\}\{k1\}\{z\}, zmm1, zmm3
[ ]*22[ ]+vaddps zmm2\{z\}, zmm1\{k3\}, zmm3
[ ]*23[ ]+vaddps zmm2\{k2\}, zmm1\{k1\}, zmm3
[ ]*24[ ]+
[ ]*25[ ]+vcvtps2pd zmm1\{1to8\}, \[eax\]
[ ]*26[ ]+vcvtps2pd zmm1, \[eax\]\{1to16\}
[ ]*27[ ]+
[ ]*28[ ]+vcvtps2pd zmm1, \[eax\]\{k1\}
[ ]*29[ ]+vcvtps2pd zmm1, \[eax\]\{z\}
[ ]*30[ ]+
[ ]*31[ ]+vaddps zmm2, zmm1, QWORD PTR \[eax\]\{1to8\}
[ ]*32[ ]+vaddps zmm2, zmm1, QWORD PTR \[eax\]\{1to16\}
[ ]*33[ ]+vaddpd zmm2, zmm1, DWORD PTR \[eax\]\{1to8\}
[ ]*34[ ]+vaddpd zmm2, zmm1, DWORD PTR \[eax\]\{1to16\}
[ ]*35[ ]+vaddps zmm2, zmm1, ZMMWORD PTR \[eax\]\{1to16\}
[ ]*36[ ]+vaddps zmm2, zmm1, DWORD PTR \[eax\]
[ ]*37[ ]+vaddpd zmm2, zmm1, QWORD PTR \[eax\]
[ ]*17[ ]+vgatherqpd \(%rdi,%zmm2,8\),%zmm6
[ ]*18[ ]+
[ ]*19[ ]+\.intel_syntax noprefix
[ ]*20[ ]+mov eax\{k1\}, \{sae\}
[ ]*21[ ]+mov eax, \{sae\}
[ ]*22[ ]+mov eax\{k2\}, ebx
[ ]*23[ ]+vaddps zmm2\{z\}\{k1\}\{z\}, zmm1, zmm3
[ ]*24[ ]+vaddps zmm2\{z\}, zmm1\{k3\}, zmm3
[ ]*25[ ]+vaddps zmm2\{k2\}, zmm1\{k1\}, zmm3
[ ]*26[ ]+
[ ]*27[ ]+vcvtps2pd zmm1\{1to8\}, \[eax\]
[ ]*28[ ]+vcvtps2pd zmm1, \[eax\]\{1to16\}
[ ]*29[ ]+
[ ]*30[ ]+vcvtps2pd zmm1, \[eax\]\{k1\}
[ ]*31[ ]+vcvtps2pd zmm1, \[eax\]\{z\}
[ ]*32[ ]+
[ ]*33[ ]+vgatherqpd zmm6, ZMMWORD PTR \[rdi\+zmm2\*8\]
[ ]*34[ ]+
[ ]*35[ ]+vaddps zmm2, zmm1, QWORD PTR \[eax\]\{1to8\}
[ ]*36[ ]+vaddps zmm2, zmm1, QWORD PTR \[eax\]\{1to16\}
[ ]*37[ ]+vaddpd zmm2, zmm1, DWORD PTR \[eax\]\{1to8\}
[ ]*38[ ]+vaddpd zmm2, zmm1, DWORD PTR \[eax\]\{1to16\}
[ ]*39[ ]+vaddps zmm2, zmm1, ZMMWORD PTR \[eax\]\{1to16\}
[ ]*40[ ]+vaddps zmm2, zmm1, DWORD PTR \[eax\]
[ ]*41[ ]+vaddpd zmm2, zmm1, QWORD PTR \[eax\]

4
gas/testsuite/gas/i386/inval-avx512f.s
View File

@ -14,6 +14,8 @@ _start:
vcvtps2pd (%eax){%k1}, %zmm1
vcvtps2pd (%eax){z}, %zmm1
vgatherqpd (%rdi,%zmm2,8),%zmm6
.intel_syntax noprefix
mov eax{k1}, {sae}
mov eax, {sae}
@ -28,6 +30,8 @@ _start:
vcvtps2pd zmm1, [eax]{k1}
vcvtps2pd zmm1, [eax]{z}
vgatherqpd zmm6, ZMMWORD PTR [rdi+zmm2*8]
vaddps zmm2, zmm1, QWORD PTR [eax]{1to8}
vaddps zmm2, zmm1, QWORD PTR [eax]{1to16}
vaddpd zmm2, zmm1, DWORD PTR [eax]{1to8}