[binutils][aarch64] Introduce SVE_IMM_ROT3 operand.
New operand AARCH64_OPND_SVE_IMM_ROT3 handles a single bit rotate operand encoded at bit position 10. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_IMM_ROT3 operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_IMM_ROT3 operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_IMM_ROT3. (aarch64_print_operand): Add printing for SVE_IMM_ROT3. (fields): Handle SVE_rot3 field. * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
This commit is contained in:
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5cd9975095
commit
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@ -1,3 +1,7 @@
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2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
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* config/tc-aarch64.c (parse_operands): Handle new SVE_IMM_ROT3 operand.
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2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
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* config/tc-aarch64.c: Add command line architecture feature flags
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@ -5782,6 +5782,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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case AARCH64_OPND_IMM_ROT3:
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case AARCH64_OPND_SVE_IMM_ROT1:
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case AARCH64_OPND_SVE_IMM_ROT2:
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case AARCH64_OPND_SVE_IMM_ROT3:
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po_imm_nc_or_fail ();
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info->imm.value = val;
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break;
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@ -1,3 +1,7 @@
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2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
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* opcode/aarch64.h (enum aarch64_opnd): New SVE_IMM_ROT3 operand.
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2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
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* opcode/aarch64.h (AARCH64_FEATURE_SVE2
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@ -372,6 +372,7 @@ enum aarch64_opnd
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AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
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AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */
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AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */
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AARCH64_OPND_SVE_IMM_ROT3, /* SVE cadd 1-bit rotate (90 or 270). */
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AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
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AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
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AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */
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@ -1,3 +1,15 @@
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2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
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* aarch64-asm-2.c: Regenerated.
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* aarch64-dis-2.c: Regenerated.
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* aarch64-opc-2.c: Regenerated.
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* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
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for SVE_IMM_ROT3.
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(aarch64_print_operand): Add printing for SVE_IMM_ROT3.
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(fields): Handle SVE_rot3 field.
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* aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
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* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
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2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
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* aarch64-opc.c (verify_constraints): Check for movprfx for sve2
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@ -628,7 +628,6 @@ aarch64_insert_operand (const aarch64_operand *self,
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case 28:
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case 29:
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case 30:
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case 160:
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case 161:
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case 162:
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case 163:
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@ -638,7 +637,7 @@ aarch64_insert_operand (const aarch64_operand *self,
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case 167:
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case 168:
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case 169:
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case 182:
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case 170:
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case 183:
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case 184:
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case 185:
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@ -647,8 +646,9 @@ aarch64_insert_operand (const aarch64_operand *self,
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case 188:
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case 189:
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case 190:
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case 194:
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case 197:
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case 191:
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case 195:
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case 198:
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return aarch64_ins_regno (self, info, code, inst, errors);
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case 14:
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return aarch64_ins_reg_extended (self, info, code, inst, errors);
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@ -660,7 +660,7 @@ aarch64_insert_operand (const aarch64_operand *self,
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case 32:
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case 33:
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case 34:
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case 200:
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case 201:
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return aarch64_ins_reglane (self, info, code, inst, errors);
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case 35:
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return aarch64_ins_reglist (self, info, code, inst, errors);
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@ -694,9 +694,8 @@ aarch64_insert_operand (const aarch64_operand *self,
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case 80:
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case 81:
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case 82:
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case 157:
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case 159:
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case 174:
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case 158:
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case 160:
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case 175:
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case 176:
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case 177:
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@ -704,7 +703,8 @@ aarch64_insert_operand (const aarch64_operand *self,
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case 179:
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case 180:
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case 181:
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case 199:
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case 182:
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case 200:
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return aarch64_ins_imm (self, info, code, inst, errors);
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case 43:
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case 44:
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@ -717,7 +717,7 @@ aarch64_insert_operand (const aarch64_operand *self,
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case 148:
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return aarch64_ins_fpimm (self, info, code, inst, errors);
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case 68:
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case 155:
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case 156:
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return aarch64_ins_limm (self, info, code, inst, errors);
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case 69:
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return aarch64_ins_aimm (self, info, code, inst, errors);
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@ -731,6 +731,7 @@ aarch64_insert_operand (const aarch64_operand *self,
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return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
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case 75:
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case 152:
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case 154:
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return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
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case 76:
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case 77:
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@ -832,26 +833,26 @@ aarch64_insert_operand (const aarch64_operand *self,
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return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
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case 151:
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return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
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case 154:
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case 155:
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return aarch64_ins_inv_limm (self, info, code, inst, errors);
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case 156:
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case 157:
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return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
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case 158:
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case 159:
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return aarch64_ins_sve_scale (self, info, code, inst, errors);
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case 170:
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case 171:
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return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
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case 172:
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return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
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case 173:
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case 174:
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return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
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case 191:
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case 192:
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case 193:
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case 194:
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return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
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case 195:
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return aarch64_ins_sve_index (self, info, code, inst, errors);
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case 196:
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case 198:
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return aarch64_ins_sve_index (self, info, code, inst, errors);
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case 197:
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case 199:
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return aarch64_ins_sve_reglist (self, info, code, inst, errors);
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default: assert (0); abort ();
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}
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@ -20059,7 +20059,6 @@ aarch64_extract_operand (const aarch64_operand *self,
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case 28:
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case 29:
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case 30:
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case 160:
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case 161:
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case 162:
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case 163:
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@ -20069,7 +20068,7 @@ aarch64_extract_operand (const aarch64_operand *self,
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case 167:
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case 168:
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case 169:
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case 182:
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case 170:
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case 183:
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case 184:
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case 185:
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@ -20078,8 +20077,9 @@ aarch64_extract_operand (const aarch64_operand *self,
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case 188:
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case 189:
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case 190:
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case 194:
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case 197:
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case 191:
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case 195:
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case 198:
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return aarch64_ext_regno (self, info, code, inst, errors);
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case 9:
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return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
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@ -20095,7 +20095,7 @@ aarch64_extract_operand (const aarch64_operand *self,
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case 32:
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case 33:
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case 34:
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case 200:
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case 201:
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return aarch64_ext_reglane (self, info, code, inst, errors);
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case 35:
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return aarch64_ext_reglist (self, info, code, inst, errors);
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@ -20130,9 +20130,8 @@ aarch64_extract_operand (const aarch64_operand *self,
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case 80:
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case 81:
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case 82:
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case 157:
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case 159:
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case 174:
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case 158:
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case 160:
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case 175:
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case 176:
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case 177:
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@ -20140,7 +20139,8 @@ aarch64_extract_operand (const aarch64_operand *self,
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case 179:
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case 180:
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case 181:
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case 199:
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case 182:
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case 200:
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return aarch64_ext_imm (self, info, code, inst, errors);
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case 43:
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case 44:
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@ -20155,7 +20155,7 @@ aarch64_extract_operand (const aarch64_operand *self,
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case 148:
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return aarch64_ext_fpimm (self, info, code, inst, errors);
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case 68:
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case 155:
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case 156:
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return aarch64_ext_limm (self, info, code, inst, errors);
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case 69:
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return aarch64_ext_aimm (self, info, code, inst, errors);
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@ -20169,6 +20169,7 @@ aarch64_extract_operand (const aarch64_operand *self,
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return aarch64_ext_imm_rotate2 (self, info, code, inst, errors);
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case 75:
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case 152:
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case 154:
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return aarch64_ext_imm_rotate1 (self, info, code, inst, errors);
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case 76:
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case 77:
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return aarch64_ext_sve_float_half_two (self, info, code, inst, errors);
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case 151:
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return aarch64_ext_sve_float_zero_one (self, info, code, inst, errors);
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case 154:
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case 155:
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return aarch64_ext_inv_limm (self, info, code, inst, errors);
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case 156:
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case 157:
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return aarch64_ext_sve_limm_mov (self, info, code, inst, errors);
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case 158:
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case 159:
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return aarch64_ext_sve_scale (self, info, code, inst, errors);
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case 170:
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case 171:
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return aarch64_ext_sve_shlimm (self, info, code, inst, errors);
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case 172:
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return aarch64_ext_sve_shlimm (self, info, code, inst, errors);
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case 173:
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case 174:
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return aarch64_ext_sve_shrimm (self, info, code, inst, errors);
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case 191:
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case 192:
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case 193:
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case 194:
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return aarch64_ext_sve_quad_index (self, info, code, inst, errors);
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case 195:
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return aarch64_ext_sve_index (self, info, code, inst, errors);
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case 196:
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case 198:
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return aarch64_ext_sve_index (self, info, code, inst, errors);
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case 197:
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case 199:
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return aarch64_ext_sve_reglist (self, info, code, inst, errors);
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default: assert (0); abort ();
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}
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@ -178,6 +178,7 @@ const struct aarch64_operand aarch64_operands[] =
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{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_ZERO_ONE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i1}, "either 0.0 or 1.0"},
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{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_rot1}, "a 1-bit rotation specifier for complex arithmetic operations"},
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{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_rot2}, "a 2-bit rotation specifier for complex arithmetic operations"},
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{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_rot3}, "a 1-bit rotation specifier for complex arithmetic operations"},
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{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_INV_LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms}, "an inverted 13-bit logical immediate"},
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{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms}, "a 13-bit logical immediate"},
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{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_LIMM_MOV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms}, "a 13-bit logical move immediate"},
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@ -309,6 +309,7 @@ const aarch64_field fields[] =
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{ 0, 4 }, /* SVE_prfop: prefetch operation for SVE PRF[BHWD]. */
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{ 16, 1 }, /* SVE_rot1: 1-bit rotation amount. */
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{ 10, 2 }, /* SVE_rot2: 2-bit rotation amount. */
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{ 10, 1 }, /* SVE_rot3: 1-bit rotation amount at bit 10. */
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{ 22, 1 }, /* SVE_sz: 1-bit element size select. */
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{ 16, 4 }, /* SVE_tsz: triangular size select. */
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{ 22, 2 }, /* SVE_tszh: triangular size select high, bits [23,22]. */
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case AARCH64_OPND_IMM_ROT3:
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case AARCH64_OPND_SVE_IMM_ROT1:
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case AARCH64_OPND_SVE_IMM_ROT3:
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if (opnd->imm.value != 90 && opnd->imm.value != 270)
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{
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set_other_error (mismatch_detail, idx,
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case AARCH64_OPND_IMM_ROT3:
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case AARCH64_OPND_SVE_IMM_ROT1:
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case AARCH64_OPND_SVE_IMM_ROT2:
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case AARCH64_OPND_SVE_IMM_ROT3:
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snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
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break;
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@ -136,6 +136,7 @@ enum aarch64_field_kind
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FLD_SVE_prfop,
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FLD_SVE_rot1,
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FLD_SVE_rot2,
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FLD_SVE_rot3,
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FLD_SVE_sz,
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FLD_SVE_tsz,
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FLD_SVE_tszh,
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@ -4879,6 +4879,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
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"a 1-bit rotation specifier for complex arithmetic operations") \
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Y(IMMEDIATE, imm_rotate2, "SVE_IMM_ROT2", 0, F(FLD_SVE_rot2), \
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"a 2-bit rotation specifier for complex arithmetic operations") \
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Y(IMMEDIATE, imm_rotate1, "SVE_IMM_ROT3", 0, F(FLD_SVE_rot3), \
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"a 1-bit rotation specifier for complex arithmetic operations") \
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Y(IMMEDIATE, inv_limm, "SVE_INV_LIMM", 0, \
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F(FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms), \
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"an inverted 13-bit logical immediate") \
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